JPS6012762A - Photoelectric conversion device - Google Patents

Abstract

PURPOSE:To obtain the titled device sufficiently realizing high resolution by a method wherein the potential of a control electrode region of floating state provided in a semiconductor transistor is controlled via capacitor, where the potential is controlled by means of an IGFET constituting the device during the action of carrier accumulation, read-out, and refreshing. CONSTITUTION:An n<-> type layer 5 is epitaxially grown on an n<+> type Si substrate 1 and then formed into island form by means of an element isolation region 4 made of an insulation film, where the base region 6 of a p type bi-polar transistor is diffusion-formed, and an n<+> type emitter region 7 is provided therein. Next, the entire surface is covered with an SiO2 film 3, a window being opened, and an Al wiring 8 contacting the region 7 being formed. An electrode 9 is provided on the region 6 via film 3, and an Al wirng 10 is installed. An SiO2 film 2 is adhered over the entire surface, and an Al collector electrode 12 is adhered to the back surface of a substrate 1 via n<+> type layer 11. In this construction, the base region 6 is kept in floating state and then the surface of the device is irradiated with a light 20 while the potential of the electrode 9 is controlled by the impression of pulses via capacitor generating in the element.

Description

[Detailed description of the invention] The present invention relates to a photoelectric conversion device.

In recent years, research on photoelectric conversion devices, especially solid-state imaging devices, has been
With the progress of semiconductor technology, this has been actively carried out, and in some cases it has begun to be put into practical use.

These solid-state imaging devices can be roughly divided into CCD type and M
It is classified into two types of OS. The CCD type imaging device is MO
A potential well is formed under the S capacitor electrode, and charges generated by incident light are accumulated in this well. During readout, these potential wells are sequentially moved by a pulse applied to the electrode to collect the accumulated charges. The principle is that the data is transferred to the output amplifier section and read out. Furthermore, some CCD type imaging devices use a pn junction diode structure for the light receiving section and a COD structure for the transfer section. On the other hand, in a MOS type imaging device, charges generated by incident light are accumulated in each of the photodiodes made of pn junctions that constitute the light receiving section, and when reading out, the MOS switching transistors connected to each photodiode are sequentially activated. It uses the principle that by turning on, the accumulated charge is read out to the output amplifier section.

The CCD type imaging device has a relatively simple structure, and
Considering the noise that can be generated, only the capacitance value of the charge detector consisting of the floating diffusion in the final stage contributes to random noise, so it is a relatively low-noise imaging device and is capable of low-light imaging. However, CCD
Due to process constraints for manufacturing a type imaging device, a MOS type amplifier is installed on-chip as an output amplifier, so the interface between the silicon and the SiO2 film is easily visible on the image1.
/f noise occurs. Therefore, although it is said to have low noise,
There are limits to its performance. Furthermore, if the number of cells is increased to achieve higher density in order to achieve higher resolution, the maximum amount of charge that can be stored in one potential well will decrease, making it impossible to maintain a dynamic range. This will be a big problem as it becomes more and more popular. In addition, since a CCD type imaging device transfers accumulated charges while sequentially moving potential wells,
Another drawback is that even if a defect exists in one of the cells, charge transfer will stop there or become extremely poor, resulting in poor manufacturing yield.

On the other hand, MOS type imaging devices are structurally a little more complex than CCD type imaging devices, especially frame transfer type devices, but they can be configured to increase storage capacity.
It has the advantage of having a wide dynamic range.

Furthermore, even if one of the cells has a defect, because of the X-Y addressing method, the defect does not affect other cells, which is advantageous in terms of manufacturing yield. However, in this MOS type imaging device, wiring capacitance is connected to each photodiode during signal readout, so an extremely large signal voltage drop occurs, resulting in a drop in the output voltage, and the wiring capacitance is large, resulting in random noise. CCD
Compared to conventional imaging devices, these devices have drawbacks such as difficulty in low-light photography.

Furthermore, in the future, as the resolution of imaging devices increases, the size of each cell will be reduced and the amount of accumulated charge will decrease. On the other hand, the wiring capacitance, which is determined by the chip size, does not decrease much even if the line width is made thinner. For this reason, the MOS type imaging device becomes increasingly disadvantageous in terms of S/N.

Although CCD type and MOS type image pickup devices have the above-mentioned advantages and disadvantages, they are gradually approaching the level of practical use. However, it can be said that there are essentially major problems in promoting the higher resolution that will be required in the future.

Regarding those solid-state imaging devices, Japanese Patent Application Laid-Open No. 58-15087
8 "Semiconductor Imaging Device", Japanese Patent Application Laid-open No. 56-157073 "Semiconductor Imaging Device", and Japanese Patent Application Laid-Open No. 56-165473 "Semiconductor Imaging Device". CCD type, M
While an OS-type imaging device stores charges generated by incident light on the main electrode (for example, the source of a MOS transistor), the method proposed here stores charges generated due to incident light on the control electrode. It is based on a new concept of controlling the flowing current by the charges accumulated in the base of a bipolar transistor (for example, the gate of a SIT (static induction transistor) or MOS transistor) and generated by light. That is, C
While the CD type and MOS type read out the accumulated charge itself to the outside, the method proposed here amplifies the charge using the amplification function of each cell and then reads out the accumulated charge. So, looking at it from another perspective, it is read out as a low impedance output by impedance conversion. Therefore, the method proposed here has high output, wide dynamic range, and low noise, and since carriers (charges) excited by optical signals are accumulated in the control electrode, non-destructive readout is possible. It has several advantages. Furthermore, it can be said that this method has the potential for higher resolution in the future.

However, this method is basically an X-Y address method, and the element structure described in the above publication combines amplification elements such as bipolar transistors and SIT transistors in each cell of a conventional MOS type imaging device. The basic structure is as follows. Therefore, it has a relatively complicated structure, and although it has the possibility of achieving high resolution, there is a limit to how high resolution can be achieved as it is.

An object of the present invention is to provide a new photoelectric conversion device that has an amplification function in each cell but has an extremely simple structure and can sufficiently cope with future increases in resolution.

This purpose is to bring the control electrode regions of a semiconductor transistor, which are made up of two main electrode regions of the same conductivity type and a control electrode region of the opposite conductivity type from the main electrode regions, into a floating state, and to remove the control electrodes in the floating state. an accumulation operation in which carriers generated by light are accumulated in the floating control electrode region by controlling the potential of the region via a capacitor;
In an optical conversion device having a structure capable of performing a readout operation for reading out the accumulated voltage generated in the control electrode region by the accumulation operation and a refresh operation for extinguishing the carriers accumulated in the control electrode region, At least one high concentration region of the opposite conductivity type to the control electrode region is provided in a part of the control electrode region other than the main electrode region adjacent to the surface, and the high concentration region of the opposite conductivity type is controlled by the control electrode region. This is achieved by a photoelectric conversion device characterized in that the main electrode region of an insulated gate transistor is used to control the potential of the electrode region.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram illustrating the basic structure and operation of a photosensor cell that constitutes a photoelectric conversion device according to an embodiment of the present invention.

FIG. 1(a) shows a plan view of the optical sensor cell, and FIG. 1(b) shows a plan view of the optical sensor cell.
) is a cross-sectional view of a portion AA' in the plan view of FIG. 1(a), and FIG. 1(c) is an equivalent circuit thereof. In addition,
In each part, parts common to FIGS. 1(a), (b), and (c) are given the same number.

Although FIG. 1 shows a plan view of the aligned layout method, it goes without saying that the pixel shifting method (interpolation layout method) can also be used to increase the horizontal resolution.

This optical sensor cell is made of a silicon substrate doped with impurities such as phosphorus (P), antimony (Sb), and arsenic (As) to make it n-type or n+ type, as shown in FIGS. 1(a) and (b). 1, a passivation film 2 usually made of a PSG film or the like; an insulating oxide film 3 made of a silicon oxide film (SiO2); An element isolation region 4 made of an insulating film or a polysilicon film, etc.;
- region 5; p region 6, which is the base of the bipolar transistor doped with an impurity such as boron (B) using an impurity diffusion technique or an ion implantation technique; formed by an impurity diffusion technique, an ion implantation technique, etc. N+ region 7 which becomes the emitter of the bipolar transistor to be used; for example, aluminum (Al
), Al-Si, Al-Cu-Si, or other conductive material; an electrode 9 for applying a pulse to the floating p-region 6 through the insulating film 3; its wiring 10; N+ region 1 with a high impurity concentration formed by impurity diffusion technology etc. to make ohmic contact with the back surface of the substrate 1
1; an electrode 12 made of a conductive material such as aluminum for applying a substrate potential, that is, a collector potential of a bipolar transistor;

Note that 19 in FIG. 1(a) is a contact portion for connecting the n+ region 7 and the wiring 8. Further, the alternating portions of the wirings 8 and 10 are so-called two-layer wirings, and are insulated from each other by insulating regions formed of an insulating material such as SiO2. That is, it has a two-layer metal wiring structure.

The capacitor Cox 13 in the equivalent circuit of FIG. 1(c) has a MOS structure including an electrode 9, an insulating film 3, and a p-region 6, and a bipolar transistor 14 has an n+ region 7 as an emitter, a p-region 6 as a base, and an impurity. small concentration n
- region 5, and n or n+ region 1 as a collector. As is clear from these drawings, p region 6 is made into a floating region.

The second equivalent circuit in FIG. 1(c) includes the bipolar transistor 14, a base-emitter junction capacitance Cbe15, a base-emitter pn junction diode Dbe16, a base-collector junction capacitance Cbc17, and a base-collector pn junction diode. This is expressed using Dbc18.

The basic operation of the optical sensor cell will be explained below with reference to FIG.

The basic operation of this photosensor cell consists of a charge accumulation operation by light incidence, a read operation, and a refresh operation. In charge storage operation, for example, the emitter is grounded through wire 8 and the collector is biased to a positive potential through wire 12. It is also assumed that the base is brought to a negative potential, that is, to a reverse bias state with respect to the emitter 7, by applying a positive pulse voltage to the capacitor Cox 13 through the wiring 10 in advance.

The operation of biasing the base 6 to a negative potential by applying a pulse to the Cox 13 will be explained in detail later when the refresh operation is explained.

In this state, when light 20 enters from the front side of the photosensor cell as shown in FIG. 1, electron-hole pairs are generated within the semiconductor.

Of these, electrons flow toward the n-region 1 side because the n-region 1 is biased to a positive potential, but holes are rapidly accumulated in the n-region 6. Due to the accumulation of holes in the p region, the potential of the p region 6 gradually changes toward a positive potential.

In FIGS. 1(a) and 1(b), the lower surface of the light-receiving surface of each sensor cell is almost entirely occupied by the p region, and a portion thereof is an n+ region 7. Naturally, the concentration of electron-hole pairs excited by light increases as it approaches the surface. Therefore, many electron-hole pairs are excited in the p-region 6 by the light. Electrons photoexcited in the p region flow out from the p region 6 without recombining,
If the structure is such that it is absorbed in the n region, the p region 6
The excited holes are accumulated as they are, changing the potential of p region 6 to a positive potential direction. When the impurity concentration of p region 6 is made uniform, electrons excited by light diffuse to the pn-junction between p region 6 and n-region 5, and then join the n-region. It is absorbed by the n collector region 1 due to the drift caused by the strong electric field. of course,
Although it is possible for electrons to travel within the p region 6 only by diffusion, if the structure is such that the p base impurity concentration decreases from the surface to the inside, this impurity concentration difference will cause the base An electric field Ed, directed from the inside to the surface is generated within the surface. Here, W8 is the depth from the light incident surface of the p region 6, k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, NAs is the surface impurity concentration of the p base region 6, N
Ai is the impurity concentration at the interface between p region 6 and n-high resistance region 5.

Here, if NAs/NAi>3, the movement of electrons in p region 6 is performed by drift rather than diffusion. That is, in order to effectively operate the carriers excited by light in the p-region 6 as a signal, the impurity concentration of the p-region 6 must decrease from the light-incidence side surface toward the inside. is desirable. When p region 6 is formed by diffusion, its impurity concentration decreases toward the inside compared to the light incident side surface.

A portion below the light-receiving surface of the sensor cell is occupied by the n+ region 7. The depth of the n+ region 7 is usually 0.2 to 0.3μ.
Since the light is designed to be about m or less, the amount of light absorbed by the n+ region 7 is not so large to begin with, so there is no problem.

However, the presence of the n+ region 7 causes a decrease in sensitivity to light on the short wavelength side, particularly blue light. The impurity concentration of n+ region 7 is usually designed to be about 1×10 20 cm −3 or more. The diffusion distance of holes in the n+ region 7 doped with impurities at such a high concentration is 0.15 to 0.
It is about 2 μm. Therefore, in order to effectively flow the holes optically excited in n+ region 7 into p region 6, it is desirable that n+ region 7 also have a structure in which the impurity concentration decreases from the light incident surface toward the inside. If the impurity concentration distribution of the n+ region 7 is as described above, a strong drift electric field will be generated from the light incident side surface to the inside, and the n+ region 7 will be
The holes that are optically excited immediately flow into the p region 6 due to the drift. If the impurity concentrations of both the n+ region 7 and the p region 6 are configured to decrease from the light incident side surface toward the inside, then in the n+ region 7 and the p region 6 existing on the light incident side surface side of the sensor cell, All optically excited carriers function effectively as optical signals. As or P
If this n+ region 7 is formed by impurity diffusion from a silicon oxide film or a polysilicon film doped with a high concentration of , it is possible to obtain an n+ region having the desired impurity gradient as described above.

Eventually, the accumulation of holes will cause the base potential to change to the emitter potential, in this case to ground potential, where it will be clipped.

More precisely, the base-emitter region is deeply biased in the forward direction, and holes accumulated in the base are clipped by a voltage that begins to flow to the emitter. That is, the saturation potential of the photosensor cell in this case is approximately given by the potential difference between the bias potential when p region 6 is initially biased to a negative potential and the ground potential. When n+ region 7 is not grounded and accumulates charges generated by optical input in a floating state, p region 6 can accumulate charges to approximately the same potential as n region 1.

The above is a qualitative and general explanation of the charge accumulation operation, but a more specific and quantitative explanation will be given below.

The spectral sensitivity distribution of this optical sensor cell is given by the following equation.

However, λ is the wavelength of light [μm], α is the attenuation coefficient of light in silicon crystal [μm−1], and x is at the semiconductor surface.

“Dead la” causes recombination loss and does not contribute to sensitivity.
yer” (insensitive region) thickness [μm], y is the thickness of the epitaxial layer [μm], and T is the transmittance, that is, the amount of light that is effectively incident on the semiconductor, taking into account reflection, etc. Using the spectral sensitivity S(λ) and the irradiance Ee(λ) of the photosensor cell, the photocurrent Ip is calculated by the following formula.

However, the irradiance Ee (λ) [μW・cm−2・nm−1]
is given by the following equation.

However, EV is the illuminance [Lux] of the light receiving surface of the sensor, P (λ)
is the spectral distribution of the light incident on the light receiving surface of the sensor, V(λ
) is the relative luminous efficiency of the human eye.

Using these formulas, in a photosensor cell with an epitaxial layer of 4 μm, when irradiated with light source A (285°K) and the sensor light receiving surface illuminance is 1 [Lux], it is approximately 280 nA/cm.
-2 photocurrent flows, the number of incident photons or the number of generated electron-hole pairs is 1.8 × 10
It is about 12 pieces/cm2·sec.

Further, at this time, the potential Vp generated by the accumulation of holes excited by light in the base is given by Vp=Q/C. Q is the amount of accumulated hole charge, and C is C
This is the junction capacitance that is the sum of be15 and Cbc17.

Now, the impurity concentration of n+ region 7 is set to 1020 cm-3, p
The impurity concentration of region 6 is 5 x 1016 cm-3, the impurity concentration of n- region 5 is 10 cm13, and the area of n+ region 7 is 1.
6 μm2, the area of p region 6 is 64 μm2, and the thickness of n-region 5 is 3 μm, the junction capacitance is approximately 0.014p.
On the other hand, the number of holes accumulated in the p region 6 is determined by the accumulation time of 1/60 sec, and the effective light receiving area, that is, the area obtained by subtracting the area of the electrodes 8 and 9 from the area of the p region 6, is approximately 56 μm2. Then, the number becomes 1.7×104.

Therefore, the potential Vp generated by light incidence is about 190 mV.

What should be noted here is that as the resolution increases and the cell size decreases, the amount of light incident on each photosensor cell decreases, and the amount of stored heat charge Q decreases as well. As the cell becomes smaller, the junction capacitance also decreases in proportion to the cell size, so the potential Vp generated by light incidence remains almost constant. This is because the uninvented photosensor cell has an extremely simple structure, as shown in FIG. 1, and has the potential to have an extremely large effective light-receiving surface.

This is one of the reasons why the photoelectric conversion device of the present invention is advantageous compared to interline type CCDs.
In a D-type imaging device, in order to secure the amount of charge to be transferred, the area of the transfer section becomes relatively large, which reduces the effective light-receiving surface, resulting in a decrease in sensitivity, that is, the voltage generated by incident light. become. Furthermore, in the interline type CCD type imaging device, the saturation voltage is limited by the size of the transfer section and gradually decreases, whereas in the optical sensor cell of the present invention, as mentioned earlier, the saturation voltage is limited by the size of the transfer section and gradually decreases. The saturation voltage is determined by the bias voltage when p-region 6 is initially biased to a negative potential, and a large saturation voltage can be ensured.

The operation of reading out the voltage generated by the charges accumulated in p region 6 as described above to the outside will be described next.

In the read operation state, the emitter and wiring 8 are in a floating state,
The collector is held at a positive potential Vcc.

Figure 2 shows an equivalent circuit. Now, if the potential when the base 6 is biased to a negative potential before irradiation with light is -V■, and the accumulated voltage generated by light irradiation is Vp, then the base potential becomes -V■ + Vp. ing. When a positive voltage VR for reading is applied to the electrode 9 through the wiring 10 in this state, this positive potential VR is applied to the oxidation film capacitance Cox13.
The capacitance is divided by the base-emitter junction capacitance Cbe15 and the base-collector junction capacitance Cbc7, and a voltage is added to the base. Therefore, the base potential becomes. Here, if the following conditions are satisfied, the base potential becomes the accumulated voltage Vp itself generated by light irradiation. When the base potential is biased in the positive direction with respect to the emitter potential in this way, electrons are injected from the emitter to the base, and since the collector potential is positive, they are accelerated by the drift electric field and flow into the collector. reach. The current flowing at this time is given by the following equation.

However, Aj is the junction area between the base and emitter, q is the unit charge (1.6 × 10-17 coulombs), Dn is the electron diffusion constant in the base, and npo is the electron as minority carrier at the emitter end of the p base. W is the base width, NAe is the acceptor concentration at the emitter end of the base, NAc is the acceptor concentration at the collector end of the base, k is the Boltzmann constant, T is the absolute temperature, and Ve is the emitter potential.

It is clear from the above equation that this current flows until the emitter potential Ve becomes equal to the base potential, that is, the accumulated voltage Vp generated by light irradiation here. At this time, the temporal change in the emitter potential Ve is calculated by the following equation.

However, here, the wiring length Cs is the capacitance 21 of the wiring 8 connected to the emitter.

FIG. 3 shows an example of a temporal change in emitter potential calculated using the above equation.

According to FIG. 3, it takes about 1 second for the emitter potential to become equal to the base potential. This is because when the emitter potential Ve approaches Vp, less current flows. Therefore, the means to solve this problem is to set the following condition when applying the positive voltage VR to the electrode 9, but by inserting an alternative condition to this condition, the base potential is increased by Vnias in the forward direction. One possible method is to bias the

The current flowing at this time is given by the following equation.

In Fig. 4(a), when V8ias = 0.6V, the accumulated voltage V when V8 applied to the electrode 9 is returned to zero volts after a certain period of time and the flowing current is stopped.
The relationship between read voltage, ie, emitter potential, and p is shown. However, in FIG. 4(a), a constant potential depending on the read time due to the bias voltage component is always added to the read voltage, but the value obtained by subtracting the gain is plotted. When the positive voltage V8 applied to the electrode 9 is returned to zero volts, a voltage opposite to that when applied is added to the base potential, so the base potential remains in the state before applying the positive voltage V8, i.e. -V9 and the emitter is reverse biased, so current flow stops. According to FIG. 4(a), if the readout time is about 100ns or more (that is, the time during which V8 is applied to the electrode 9), the linearity of the accumulated voltage Vp and the readout voltage can be ensured over a range of about 4 digits. , indicating that high-speed reading is possible. In FIG. 4(a), the 45° line is the result when sufficient time is taken for reading, and the line at 45° is the result when sufficient time is taken for reading.In the above calculation example, the arrangement 8 Although the capacitance Cs is set to 4 pF, which is about 300 times larger than the junction capacitance of Cbc+Cbc of 0.014 pF, the accumulated voltage Vp generated in the p region 6 is not attenuated in any way. Furthermore, FIG. 4(a) shows that the data can be read out at extremely high speed due to the effect of the bias voltage. This is because the amplification function, that is, the charge amplification function, of the photosensor cell according to the above configuration is working effectively.

On the other hand, in the conventional MOS type imaging device, the accumulated voltage V
In such a readout process, p becomes Cj·Vp/(Cj+Cs) (where Cj is the pn junction capacitance of the light receiving part of the MOS image pickup device) in the shadow tube of the wiring capacitance Cs, and the readout voltage value decreases by two orders of magnitude. It had the disadvantage of being stored away. For this reason, in MOS type imaging devices, fixed pattern noise due to variations in parasitic capacitance of switching MOS transistors for external readout, or random noise generated due to large wiring capacitance, that is, output capacitance, is large.
Although there was a problem that the S/N ratio could not be obtained, Fig. 1 (a
), (b), and (c), p
The accumulated voltage itself generated in region 6 is read out to the outside, and since this voltage is quite large, fixed pattern noise and random noise caused by the output capacitance are relatively small, resulting in a signal with an extremely good S/N ratio. It is possible to obtain

Previously, we showed that when the bias voltage V8ias was set to 0.6V, linearity of about 4 orders of magnitude could be obtained with a high-speed readout time of about 100nsec. The calculated results are shown in more detail in FIG. 4(b).

In FIG. 4(b), the horizontal axis represents the bias voltage V8ias, and the vertical axis represents the read time.

The parameters also indicate time dependence until the read voltage reaches 80%, 90%, 95%, and 98% of 1 mV when the accumulated voltage is 1 mV. As shown in Figure 4(a), at a storage voltage of 1 mV, 80% and 9%, respectively.
It is clear that when the values are 0%, 95%, and 98%, even better values are shown at higher storage voltages.

According to FIG. 4(b), when the bias voltage V8ias is 0.6V, the readout time is 0.12μs for the readout voltage to be 80% of the accumulated voltage, and 0.2μs for the readout voltage to be 90%.
It can be seen that it takes 7 μs, 0.54 μs to reach 95%, and 1.4 μs to reach 98%. Further, it is shown that if the bias voltage V8ias is made larger than 0.6V, even faster reading is possible. In this way, once the readout time and required linearity are determined from the overall design of the imaging device, the required bias voltage VSias can be determined using the graph in FIG. 4(b).

Another advantage of the optical sensor cell having the above configuration is that the holes accumulated in the p region 6 can be read out nondestructively because the probability of recombination of electrons and holes in the p region 6 is extremely small. That is, when the voltage V8 applied to the electrode 9 during readout is returned to zero volts, the potential of the p region 6 becomes the reverse bias state before applying the voltage V8, and the accumulated voltage Vp generated by light irradiation is newly As long as it is not irradiated, it will be preserved as is. This means that when the optical sensor cell according to the above configuration is configured as a photoelectric conversion device, new functions can be provided in terms of system operation.

The time during which the accumulated voltage Vp can be held in the p region 6 is extremely long, and the maximum holding time is rather limited by the dark current thermally generated in the depletion layer of the junction.

In other words, this is because the optical sensor cell is saturated by this thermally generated dark radio wave.However, in the optical sensor cell according to the above configuration, the region where the depletion layer spreads is the n- region which is a low impurity concentration region. This n-region 5 has an extremely low impurity concentration of about 1012 cm-3 to 1014 cm-3, so its crystallinity is good, and it is thermally stable compared to MOS type and CCD type imaging devices. Few electron-hole pairs are generated.

Therefore, the dark current is small compared to other conventional devices. That is, the optical sensor cell according to the above configuration essentially has a structure with low dark current noise.

Next, the operation of refreshing the charges accumulated in p region 6 will be explained.

In the optical sensor cell having the above configuration, as already mentioned, the charges accumulated in the p region 6 are not eliminated by the read operation. Therefore, in order to input new optical information, a refresh operation is required to eliminate the previously accumulated charges. At the same time, it is necessary to charge the potential of p region 6, which is in a floating state, to a predetermined negative voltage.

In the optical sensor cell having the above configuration, the refresh operation is also performed by applying a positive voltage to the electrode 9 through the wiring 10, similarly to the read operation. At this time, the emitter is grounded through the wiring 8. The collector is grounded or at a positive potential through the electrode 12. FIG. 5 shows an equivalent circuit for refresh operation. However, an example is shown in which the collector side is grounded.

When a positive voltage V8H is applied to the electrode 9 in this state, the base 22 has an oxide film capacitance Cox13 and a base
Due to the capacitance division of the emitter junction capacitance Cbe15 and the base-collector junction capacitance Cbc17, the following voltage is instantaneously applied as in the previous read operation. Due to this voltage, the base-emitter junction diode Dbe16 and the base-collector junction diode Dbc18 are forward biased and become conductive, current begins to flow, and the base potential gradually decreases.

At this time, the change in the potential V of the base in a floating state is approximately expressed by the following equation.

However, i1 is the current flowing through the diode Dbc, and i2 is the current flowing through the diode Dbe. Ab is the base area, Ae
is the emitter area, Dp is the diffusion constant of holes in the collector, pne is the hole concentration in the collector in a thermal equilibrium state, pne is the mean free path of holes in the collector, and npe is the electron ρ degree in the base in a thermal equilibrium state. be. In i2, the current due to hole injection from the base side to the emitter can be ignored because the impurity concentration of the emitter is sufficiently higher than that of the base.

The above equation is an approximation of a stepwise junction, and the actual device deviates from a stepwise junction, and the base is thin and has a complicated concentration distribution, so it is not exact. , the refresh operation can be explained with a fair approximation.

Of the current i1 flowing between the base and collector in the above equation, q
・Dp・pne/Lp indicates a current due to holes, that is, a component where holes flow from the base to the collector side. In order to facilitate the flow of current due to these holes, in the optical sensor cell having the above configuration, the impurity concentration of the collector is designed to be a little lower than that of a normal bipolar transistor.

FIG. 6 shows an example of the time dependence of the base potential calculated using this formula. The horizontal axis shows the passage of time from the time when the refresh voltage V8H was applied to the electrode 9, that is, the refresh time, and the vertical axis shows the base potential. In addition, the initial potential of the base is used as a parameter. The initial potential of the base is the potential exhibited by the base in a floating state at the moment when refresh voltage VRH is applied, and VRH
, Cox, Cbe, Cbc and the charge stored in the base.

Looking at FIG. 6, the base potential always falls along a straight line on the semi-logarithmic graph after a certain period of time, regardless of the initial potential.

FIG. 6(b) shows an experimental example of base potential change with respect to refresh time. Compared to the calculation example shown in Figure 6(a), the test device used in this experiment has a much larger dimension, so although the absolute value does not match the calculation example, the base potential change with respect to the refresh time is It has been demonstrated that it changes linearly on a semi-logarithmic graph. This experimental example shows values when both the collector and emitter are grounded.

Now, the maximum value of the accumulated voltage VP due to light irradiation is 0.4 [V]
, if the voltage V applied to the base by the refresh voltage VRH is 0.4 [V], the maximum value of the initial base potential is 0.8 [V] as shown in FIG. ] After that, the base potential starts to fall in a straight line, and after 10-5 [sec], when there is no light, that is, the initial base potential is 0.4 [V
] corresponds to the potential change when .

There are two ways in which the p region 6 can be charged to a negative potential by applying a positive voltage for a certain period of time through the MOS capacitor Cox and removing the positive voltage. One is p region 6
The holes with positive charge from n are mainly in the grounded state.
This is an operation in which negative charges are accumulated by flowing out into region l.

In order to prevent holes from flowing unilaterally from p-region 6 to n-region 1 and to prevent electrons from n-region 1 from flowing into p-region 6 too much, the impurity density of p-region 6 must be set to the impurity density of n-region 1. It should be higher. On the other hand, electrons from n+ region 7 and n region 1 flow into p region 6 and recombine with holes, thereby allowing negative charges to accumulate in p region 6. In this case, the impurity density of n region 1 is p
It is set higher than area 6. The operation in which negative charges are accumulated due to the outflow of holes from the p region 6 is more
This is much faster than the operation in which negative charges are accumulated by electrons flowing into the base of region 6 and recombining with holes. However, according to experiments conducted so far, it has been confirmed that even a refresh operation in which electrons are flowed into the p region 6 shows a sufficiently fast time response for the operation of the photoelectric conversion device.

When a photoelectric conversion device is constructed by arranging a large number of optical sensor cells according to the above configuration in the X and Y directions, the accumulated voltage Vp of each sensor cell varies between 0 and 0.4 [V] in the above example according to the image. However, 10-5 [sec] after applying the refresh voltage VRH, although a constant voltage of about 0.3 [V] remains at the base of all sensor cells, the change in the charged product voltage Vp due to the image completely disappears. I know that it will happen. That is, in the photoelectric conversion device using the optical sensor cells according to the above configuration, there is a complete refresh mode in which the base potential of all sensor cells is brought to zero volts by a refresh operation (in this case, in the example of FIG. 6(a), the
0 [sec]), and a transient refresh mode in which a certain constant voltage remains at the base potential but the fluctuation component due to the accumulated voltage Vp disappears (in this case, as shown in Figure 6(a) In the example, 10 [μsec]
~10 [sec] refresh pulse). In the above example, the voltage V applied to the base by the refresh voltage VRH was set to 0.4 [V], but this voltage VA was set to 0.6 [V].
[V], the above transient refresh mode is
According to FIG. 6, the refresh occurs in 1 [nsec] and can be refreshed at extremely high speed. The choice of whether to operate in complete refresh mode or transient refresh mode is determined by the purpose of use of the photoelectric conversion device.

If the voltage remaining at the base in this transient refresh mode is VK, then after applying the refresh voltage VRH,
In the instantaneous additive state when VRH is returned to zero volts, a negative voltage is added to the base, so that the base potential after the refresh operation by the refresh pulse becomes, and the base becomes reverse biased with respect to the emitter.

It was explained earlier that during the accumulation operation of accumulating carriers excited by light, the base is in a reverse bias state in the accumulation state, but with this refresh operation,
The two operations of refreshing and bringing the base to a reverse bias state are performed simultaneously.

FIG. 6(c) shows experimental values of changes in base potential after refresh operation with respect to refresh voltage VRH. As a parameter, the CoK value is set from 5 pF to 100 pF. The circles are experimental values, and the solid lines are more calculated values. At this time VK=0
．． 52V, and Cbc+Cbe=4pF. However, the probe capacitance of 13 pF of the viewing oscilloscope is connected in parallel to Cbc+Cbe. In this way, the calculated values and experimental values are in complete agreement, and the refresh operation has been experimentally confirmed.

In the above refresh operation, an example has been described in which the collector is grounded as shown in FIG. 5, but it is also possible to perform the refresh operation with the collector at a positive potential.

At this time, the base-collector junction diode Dbc
18, even if a refresh pulse is applied, the potential applied to the base by this refresh pulse is
If the positive potential applied to the collector is greater, it remains non-conductive, so current flows only through the base-emitter junction diode Dbe16. Therefore, the base potential decreases more slowly, but basically the operation is exactly the same as that described above.

In other words, the relationship between the base potential and the refresh time in FIG. 6(a) is such that the diagonal straight line when the base potential decreases in FIG. 6(a) shifts to the right, that is, in the direction that requires more time. become.

Therefore, if you use the same refresh voltage VRH as when the collector is grounded, it will take time to refresh, but if you slightly increase the refresh voltage VRH, you can achieve a high-speed refresh operation just like when the collector is grounded. be.

The above is an explanation of the basic operation of the photosensor cell according to the above configuration, which consists of a charge accumulation operation, a readout operation, and a refresh operation by light incidence.

As explained above, the basic structure of the optical sensor cell according to the above configuration is the same as that of the above-mentioned Japanese Patent Application Laid-Open Nos. 56-150878, 560-157073, and 56-165473.
They have an extremely simple structure compared to the previous ones, and are fully compatible with future higher resolutions.They also have advantages such as low noise, high output, wide dynamic range, and non-destructive readout due to their excellent amplification function. is stored as is.

Next, an embodiment of the photoelectric substation device of the present invention, which is configured by two-dimensionally arranging the optical sensor cells according to the configuration described above, will be described with reference to the drawings.

FIG. 7 shows a circuit configuration diagram of a photoelectric conversion device in which basic optical sensor cell structures are two-dimensionally arranged in a 3×3 arrangement.

The basic optical sensor cell 30 surrounded by the dotted line already explained
(At this time, the collector of the bipolar transistor is shown to be connected to the substrate and the substrate electrode.), horizontal lines 31, 31', 31'' for applying read pulses and refresh pulses, and for generating read pulses; vertical shift register 32, buffer MOS transistors 33, 33', 33'' between the vertical shift register 32 and horizontal lines 31, 31', 31'', buffer M
A terminal 34 for applying a pulse to the gates of the OS transistors 33, 33', 33'', and a buffer MOS transistor 35, 35' for applying a refresh pulse.
, 35″, a terminal 36 for applying a pulse to its gate, a terminal 37 for applying a refresh pulse,
Vertical lines 38, 38', 38'' for reading the accumulated voltage from the basic photosensor cell 30, horizontal shift register 39 for generating pulses for selecting each vertical line, MOS for gates for opening and closing each vertical line Transistors 40, 40', 40'', an output line 41 for reading out the stored voltage to the amplifier section, and a MOS transistor 4 for refreshing the charge stored in the output line after reading.
2. A terminal 43 for applying a refresh pulse to the MOS transistor 42, a transistor 44 such as bipolar, MOS, FET, J-FET, etc. for amplifying the output signal, a load resistor 45, a terminal for connecting the transistor and the power supply 46, transistor output terminal 47, MOS transistor 4 for refreshing the charges accumulated in the vertical lines 40, 40', 40'' in a read operation;
8, 48', 48'', and MOS transistor 48,
This photoelectric conversion device is constituted by a terminal 49 for applying a pulse to the gates 48' and 48''.

The operation of this photoelectric conversion device will be explained using pulse timing diagrams shown in FIGS. 7 and 8.

In FIG. 8, section 61 is a refresh operation;
2 corresponds to the storage operation, and section 63 corresponds to the readout operation.

At time t1, the substrate potential, that is, the collector potential 64 of the photosensor cell portion is kept at the ground potential or positive potential, and FIG. 8 shows that it is kept at the ground potential. Regardless of whether it is a ground potential or a positive potential, as already explained, the time required for refreshing differs, and there is no change in the basic operation.
5 is in a high state, and the M0S transistors 48, 4
8′, 48″ are kept conductive, and each photosensor cell is
It is grounded through vertical lines 38, 38', 38''. Also, terminal 36 has a buffer MO as shown in waveform 66.
A voltage that makes the S transistor conductive is applied to the buffer MOS transistor 35 for refreshing the entire screen at once.
, 35', 35'' are in a conductive state. In this state, when a pulse is applied to the terminal 37 as shown in waveform 67, a voltage is applied to the base of each optical sensor cell through the horizontal lines 31, 31', 31''. , as already explained, the refresh operation begins, and the charge that had been accumulated before then is
It is refreshed according to a complete refresh mode or a transient refresh mode. The pulse width of waveform 67 determines whether the mode is complete refresh mode or transient refresh mode.

At time t2, as described above, the base of the transistor of each photosensor cell is reverse biased with respect to the emitter, and the next accumulation period 62 is entered. In this refresh period 61, as shown in the figure, all other applied pulses are kept in a low state.

In the accumulation operation section 62, the substrate voltage, that is, the collector potential waveform 64 of the transistor is set to a positive potential. This allows electrons of the electron-hole pairs generated by light irradiation to quickly flow toward the collector side. However, keeping this collector potential at a positive potential is not an essential condition because the base is biased in the reverse direction with respect to the emitter, that is, images are taken with a negative potential.It is also basic to keep the collector potential at ground potential or a slightly negative potential. There is no change in the storage behavior.

In the storage operation state, the MOS transistors 48, 4
The potential 65 of the gate terminal 49 of 8', 48'' is kept high, as in the refresh interval, and each MOS transistor is kept conductive. Therefore, the emitter of each photosensor cell is connected to the vertical line 38, 38'. , 38''. When holes are accumulated in the base due to strong light irradiation and become saturated, that is, when the base potential becomes forward biased with respect to the emitter potential (ground potential), the holes become vertical lines 38, 38'. , 38
'', where the base potential change stops and becomes clipped.

Therefore, even if the emitters of vertically adjacent photosensor cells are commonly connected by vertical lines 38, 38', 38'', vertical lines 38, 30', 3
If 0'' is grounded, no blooming phenomenon will occur.

To avoid this blooming development, even if the MOS transistors 48, 48', 48'' are made non-conductive and the vertical lines 38, 38', 38'' are made floating, the substrate potential, that is, the collector potential 64, may be slightly reduced. This can also be achieved by setting the potential to be negative, and when the base potential changes to a positive potential due to accumulation of holes, the potential flows toward the collector side before the emitter.

Following the accumulation section 62, a readout section 63 begins at time t3. At this time t3, the MOS transistor 48
, 48', 48'', the potential 65 of the gate terminal 49 is low.
Then, the potential 68 of the gate terminals of the buffer MOS transistors 33, 33', 33'' of the horizontal lines 31, 31', 31'' is set to high, thereby making each MOS transistor conductive. However, the timing at which the potential 68 of the gate terminal 34 is set to high is not necessarily at time t3, but may be at an earlier time.

At time t4, among the outputs of the vertical shift register 32, those connected to the horizontal line 31 are as shown in the waveform 69.
Since the MOS transistor 33 is in a conductive state at this time, each of the three photosensor cells connected to the horizontal line 31 is read out. This readout operation is as already explained above, and the signal voltage generated by the signal charge accumulated in the base region of each photosensor cell remains unchanged on the vertical lines 38, 38', 38''.
appears in The pulse width of the pulse voltage from the vertical shift register 32 at this time is set to a pulse width that maintains a sufficient linearity between the read voltage and the stored voltage, as shown in FIG. Further, as explained above, the pulse voltage is adjusted so that a forward bias is applied to the emitter by V8ias.

Next, at time t5, among the outputs of the horizontal select register 39, only the output to the gate of the MOS transistor 40 connected to the vertical line 38 becomes h as shown in the waveform 70.
high, the MOS transistor 40 becomes conductive, and the output signal passes through the output line 41 and enters the output transistor 44, where the current is amplified and output from the output terminal 47. After the signal is read out in this way, the output line 41
Since the signal charge due to the wiring capacitance remains, at time t6, a pulse as shown in pulse waveform 71 is applied to the gate terminal 43 of the MOS transistor 42,
The remaining signal charge is refreshed by turning on the transistor 42 and grounding the output line 41. Thereafter, in the same manner, the switching MOS transistors 40' and 40'' are made conductive one after another, and the vertical line 3
8' and 38'' are read out. After reading out the signals from each horizontally arranged line of photosensor cells in this way, the output line 41 is read out on the vertical lines 38, 38', and 38''. Similarly, since the signal charge due to the wiring capacitance remains, the MOS transistors 48, 48', 48'' connected to each vertical line 38, 38', 38'' are connected to their gate terminal 49. As shown by waveform 65, hi
gh to make it conductive and refresh this residual signal charge.

Next, at time t8, the vertical shift register 32
Of the outputs, the output connected to the horizontal line 31' becomes high as shown in waveform 69', and the accumulated voltage of each photosensor cell connected to the horizontal line 31' is applied to each vertical line 138, 38', 38''. Thereafter, signals are sequentially read out from the output terminal 47 by the same operations as before.

In the above explanation, the storage section 62 and the readout section 63 are
The description has been made of the operating conditions applied to application fields in which there are clear divisions, such as methyl video, which has been actively researched and developed recently. It is also possible to apply the present invention to an application field where the operations in FIG. 8 are performed simultaneously by changing the pulse timing shown in FIG. However, the refresh at this time does not refresh the entire screen at once, but requires a refresh function for each line. For example, after the signals of each photosensor cell connected to the horizontal line 31 are read out, the MOS transistor 4 is used to erase the charge remaining on each vertical line at time t7.
8, 48', and 48'', but at this time a refresh pulse is applied to the horizontal line 31. That is, in the waveform 69, at time t7, pulses with different pulse voltages and pulse widths are applied at time t4 as well. This can be achieved by using a vertical shift register configured to generate refresh pulses.In addition to this double-pulse operation, instead of the device that applies a batch refresh pulse installed on the right side of Fig. 7, It is also possible to achieve this by providing a second vertical shift register on the right side, similar to the one on the left side, and operating it at a timing different from that of the vertical register provided on the left side.

In this case, in the accumulation state as described above, there is less freedom in controlling the blooming by controlling the potentials of the emitter and collector of each photosensor cell. However, as explained in the basic operation section, in the read state, the configuration is such that high-speed reading can only be performed when a bias voltage of V8ias is applied to the base. When no voltage is applied, the amount of signal charge flowing into the vertical lines 28, 28', 28'' due to the candy of each photosensor cell is extremely small, and the blooming phenomenon does not pose a problem at all.

Moreover, the photoelectric conversion device according to this embodiment can obtain extremely excellent characteristics with respect to the smear phenomenon. The smear phenomenon is a problem that occurs in the operation and structure of CCD type imaging devices, especially frame transfer type, in which charge is transferred to the area irradiated with light. This problem occurs because carriers generated deep in the semiconductor due to light are accumulated in the charge transfer section.

Furthermore, in a MOS type imaging device, this problem arises because carriers generated deep in the semiconductor due to long wavelength light are accumulated on the drain side of the switching MOS transistor grounded in each photosensor cell.

In contrast, in the photoelectric conversion device according to this embodiment, there is no smear phenomenon that occurs due to its operation and structure, and there is no phenomenon that carriers generated deep in the semiconductor are accumulated due to long wavelength light. However, there is a concern that electrons are accumulated among the electrons and holes generated relatively near the surface of the emitter of the optical sensor cell. Therefore, electrons are not accumulated and smear phenomenon does not occur. In addition, during the line refresh operation applied to ordinary television cameras, during the horizontal blanking period, the vertical line is grounded and refreshed before reading out the accumulated voltage on the vertical line, so at the same time the emitter is The electrons accumulated during one horizontal scanning period flow out, and therefore almost no smear phenomenon occurs. In this way, in the photoelectric conversion device according to this example,
Due to its structure and operation, the smear phenomenon occurs to an essentially negligible extent, which is one of the major advantages of the photoelectric conversion device according to this embodiment.

Further, although the operation of suppressing the blooming phenomenon by manipulating the emitter and collector potentials in the storage operation state has been described above, it is also possible to use this to control the γ characteristics.

In other words, during the accumulation operation, the potential of the emitter or collector is temporarily set to a certain negative potential, and of the carriers accumulated in the base, holes that are accumulated in a greater number than the number of carriers that give this negative potential are transferred to the emitter. Alternatively, the data may be flowed to the collector side. As a result, the relationship between the accumulated voltage and the amount of incident light exhibits the characteristic of γ=1 of silicon crystal when the amount of incident light is small, and exhibits the characteristic that γ becomes smaller than 1 when the amount of incident light is large. In other words, it is possible to provide the characteristic of γ=0.45, which is normally required for a television camera, using a polygonal line approximation. If the above operation is performed once during the storage operation, a one-fold line approximation can be obtained, and if the negative potential applied to the emitter or collector is changed twice as appropriate, it is also possible to have a two-fold line type γ characteristic.

Further, in the above embodiments, the silicon substrate is used as a common collector, but a buried n+ region may be provided as in a normal bipolar transistor, and the collector may be divided for each line.

In addition to the pulse timing shown in FIG. 8, the actual operation requires the vertical shift register 32 and the horizontal shift register 3.
A clock pulse is required to drive 9.

FIG. 9 shows an equivalent circuit related to the output signal.

The capacitance Cv80 is the wiring capacitance of the vertical lines 38, 38, 38'', and the capacitance Cu81 is the wiring capacitance of the output line 41.The equivalent circuit on the right side of FIG.
This is in the read state, and the switching MOS
Transistors 40, 40', 40'' are in a conductive state;
Its resistance value in the conductive state is shown by resistor RM82. Further, the amplification transistor 44 is shown as an equivalent circuit using a resistor re83 and a current source 84. The MOS transistor 42 for refreshing the charge accumulation caused by the wiring capacitance of the output line 41 is non-conductive in the read state and has high impedance, so it is omitted in the equivalent circuit on the right side.

Each parameter of the equivalent circuit is determined by the size of the photoelectric conversion device actually configured. For example, the capacitance CV80 is about 4 pF, the capacitance CH81 is about 4 pF,
Resistance RM82 in conduction state of MOS transistor is 3KΩ
FIG. 10 shows an example of calculating the output signal waveform observed at the output terminal 47, assuming that the current amplification factor β of the bipolar transistor 44 is approximately 100.

In FIG. 10, the horizontal axis represents the time [μ
s], and the vertical axis is the output terminal 47 when the signal charge is read out from each photosensor cell and a voltage of 1 volt is applied to the wiring capacitance CV80 of the vertical lines 38, 38', 38''.
The output voltages [V] appearing in each are shown.

The output signal waveform 85 shows that the load resistance RE45 is 10KΩ, 86
The load resistance RE45 is 5KΩ, and the load resistance RE45 is 87.
is 2KΩ, and in both cases, the peak value is about 0.5V due to capacitance division between Cv80 and CH81. Naturally, the load resistance RE45
The larger the value, the smaller the amount of attenuation, resulting in a desirable output waveform.

The rise time is approximately 20ns with the above parameter values.
EC and high speed. Switching MOS transistor 4
By reducing the resistance RM in the conductive state of 0, 40', and 40'' and by reducing the wiring capacitances CV and CH, even higher-speed reading is possible.

In a photoelectric conversion device using photosensor cells with the above configuration, the voltage appearing at the output is large due to the amplification function of each photosensor cell, so the final stage amplification amplifier is also quite simple compared to a MOS type imaging device. That's fine. In the above example, a one-stage bipolar transistor type was used, but it is of course possible to use other systems, such as a two-stage structure. When bipolar transistors are used as in this example, the problem of 1/f noise that is easily noticeable on images generated from the MOS transistor of the final stage amplifier in a CCD imaging device does not occur in the photoelectric conversion device of this example. It is possible to obtain image quality with an extremely good S/M ratio.

As mentioned above, in a photoelectric conversion device using a photosensor cell with the above configuration, the amplification amplifier at the final stage can be extremely simple, so the configuration shown in FIG. 7 in which only one amplification amplifier at the final stage is provided Instead of the type shown in the embodiment shown, it is also possible to install a plurality of amplification amplifiers so that one screen can be divided into a plurality of parts and read out.

FIG. 11 shows an example of a divided readout method. In the embodiment shown in FIG. 11, the horizontal direction is divided into three parts, and the final stage amplifier is divided into three parts.
This is an example of installing one. Although the basic operation is almost the same as that described using the embodiment of FIG. 7 and the timing diagram of FIG. 8, the embodiment of FIG. 11 uses three equivalent horizontal shift registers 100, 101. , 102 are provided, and when a starting pulse is input to the terminal 103 for applying these starting pulses, the 1st column, (n+1)th column, and (2n
The outputs of the sensor cells connected to the +1)th column (n is an integer, and in this embodiment, the number of picture elements in the horizontal direction is 3n) are read out simultaneously. At the next point, 2
The column, (n+2) column, and (2n+2) column will be read.

According to this embodiment, when the time to read one horizontal line is fixed, the scanning frequency in the horizontal direction is 1/3 that of the system with one final stage amplifier. The horizontal shift register is simple, and the high-speed analog/digital converter is suitable for applications such as analog/digital conversion of the output signal from a photoelectric conversion device and signal processing.
No digital converter is required, which is a major advantage of the split readout method.

In the embodiment shown in FIG. 11, three equivalent horizontal shift registers are provided, but the same function can be provided with only one horizontal register. An example in this case is shown in FIG.

The embodiment shown in FIG. 12 shows only the horizontal switching MOS transistor and the middle part of the final stage amplifier of the embodiment shown in FIG. 11, and the other parts are not shown.
Since it is the same as the embodiment shown in FIG. 11, it is omitted.

In this embodiment, the output from one horizontal shift register 104 is connected to the gates of the switching MOS transistors in the 1st column, (n+1) column, and (2n+1) column, and these lines are read out simultaneously. There is. At the next time, the second column, (n+2) column, and (2n+2) column are read out.

According to this embodiment, although the number of wirings to the gates of each switching MOS transistor increases, it is possible to operate with only one horizontal shift register.

In the examples shown in FIGS. 11 and 12, three output amplifiers are provided, but it goes without saying that this number may be increased depending on the purpose.

In both the embodiments shown in FIGS. 11 and 12, the starting pulses and clock pulses for the horizontal shift register and vertical shift register are omitted, but they are provided in the same chip like other refresh pulses. It is supplied from a clock pulse generator or a clock pulse generator provided on another chip.

In this split readout method, when horizontal lines or all screens are refreshed at once, the accumulation time is slightly different between the n-th and (n+1)-th column photosensor cells, which causes dark current components and signal components to It is possible that a slight discontinuity may occur and be visible on the image, but
This amount is small and poses no practical problem. Furthermore, even if this has exceeded the allowable limit, correcting it using an external circuit will generate a sharp wave, subtracting this from the dark current component, and multiplying and dividing this by the signal component. This is easily possible using conventional correction techniques.

When capturing color images using such a photoelectric conversion device, it is possible to create a stripe filter or mosaic filter on-chip, or to attach a separately made color filter on top of the photoelectric conversion device. It is possible to obtain color signals.

As an example, when R, G, and B stripe filters are used, in a photoelectric conversion device using the photosensor cell according to the above configuration, the R signal,
It is possible to obtain a G signal and a B signal. An example of this is shown in FIG. This figure 13 is similar to figure 12,
Only the area around the horizontal register is shown. The rest is the same as in Figures 7 and 11, except that the first row is an R color filter, the second row is a G color filter, the third row is a B color filter, and the fourth row is an R color filter. It is assumed that a color filter is attached, such as a filter. As shown in Figure 13, the 1st row, 4th row, 7th row ---
--- each vertical line is connected to an output line 110;
This takes out the R signal. Also, 2nd row, 5th row, 8th row-
Each vertical line of ---- is connected to an output line 111, which takes out the G signal. Similarly, in the third row,
Each vertical line in the 6th column and 9th column is connected to the output line 112 to take out the B signal. Output line 11
0, 111, and 112 are connected to an on-chip refresh MOS transistor and a final stage amplifier, for example, an emitter follower type bipolar transistor, and each color signal is output separately.

FIG. 14 shows a diagram for explaining the basic structure and operation of another example of a photosensor cell constituting a photoelectric conversion device according to another example of the present invention. Further, its equivalent circuit and overall circuit configuration diagram are shown in FIG. 15(a).

The photosensor cell shown in FIG. 14 is an photosensor cell that can simultaneously perform a read operation and a line refresh using the same horizontal scan pulse. 1st
4, the difference from the configuration already shown in FIG. 1 is that the MOS connected to the horizontal line wiring 10 in FIG.
Although there was only one capacitor electrode 9, there were also MOS capacitor electrodes 12 on the sides of the vertically adjacent optical sensor cells.
0 is connected, and when viewed from one optical sensor cell, it is a double capacitor type, and in the figure, the emitters 7 of the vertically adjacent optical sensor cells are two-layer wiring (1) 8, and the wiring (2) 121(
In Fig. 14, the vertical line appears to be one, but two lines are arranged through an insulating layer) and are connected alternately to
That is, the emitter 7 is connected to the wiring (1) 8 through the contact hole 19, and the emitter is connected to the wiring (2) 121 through the contact hole 1.

This becomes clearer when looking at the equivalent circuit shown in FIG. 15(a). That is, the MOS capacitor 150 connected to the base of the optical sensor cell 152 is connected to the horizontal line 31, and the MOS capacitor 151 is connected to the underwater line 3. Further, in the diagram of the optical sensor cell 152, the MOS capacitors 15 of the optical sensor cells 15 adjacent below are connected to the common horizontal line 3.

The emitter of the photosensor cell 152 is connected to the vertical line 38, the emitter of the photosensor cell 15 is connected to the vertical line 138, and the emitter of the photosensor cell 15 is connected to the vertical line 38, and so on.

The equivalent circuit in FIG. 15(a) differs from the imaging device in FIG. 7 except for the basic photosensor cell section described above.
Switching MO for vertical line 38 refreshing
In addition to the S transistor 48, a switching MOS transistor 14 for refreshing the vertical line 138 is provided.
8, and switching M to select vertical line 38.
In addition to the OS transistor 40, a switching MOS transistor 140 for selecting the vertical line 138 is added, and one output amplifier system is added. The configuration of this output system is such that switching MOS transistors 48 and 148 are connected to refresh each line, and a horizontal scanning switching MOS transistor is used as shown in FIG. 15(b). A configuration with only one output amplifier is also possible. FIG. 15(b) shows only the vertical line selection and output amplifier system portions of FIG. 15(a).

According to the optical sensor cell shown in FIG. 14 and the embodiment shown in FIG. 15(a), the following operations are possible. In other words, when the readout operation of each optical sensor cell connected to the horizontal line 31 is completed and the horizontal blanking period in the TV operation is in progress, when the output pulse from the vertical shift register 32 is output to the horizontal line 3. MOS capacitor 1
51, the optical sensor cell 152 that has been read is refreshed. At this time, the switching MOS transistor 48 is rendered conductive, and the vertical line 38 is grounded.

Further, the output of the photosensor cell 15 is read out to the vertical line 138 through the MOS capacitor 15 connected to the horizontal line 3. At this time, the switching MOS transistor 148 is naturally rendered non-conductive, and the vertical line 138 is in a floating state. In this way, with one vertical scan pulse, it is possible to simultaneously refresh the photosensor cells that have already finished reading and read out the photosensor cells of the next line using the same pulse. At this time, as already explained, the voltage at the time of refreshing and the voltage at the time of reading differ because a bias voltage is applied at the time of reading due to the necessity of high-speed reading.
OS capacitor electrode 9 and MOS capacitor electrode 12
This is achieved by changing the area of 0 so that even if the same voltage is applied to each electrode, different voltages are applied to the base of each photosensor cell.

In other words, the area of the refresh MOS capacitor is
The area is smaller than that of the read MOS capacitor. When refreshing one line at a time instead of refreshing all the sensor cells at once, as in this example, the collector should be configured with an n-type or n-substrate as shown in Figure 1(b). However, it may be desirable to separate collectors for each horizontal line. When the collector is a substrate, the collector of all optical sensor cells is a common area, so
In the storage and light reception/readout states, a constant bias voltage is applied to the collector. Of course, as already explained, floating base refresh can be performed between the emitters even with a bias voltage applied to the collector. However, in this case, there is a drawback that at the same time that the base region is refreshed, a wasteful current flows between the emitter and collector of the cell to which the refresh pulse is applied, increasing power consumption. In order to overcome these drawbacks, instead of making the collectors of all the sensor cells a common area, the collectors of the sensor cells arranged in each horizontal line are common, but the collectors of each horizontal line are structured to be separated from each other. That is, to explain in relation to the structure shown in FIG. 1, the substrate is of a p-type, and an n-buried region heated mutually is provided for each horizontal line of the collector in the p-type substrate. The N buried regions of adjacent horizontal lines may be separated by a structure in which a P region is interposed therebetween. Dielectric isolation is better for reducing buried collector capacitors along horizontal lines. In FIG. 1, since the collector is comprised of a substrate, all isolation regions surrounding the sensor cell are provided to approximately the same depth. On the other hand, in order to separate the collectors of each horizontal line from each other, the separation area in the horizontal line direction is made deeper than the separation area in the vertical line direction by a necessary value.

If the collector is separated for each horizontal line, if the voltage of the collector of that horizontal line is grounded when reading is finished and the refresh operation starts, the emitter-collector current as described above will not flow, and the power consumption will be reduced. does not result in an increase in When refreshing is completed and a charge storage operation based on an optical signal begins, a predetermined bias voltage is applied to the collector region again.

According to the equivalent circuit shown in FIG. 15(a), outputs are alternately output to the output terminals 47 and 147 for each horizontal line. As already explained, this is the 15th
It is also possible to take out the output from one amplifier by using a configuration as shown in FIG. 2(b).

As explained above, according to this embodiment, line refreshing is possible with a relatively simple configuration, and it can be applied to ordinary fields of application such as television cameras.

As another embodiment of the present invention, a type may be considered in which a plurality of outputs are taken out from one optical sensor cell by a configuration in which the optical sensor cell is provided with a plurality of emitters, or a configuration in which one emitter is provided with a plurality of contacts.

This is because each optical sensor cell of the photoelectric conversion device according to the present invention has an amplification function, so even if multiple capacitors are connected to each optical sensor cell in order to extract multiple outputs from one optical sensor cell, the optical sensor cell This is due to the fact that the internally generated accumulated voltage Vp can be read out to each output without attenuating at all.

In this way, by having a configuration in which multiple outputs can be taken out from each optical sensor cell, many advantages can be added to the photoelectric conversion device formed by arranging a large number of each optical sensor cell in terms of signal processing, noise countermeasures, etc. is possible.

Next, an example of a method for manufacturing a photoelectric conversion device according to the present invention will be described. FIG. 16 shows selective epitaxial growth (N.En
do et at, “Hovei device is
ation technology with se
received cpitanial growth"T
ech. Dig. of 1982 IEDM, PP. 2
41-244)) is shown below.

n-type S with an impurity concentration of about 1 to 10 x 1016 cm-3
An n+ region 11 for contact is provided on the back side of the i-substrate 1.
Provided by diffusion of As or P. In order to prevent autodoping from the n+ region, an oxide film and a nitride film are usually provided on the back surface, although not shown.

The substrate 1 used has impurity concentration and oxygen concentration controlled to be uniform. That is, a crystal wafer having a sufficiently long and uniform carrier line time is used. For example, a crystal produced by the MCZ method is suitable as such a material. An oxide film approximately 1 μm thick is formed on the surface of the substrate 1 by wet oxidation. That is, oxidation is performed in an H2O atmosphere or (H2+O2) atmosphere.High-pressure oxidation at a temperature of about 900.degree. C. is suitable for obtaining a good oxide film without producing stacking faults.

A SiO2 film having a thickness of, for example, about 2 to 4 .mu.m is deposited thereon by CVD. (N2+SiH4+O2) gas system to obtain desired thickness of SiO at a temperature of about 300 to 500℃.
2 films are deposited. The molar ratio of O2/SiH4 is set to about 4 to 40, although it depends on the temperature. Through the photolithography process, the oxide film in the other regions is formed into (CF4+H2), C2F6, C
For example, remove by reactive ion etching using a gas such as H2F2 (step (a) in Figure 16).
When one pixel is provided in ×10 μm2, the SiO2 film is left in a mesh shape with a pitch of 10 μm. The width of the SiO2 film is selected to be, for example, about 2 μm. The damaged layer and contamination layer on the surface by reactive ion etching are
After removal by Cl2 gas-based plasma etching or wet etching, evaporation in an ultra-high vacuum, sputtering in a load-lock format with a sufficiently purified atmosphere, or low-pressure light CVD in which SiH4 gas is irradiated with a CO2 laser beam. So, amorphous silicon 30
1 (step (b) in FIG. 16). CBrF3,
Amorphous silicon other than those deposited on the side surfaces of the SiO2 layer is removed by anisotropic etching using reactive ion etching using a gas such as CCl2F2 or Cl2 (step (c) in FIG. 16). As before, after sufficiently removing the damage and the contamination layer, the silicon substrate surface is thoroughly cleaned, and a silicon layer is selectively grown using a (H2+SiH2, Cl2+HCl) gas system. Several 10 Torr
The growth is performed under reduced pressure, and the substrate temperature is 900-1000℃.
℃ and the molar ratio of HCl are set to higher values than a certain level.

If the amount of HCl is too small, selective growth will not occur. A silicon crystal layer grows on a silicon substrate, but SiO2
No silicon is deposited on the SiO2 layer because the silicon on the layer is etched by HCl (first
Figure 6(d)). The thickness of the n-layer 5 is, for example, about 3 to 5 μm.

The impurity concentration is preferably 1012 to 1016 cm-3
Set to a certain degree. Of course, it is possible to deviate from this range, but if the pn junction is completely depleted at the diffusion potential or an operating voltage is applied to the collector, at least n
- It is desirable to select an impurity concentration and thickness such that the region is completely depleted.

Since commonly available HCl gas contains a large amount of water, an oxide film is constantly formed on the surface of the silicon substrate, making it impossible to expect high-quality epitaxial growth. HCl containing a large amount of water reacts with the material of the cylinder when it is in the cylinder and contains a large amount of heavy metals, mainly iron, which tends to result in an epitaxial layer that is heavily contaminated with heavy metals. Since it is desirable for the epitaxial layer used in the optical sensor cell to have as little dark current component as possible, it is necessary to suppress contamination by heavy metals to the utmost. Of course, ultra-high purity materials are used for SiH2Cl2, but H
Cl is particularly low in moisture, preferably having a moisture content of at least 0.5 ppm or less. Of course, the lower the water content, the better.

In order to further improve the quality of the epitaxial growth layer, the substrate is first treated at a high temperature of about 1,150 to 1,250°C to remove oxygen from near the surface, and then subjected to a long-term heat treatment at about 800°C to generate many micro-defects inside the substrate. It is also extremely effective to use a substrate that has a denuded zone and is capable of performing intrinsic gettering. Since epitaxial growth is performed in the presence of the SiO2 layer 4 as a separation region, it is desirable that the growth temperature be as low as possible in order to reduce the incorporation of oxygen from the SiO2. With the commonly used high-frequency heating method, there is a lot of contamination from the carbon susceptor, making it difficult to lower the temperature further. The wafer direct heating method using lamp heating, which does not involve bringing a carbon susceptor into the reaction chamber, provides the cleanest growth atmosphere and allows high-quality epitaxial layers to be grown at low temperatures.

Ultra-high purity fused sapphire, which has a lower vapor pressure, is suitable for the wafer support in the reaction chamber. The wafer direct heating method using lamp heating allows for easy preheating of the raw material gas and makes it easy to equalize the temperature within the wafer surface even when a large flow of gas is flowing.In other words, the wafer direct heating method using lamp heating generates almost no thermal stress. suitable for getting. UV irradiation of the wafer surface during growth further improves the quality of the epilayer.

Amorphous silicon is deposited on the sidewalls of the SiO2 layer that will become the isolation region 4 (step (c) in Figure 16).
The crystals near the interface with O2 and the separation region 4 become very good. After forming the high resistance n-layer 5 by selective epitaxial growth (step (d) in FIG. 16), the surface concentration 1
A P region 6 of about 20.times.10.sup.16 cm.sup.-3 is formed to a predetermined depth by diffusion from doped oxide or by diffusion using a low-dose ion-implanted layer as a source.

The depth of p region 6 is, for example, about 0.6 to 1 μm.

The thickness and impurity concentration of p region 6 are determined based on the following considerations. In order to increase the sensitivity, it is desirable to lower the impurity concentration in the p region 6 to reduce Cbe. Cbe is given approximately as follows.

However, Vbi is the emitter-base diffusion potential and is given by: Here, ε is the dielectric constant of silicon crystal, N
is the impurity density of the emitter, N is the impurity density of the portion of the base adjacent to the emitter, and ni is the intrinsic carrier concentration. The smaller N is, the smaller Cbe becomes, and the sensitivity increases. However, if N is made too small, the base region will be completely depleted in the operating state, resulting in a punch-through state, so it cannot be made too low. It is set to such an extent that the base region is not completely depleted and a punch-through state occurs.

Thereafter, a thermal oxide film 3 having a thickness of about several tens of amps to several hundreds of amps is formed on the surface of the silicon substrate by (H2+O2) gas-based steam oxidation at a temperature of about 800 to 900 degrees Celsius.

A nitride film (Si3N4) 302 with a thickness of about 500 to 1500 Å is formed thereon by CVD using (SiH4+NH3)-based gas. The formation temperature is about 700 to 900°C. NH3 gas, as well as HCl gas, is a commonly available product that contains a large amount of water. If H3 gas with a high moisture content is used as a raw material, the resulting nitride film will have a high oxygen concentration, resulting in poor reproducibility and the subsequent selective etching with the SiO2 film resulting in an inability to obtain a selective etching ratio.

The NH3 gas should also have a water content of at least 0.5 ppm or less. It goes without saying that the lower the water content, the more desirable it is. A PSG film 3 is further formed on the nitride film 302.
00 is deposited by CVD. For gas systems, for example, (
300~4 using N2+SiH4+O2+PH3)
A PSG film with a thickness of about 2000 to 3000 A is deposited by CVD at a temperature of about 50°C (step (e) in Fig. 16).
)). By a photolithography process including two mask alignment processes, an As-doped polysilicon film 304 is deposited on the n+ region 7 and on the refresh and read pulse application electrodes. In this case, a p-doped polysilicon film may be used. For example, by performing two photolithography steps, the PSG film, Si3H4 film, and SiO2 film on the emitter are all removed, and the areas where the refresh and read pulse application electrodes are provided are made of the underlying SiO2 film.
Only the PSG film and the Si3H4 film are etched, leaving two films. After that, As-doped polysilicon (H2+
SiH4+AsH3) or (H2+SiH4+As
H3) Deposit with gas by CVD method. The deposition temperature is 55
The temperature is about 0°C to 700°C, and the film thickness is 1000 to 2000A. Of course, non-doped polysilicon may be deposited by CVD and then As or P may be diffused. After the mask alignment photolithography process, the polysilicon film in other parts except on the emitter and on the refresh and read pulse application electrodes is removed by etching. Furthermore, when the PSG film is etched, the PSG film is etched due to lift-off.
The polysilicon deposited on the G film is removed in a self-aligned manner (step (f) in FIG. 16). The polysilicon film is etched using C2Cl2F4, (CBrF3+
The Si3N4 film is etched with a gas system such as Cl2).
Etch with gas such as H2F2.

Next, a PSG film 305 is deposited by the gas-based CVD method as described above, and then a contact hole is formed on the polysilicon film for the refresh pulse and read pulse electrodes by a mask alignment process and an etching process.

Under these conditions, Al. Al-Si, Al-Cu-Si
by vacuum evaporation or sputtering, or by plasma CVD using (CH3)3Al or AlCl3 as a raw material gas, or by cutting Al-C bonds or Al-Cl bonds of the above raw material gases by direct light irradiation. Al is deposited by a light irradiation CVD method. (
When carrying out the above CVD method using CH3)3Al or AlCl3 as a raw material gas, a large excess of hydrogen is allowed to flow. In order to deposit Al into a narrow and rapidly acidic contact hole, CV is carried out at a substrate temperature of 300 to 400 degrees Celsius in a clean atmosphere with no moisture or oxygen contamination.
D method is superior. After patterning the metal wiring 10 shown in FIG. 1, an interlayer insulating film 306 is deposited by CVD. 306 is the aforementioned PSG film or CV
A D-method SiO2 film or, if water resistance needs to be taken into account, a Si3N4 film formed by a (SiH4+NH3) gas-based plasma CVD method. Si3H
4 In order to keep the hydrogen content in the film low, (SiH
4+N2) A plasma CVD method using a gas system is used.

The Si3N4 film formed by the photo-CVD method is excellent in increasing the electrical breakdown voltage of the Si3H4 film formed by reducing the damage caused by the plasma CVD method and reducing the leakage current. There are two types of photo-CVD methods. (Si
H4 + NH3 + Hg) gas system with a mercury lamp from the outside.
537A ultraviolet irradiation method and (SiH4+NH
) 3 gas system is irradiated with 1849A ultraviolet light from a mercury lamp. In both cases, the substrate temperature is about 150 to 350°C.

After forming contact holes penetrating the insulating films 305 and 306 in the polysilicon on the emic 7 by reactive ion etching through a mask alignment process and an etching process, Al, Al-Si, Al-Cu-
All genus such as Si are deposited. In this case, since the aspect ratio of the contact hole is large, deposition by CVD is superior. After patterning the metal wiring 8 shown in FIG. 1, a Si3N4 film or PSG film 2 as a final passivation film is deposited by CVD (FIG. 16(g)).

In this case as well, the film produced by the photo-CVD method is superior. 12
is a metal electrode made of Al, Al-Si, etc. on the back surface.

The manufacturing method of the photoelectric substation device of the present invention involves a wide variety of steps, and FIG. 16 shows only one example.

An important point of the photoelectric conversion device of the present invention is how to suppress leakage current between p region 6 and n- region 5 and between p region 6 and n+ region 7 to a minimum.

Of course, it is possible to improve the quality of the n-region 5 and reduce dark current, but it is also possible to improve the quality of the n-region 5 by reducing dark current.
-The interface in region 5 is the problem. In FIG. 16, for this purpose, amorphous S is applied to the side wall of the separation region 4 in advance.
A method of epitaxial growth after depositing i was described. In this case, the amorphous Si is made into a single crystal by solid phase growth from the substrate Si during epitaxial growth, and the epitaxial growth is performed at a relatively high temperature of about 850° to 1000°C. Therefore, microcrystals often begin to grow in the amorphous Si before the amorphous Si is made into a single crystal by solid-phase growth from the Si substrate, which causes poor crystallinity. At lower temperatures, the rate of solid phase growth is relatively much higher than the rate at which microcrystals begin to grow in amorphous Si. ,
If amorphous Si is made into a single crystal, the characteristics of the interface will be improved. At this time, if there is a layer such as an oxide film between the Si substrate and the amorphous Si, the start of solid phase growth will be delayed, so an ultra-high cleanliness process is required so that such a layer is not included at the boundary between the two.

In addition to the above-mentioned furnace growth, for solid-phase growth of amorphous Si, a rapid annealing technique using flash lamp heating or an infrared lamp while keeping the substrate at a certain temperature for, for example, several seconds to several tens of seconds is also effective. When using such techniques, the Si deposited on the sidewalls of the SiO2 layer may be polycrystalline. However, it is necessary to deposit polycrystalline Si using a very clean process and to avoid containing oxygen, carbon, etc. in the grain boundaries of the polycrystalline material.

After the Si on the SiO2 side is single crystallized, the Si
This will result in selective growth.

When leakage current at the interface between the SiO2 isolation region 4 and the high resistance n-region 5 becomes a problem, the S of the high resistance n-region 5
This leakage current problem can be avoided by increasing the n-type impurity concentration only in the portion adjacent to the iO2 isolation region 4. For example, only a region of about 0.3 to 1 μm thick of the n-region 5 in contact with the isolated SiO2 region 4, e.g.
The n-type impurity concentration is increased to about -10 x 1016 cm-3. This structure can be formed relatively easily.

After forming a thermal oxide film of about 1 μm on the substrate 1, an SiO2 film is deposited on it by CVD to a required thickness and contains a predetermined amount of P. An isolation region 4 is created by depositing SiO2 thereon by the CVD method. During the subsequent high-temperature process, the phosphorus-containing SiO present in a sandwich form in the separation region 4
Phosphorus diffuses into the high resistance n-region 5 from the two films, creating a good impurity distribution with the highest impurity concentration at the interface.

In other words, the structure is as shown in FIG. 17. The isolation region 4 has a three-layer structure, where 308 is thermally oxidized SiO2, and 309 is phosphorous-containing CVD SiO2.
The film 301 is a CVD SiO2 film. Adjacent to isolation region 4 and between n- region 5, n region 307 is formed by diffusion from SiO2 film 309 containing phosphorus. 3
07 is formed all around the cell. With this structure, the base-collector capacitance Cbc becomes large, but the base-collector leakage current is drastically reduced.

In Fig. 16, an example was explained in which the isolation insulating region 4 is formed in advance and selective epitaxial growth is performed. U group separation technology (A. Ha
Yasaka et al. “U-groove iso
ration technique forhigh
speed bipolar VLSI'S", Tec
h. Dig. ofIEDN. P62.1982. reference)
It can also be done using .

A photoelectric conversion device according to the present invention forms a bipolar transistor in which a base region, most of which is adjacent to the semiconductor wafer surface, is in a floating state in a region surrounded by an isolation region made of an insulator, This is a device that photoelectrically converts optical information by controlling the potential of a floating base region with an electrode provided on a part of the base region via a thin insulating layer. An emitter region made of a high impurity concentration region is provided in a part of the base region, and this emitter is connected to a MOS transistor operated by a horizontal scan pulse. The aforementioned electrode provided on a portion of the floating base region via a thin insulating layer is connected to a horizontal line. The collector provided inside the wafer may be composed of a substrate, or depending on the purpose, it may be composed of high-concentration dopant-embedded regions separated for each horizontal line on a high-resistance substrate of the opposite conductivity type. be. With respect to the pulse voltage when refreshing the floating base region with the electrode provided through the insulating layer,
The applied pulse voltage when reading out the signal is substantially large. In fact, a pulse train with two types of voltages may be used,
As described in the double capacitor structure, the capacitance Cox of the read MOS capacitor electrode may be made larger than the capacitance Cox of the refresh MOS capacitor electrode. By applying a refresh pulse, optically excited carriers are accumulated in the floating base region, which is brought into a reverse bias state, to store a signal based on an optical signal, and when reading out the signal, the base-emitter region is deeply biased in the forward direction. The feature is that a readout pulse voltage is applied so that signals can be read out at high speed. As long as it has these characteristics, the photoelectric conversion device of the present invention may be realized in any structure, and it is needless to say that it is not limited to the structure described in the above embodiments.

For example, the structure is similar even if the conductivity type is completely reversed from that described in the above embodiment. however,
At this time, it is necessary to completely reverse the polarity of the applied voltage. In a structure where the conductivity types are completely reversed, the region would be n-type. That is, the impurities constituting the base are As and P. When the surface of a region containing As and P is oxidized, As and P
is piled up on the Si side of the Si/SiO2 interface. That is, a strong drift electric field is generated inside the base from the surface to the inside, and the optically excited holes immediately escape from the base to the collector side, and electrons are efficiently accumulated in the base.

If the base is p-type, the commonly used impurity is boron. When the surface of the p-region containing boron is thermally oxidized, boron is incorporated into the oxide film, so that the boron concentration in the Si near the Si/SiO2 interface becomes slightly lower than the boron concentration inside. Although this depth depends on the oxide film thickness, it is usually several hundred amps. Near this interface, reverse drift electrolysis occurs for electrons, and electrons photoexcited in this region tend to be collected on the surface. If this continues, the region where this reverse drift electrolysis occurs will become an insensitive region, but since the photoelectric conversion device of the present invention has an n+ region along a part of the surface, the p-region Si/
Electrons gathered at the SiO2 interface flow into this n+ region before being recombined. Therefore, even if there is a region where boron is reduced near the Si/SiO2 interface and a reverse drift electric field occurs, it hardly becomes a dead region. Rather, these regions are Si/Si
When present at the O2 interface, the accumulated holes are transferred to the Si/Si
By separating the holes from the O2 interface and making them exist inside, the effect of holes disappearing at the interface is eliminated, and the hole accumulation effect at the base of the p-layer becomes good, which is extremely desirable.

As described above, the photoelectric conversion device of the present invention accumulates carriers excited by light in the base region, which is the control electrode region in a floating state. That is, it is a device that should be called a Base Store Image Sensor, and is abbreviated as BASIS.

Since the photoelectric conversion device of the present invention can configure one pixel with one transistor, it is extremely easy to increase the density.At the same time, due to its structure, it has less blooming and smearing, has high sensitivity, and has a wide dynamic range. Since it has an internal amplification base function, it generates a large signal voltage regardless of wiring capacitance, so it has the characteristics of low noise and easy peripheral circuitry. For example, its industrial value as a future high-quality solid-state imaging device is extremely high.

In addition to the above-mentioned solid-state imaging device, the photoelectric conversion device according to the present invention can be applied to, for example, an image input device, a facsimile,
It can also be applied to workstations, digital copying machines, image input devices such as word processors, barcode readers, photoelectric conversion object detection devices for autofocus of cameras, video cameras, 8mm cameras, etc.

FIG. 8(b) shows a transient refresh operation, an accumulation operation,
The graph shows potential levels at the emitter, base, and collector sections during a read operation and a transient refresh operation.

The voltage level at each location is the potential seen externally, and there are some locations that do not match the internal potential level.

To simplify the explanation, the emitter-base diffusion potential is excluded. Therefore, when the emitter and base are shown at the same level in FIG. 8(b), there actually exists a diffusion potential applied between the emitter and the base.

In FIG. 8(b), states (1) and (2) perform a refresh operation, state (3) a storage operation, and states (4) and (
5) shows the read operation, and state (5) shows the operating state when the emitter is grounded. Further, the potential level indicates a negative potential on the upper side and a positive potential on the lower side with respect to 0 volt. It is assumed that the base potential before state (1) is zero volts, and that the collector potential is biased to positive potential in all states (1) to (6).

The above series of operations will be explained with reference to the timing diagram of FIG. 8(a).

As shown in the waveform 67 in FIG. 8(a), at time t1,
When a positive voltage, that is, a refresh voltage VRH is applied to the terminal 37, the potential 200 changes to state (1) in FIG. 8(b).
As explained above, a partial pressure is applied to the base. This potential gradually decreases toward zero potential between time t1 and t2, and at time t2 reaches the potential 201 shown by the dotted line in FIG. 8(b). As explained earlier, this potential is the potential VK that remains at the base in the transient refresh mode. At time t2, as shown in waveform 67, at the moment when the refresh voltage VRH returns to zero voltage, a voltage of The potential is the sum of the . That is, the base potential 202 shown in state (2) is given by:

When light enters such an emitter in a reverse bias state, holes generated by this light are accumulated in the base region, so as in condition (3), the intensity of the incoming light is Accordingly, the base potential 202 gradually changes toward a positive potential like base potentials 203, 203', and 203''. The voltage generated by this light is designated as Vp.

Next, as shown in waveform 69, when a voltage, ie, read voltage VR, is applied to the horizontal line from the vertical shift register, the voltage that becomes the base is added, so the base potential 204 when no light is irradiated is as follows. As explained earlier, the potential 204 at this time is
It is set so that the emitter is forward biased by about 0.5 to 0.6 V. Also, the base potential 20
5, 205', and 205'' are given respectively.

When the base potential is biased in the forward direction with respect to the emitter in this manner, electron Gron is injected from the emitter side, and the emitter potential gradually moves in the positive potential direction. Base potential 2 when no light is irradiated
The emitter potential 206 for 04 has a read pulse width of 1 to 2 when the forward bias is set to 0.5 to 0.6V.
When it is about μs, it is about 50 to 100 mV, and if this voltage is VB, the emitter potentials 207, 207', 2
07'', as in the previous example, linearity is sufficiently ensured if the pulse width is 0.1 μs or more, so VP + VB +
, VP'+VB, VP''+VB.

After a certain readout time, when the readout voltage VB reaches zero potential as shown in waveform 69, the voltage that becomes the base is added, so the base potential is applied with a readout pulse as shown in state (5). previous state.

In other words, it becomes a conductive bias state and the emitter potential stops changing6.In other words, the base potential 208 at this time is given as follows.The base potentials 209, 209', and 209'' are respectively given as follows.This is the state before reading starts ( 3) is exactly the same.

In this state (5), the optical information signal on the emitter side is read out to the outside. After this reading is completed, each switching MOS transistor 48, 48', 48''
becomes conductive, the emitter is grounded, and the emitter becomes zero potential as in state (6). This completes the refresh operation, storage operation, read operation, and then the state (
Returning to 1), at this time, before starting the refresh operation for the first time, the base potential starts from zero potential, but after completing one cycle, the base potential increases to Vp and Vp, respectively. ', Vp'' are added. Therefore, in this state, even if the refresh voltage VRH is applied, the base potentials are VK, VK+VP, and VK+VP', respectively.
, VK + VP'', and in this case, sufficient forward bias is not applied to the base, and the amount of forward bias is large in areas that are strongly illuminated, so optical information disappears, but in areas where the light is weak, It is clear from the calculation example of the refresh operation shown in FIG. 6 that information does not disappear but remains.

Such a phenomenon is unique to the transient refresh mode, and in the complete refresh mode, such a problem does not occur because it takes a long refresh time until the base potential always reaches zero potential.

A method that uses a transient refresh mode that allows high-speed refresh and that does not cause such inconvenience will be described below.

One way to solve this problem is the state (6
) brings the base potential 210 to zero potential. In this way, state (1)
When the refresh pulse is applied, the base potential is at zero potential as in the initial state, so reliable transient refresh mode operation is possible.

FIG. 18 shows an embodiment for achieving this. 1st
Figure 8(a) shows the cross-sectional structure of the optical sensor cell, and Figure 18(a) shows the cross-sectional structure of the optical sensor cell.
b) shows its equivalent circuit.

The emitter region 7 and the n+ region 270 of the basic photosensor cell shown in FIG. 1, which are shown in FIG. 18, form the drain and source of a MOS transistor, respectively, and are controlled by a gate 271 made of polysilicon or the like. It has become. Further, the n+ region 270 is connected to the base region 6 of the basic photosensor cell by a wiring 272. The other parts are the same as the basic photosensor cell shown in FIG.

FIG. 18(b) is an equivalent circuit of the structural diagram of FIG. 18(a), in which a MOS transistor 273 consisting of a drain region 7, a gate 271, and a source region 270 common to the emitter region of the photosensor cell is connected to the base region 6 of the photosensor cell. and wiring 27
2, the drain region is common to the emitter region, and the gate 271 is connected to a wiring 274, so that a pulse can be applied from the outside.

In refresh operation, storage operation, and read operation, wiring 2 is connected to the gate 271 of this MOS transistor.
It is assumed that a negative voltage is applied through 74 so that the channel of the MOS transistor becomes sufficiently non-conductive.

In state (6) of FIG. 8(b), the potential 2 of the base region
When 10 is negative, the emitter is grounded, and if the gate 271 is set to zero potential or positive potential in this state, the MOS
It is clear that the channel of the transistor becomes conductive, current flows and the base potential becomes zero potential.

In this way, the base potential becomes zero potential in state (6), so in the next refresh operation, the transient refresh mode operation is reliably performed as explained in FIG. becomes possible.

As described above, according to this embodiment, although the number of wires is increased, an image sensor capable of high-speed operation can be constructed by simply adding one simple MOS transistor.

In the embodiment shown in FIG. 18, wiring for connecting the source region 270 of the MOS capacitor electrode MOS transistor and the base region 6 of the photosensor cell, the gate 271 of the MOS transistor, and the emitter region 7 of the photosensor cell are used.
For convenience of explanation, the wiring 8 for It is possible to arrange each of them in other parts of the sensor cell, taking into account the shape of the incident window, the convenience of wiring, etc.

The above explanation uses Cox for both refresh and read.
Although the explanation is about the mode in which the refresh is performed by the electrode 9 on the p base through the p-base, it is also possible to perform the refresh with the nMOS. That is, in this case, only the readout pulse is applied to the electrode 9. To refresh the sensor cells along one horizontal line that have been read out, apply a positive voltage to 271 during the blanking period before reading out the sensor cells along the next horizontal line.
conduction, then the vertical lines 38, 38', .
A negative voltage -Vp is applied. The p base region is charged to -(Vp-VtH), and refreshing is completed. VtH is the threshold voltage of nMOS. This n
A MOS operates in such a manner that the channel and the n+ region 270 are at the same potential.

It is also possible to create a completely independent nMOS for p-based refresh. At this point, the n+ emitter is completely independent, and two more n+ regions 270 and 27 are formed in the p base.
5 is provided to constitute an nMOS.

Similar to that shown in FIG. 18(a), the n+ region 27
0 is directly connected to the p base 6 by electrode wiring, and the other n+ electrode 275 is connected to the gate 271 by electrode wiring.
A predetermined negative voltage -Vp is applied when a voltage is applied to.

FIG. 19 shows the circuit configuration diagram. Lines 201, 282, . . . for applying negative voltage are provided along the horizontal line.
...is provided.

When a read pulse is applied to the horizontal line 275 to read out the sensor cells along this horizontal line, and then a read pulse is applied to 276 to read the horizontal line below, the read pulse is applied to the gate of the refresh nMOS transistor of the sensor cell along the horizontal line 275, and the negative voltage -Vp is applied to the line 281 at that time, so that the reading of the sensor cell along the horizontal line 275 is completed.

[Brief explanation of the drawing]

1 to 6 are diagrams for explaining the main structure and basic operation of an optical sensor cell according to an embodiment of the present invention. Figure 1 (a) is a plan view, (b) is a sectional view, (c)
is an equivalent circuit diagram, FIG. 2 is an equivalent circuit diagram during read operation, FIG. 3 is a graph showing the relationship between read time and read voltage, and FIG. 4 (a) is a graph showing the relationship between storage voltage and read time. Figure 4 (b) is a graph showing the relationship between bias voltage and read time, Figure 5 is an equivalent circuit diagram during refresh operation, and Figures 6 (a) to (c) are graphs showing the relationship between bias voltage and read time. It is a graph showing the relationship with electric potential. 7 to 10 are explanatory diagrams of a photoelectric conversion device using the optical sensor cell shown in FIG. 1, FIG. 7 is a circuit diagram, and FIG. 8 (
8(a) is a pulse timing diagram, and FIG. 8(b) is a graph showing potential distribution during each operation. FIG. 9 is an equivalent circuit diagram related to the output signal, and FIG. 10 is a graph showing the output voltage from the moment of conduction in relation to time. 11, 12 and 13 are circuit diagrams showing other photoelectric conversion devices. 1st
FIG. 4 is a plan view for explaining the main structure of another optical sensor cell according to an embodiment of the present invention. Figure 15 shows the 14th
FIG. 2 is a circuit diagram of a photoelectric conversion device using the optical sensor cell shown in the figure. FIGS. 16 and 17 are cross-sectional views showing an example of a method for manufacturing a photoelectric conversion device of the present invention. FIG. 18 shows an optical sensor cell according to an embodiment of the present invention, in which (a) is a cross-sectional view and (b) is an equivalent circuit diagram thereof. FIG. 19 is a circuit configuration diagram using the optical sensor cell shown in FIG. 18. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... PSG film, 3... Insulating oxide film, 4... Element isolation region, 5... N- region (
collector region), 6...p region (base region), 7,
7'...n+ region (emitter region), 8... Wiring,
9... Electrode, 10... Wiring, 11... n+ region,
12... Electrode, 13... Capacitor, 14... Bipolar transistor, 15, 17... Junction capacitance, 1
6, 18... Diode, 19, 19'... Contact portion, 20... Light, 28... Vertical line, 30...
... Optical sensor cell, 31 ... Horizontal line, 32 ...
Vertical shift register, 33, 35...MOS transistor, 36, 37...terminal, 38...vertical line,
39...Horizontal shift register, 40...MOS transistor, 41...output line, 42...MOS transistor, 43...terminal, 44...transistor, 44, 45...load resistor, 46...terminal, 47.
...Terminal, 48...MOS transistor, 49...
Terminal, 61, 62, 63... Section, 64... Collector potential, 67... Waveform, 80, 81... Capacity, 82
, 83... Resistor, 84... Current source, 110, 101
, 102...horizontal shift register, 111, 112...
...Output line, 138...Vertical line, 140...
・MOS transistor, 148...MOS transistor, 150, 150'...MOS capacitor, 152
, 152'... optical sensor cell, 202, 203, 20
5...Base potential, 220...p+ region, 222,
225... Wiring, 251... P+ region, 252...
・n+ region, 253... Wiring, 300... Amorphous silicon, 302... Nitride film, 303... PS
G film, 304...polysilcon, 305...PSG
Film, 306... Interlayer insulating film. Figure 1 Figure 1 1; nl No. 17 Figure 7L/ 7L+/l 1゛ et al. Figure 18 Figure 19 Procedural amendment May 23, 1980 Director General of the Patent Office Kazutsu Wakasugi 1.41+- Indication Patent Application No. 120754 No. 1988-12 Name of the invention Photoelectric conversion device 3 Relationship with the 211 amendments Patent applicant name Tadahiro Omi 4, agent address 40 Toranomon 5-13-1, Minato-ku, Tokyo Mori Building of the invention in the specification Detailed explanation fence 6, content of amendment (1) rlOcIf113 on page 19, line 12 of the specification
Correct J to r l 013cm-3J. (2) The name 1i it on page 22, line 6 of the specification. (3) r l O [sec
] J is corrected as r 10-15[5ecl J. (4) Line 1 from the bottom of page 36 of the specification “1” Voltage V
” is supplemented with “voltage V^ as j. (5) lJl, 1+lI Book 41, line 5 from the beginning to 4
Row 11 [, buffer MOS transistor 33.33'
, 33"J are deleted. (6) Correct "Hakutsurip" in line 11, two lines from the bottom of No. 45 of the specification, to "clip". (7) Insert "do" before "kiri'↓ni" on page 53, line 6 of the specification. (8) Insert "ni" after "middle" in "7 lines 1 from the bottom of page 53 of the specification". (9) “Emitter 7, wa” on page 64, line 1 of the specification
is corrected as "emitter 7.7'is". (10) In the 64th line of page 64 of the specification, "emitter is contact hole 1" is corrected to "emitter 7' is contact hole 19'". (11) Correct "to horizontal line 3" in "Meibu 1, page 64, line 8 from the bottom" to "to horizontal line 31'". (12) "In cell 15" in the sixth line from the bottom on page 64 of the specification is corrected to "in cell 152'." (13) "rMOs capacitor 15" on page 64 of the specification, line 6 from the bottom, 1] is corrected to "rMOs capacitor 150'". (14) 5 from the bottom of page 64 of the specification? i11's "Water=l"
"to the il mi line" is supplemented with "to the horizontal line 31'". (15) "Of the optical sensor cell 15" in the third line from the bottom of page 64 of the specification is corrected to "of the optical sensor cell 152'". (16) Correct "of the optical sensor cell 15" in "Line 1 of the second row from the bottom of page 64 of the specification" to "of the optical sensor cell 152". (17) ``To the water line 3'' on page 66, lines 6 to 7 and line 12 of the specification is supplemented with ``to the tree/IL line 31'.'' (18) Ming MIl, page 66, lines 12-13 [03
The light sensor is passed through the capacitor 15 to the cell 15.
The optical sensor cell 1 is connected through the rMOS capacitor 150'.
52'.'' (19) 2 lines from the bottom of page 66 of the specification “1 and 1 line 1”
Then, "Photosensor cell" in "Page 67, Line 8, 1" is corrected to "Photosensor cell". (20) Correct "collector" in specification 7 (-; 5th line from directly below 68th) to [j recta j. (21) Specification hot water temperature 68 4th line from directly below 11 and 3 from do
"n embedding area" in the row is corrected to "n+embedding area". (22) Supplement 1 to “(C). (24) Correct the statement on page 78, line 4 of Akira, Bunsho. (25) Correct [N is the impurity concentration of the emitter, N is the base] on page 78, line 6 of the specification to ``No means the emitter concentration. "Impurities are 0 degrees, NA is base" and corrected. (26) rN J on page 78, lines 8 and 9 of the specification is corrected to "NA". (27) rsio on page 86, line 10 of the specification, 309
``is corrected to rsio2.309''. (28) "To the present invention" on page 91, line 12 of the specification is supplemented with "of the present invention." (28) On page 96 of the specification, line 4 from the bottom, ``Correct ``Gron'' in 1 to ``Tron''. (30) Details! ? Correct rVp+VB 10J on page 97, line 6 to rvp+ve J. (31) In the 7th line from the bottom of page 100 of the specification, "See it in Figure 18" is corrected to "See it in Figure 18." (32) "Shirush" in the third line of page 103 of the specification is replaced with "
"Refreash," he corrected.

Claims (1)

[Claims] 1 The control electrode region of a semiconductor transistor consisting of two main electrode regions of the same conductivity type and the control electrode region of the opposite conductivity type to the main electrode region is brought into a floating state, and the potential of the control electrode region brought into the floating state an accumulation operation in which carriers generated by light are accumulated in the control electrode region set in a floating state by controlling via a capacitor; a readout operation in which the accumulated voltage generated in the control electrode region by the accumulation operation is read out; In a light conversion device having a structure capable of performing a refresh operation to eliminate carriers accumulated in the control electrode region, a part of the control electrode region in a floating state has a conductivity opposite to that of the control electrode region. A main electrode region of an insulated gate transistor for controlling the potential of the control electrode region with at least one high concentration region of the opposite conductivity type provided adjacent to the surface other than the main electrode region. A photoelectric conversion device characterized by the following.