JPH0340573A - Photoelectric converter - Google Patents

Abstract

PURPOSE:To reduce the after-image at high speed operation by fixing a potential of a main electrode region to control the potential of a control electrode region independently, thereby biasing the junction between the control electrode region and the main electrode region in forward direction thereby eliminating the stored electric charge. CONSTITUTION:The potential of a control electrode region at each refresh operation is controlled independently of the potential of the main electrode region, and the junction between the control electrode region and the main electrode region connecting to an output circuit comprising vertical lines 38-38'', a horizontal shift register 39, MOS transistors(TRs) 40-40'', an output line 41, a MOS TR 42, an output TR 44, and a load resistor 45 is biased forward at the readout, and the main electrode region connecting to the output circuit is refreshed at refreshing. In addition, the resetting for setting the potential of the control electrode region fixing directly the potential of the control elec trode region and the resetting of the main electrode region are combined. Thus, excellent high speed refreshing is attained.

Description

[Detailed description of the invention] The present invention relates to a photoelectric conversion device.

Research on photoelectric conversion devices, particularly solid-state Ti image devices, has been actively conducted along with the progress of semiconductor technology, and some are beginning to be put into practical use.

These solid-state imaging devices can be roughly divided into CCD type and M
It is classified into two types of OS. The CCD type imaging device is MO
A potential gate is formed under the S capacitor electrode, and the charge generated by the incidence of light is transferred to this well. During readout, these potential wells are sequentially moved by a pulse applied to the electrode, and the accumulated charges are transferred. It uses the principle of transferring the charge to the output amplifier section and reading it out.

Furthermore, some CCD type imaging devices use a pn junction diode structure for the light receiving section and a CCD structure for the transfer section. On the other hand, the MOS imaging device is
The charge generated by the incidence of light on the photodiode consisting of a pn junction constituting the light receiving section is accumulated, and when read out, the MOS connected to each photodiode is
Accumulated by sequentially turning on switching transistors? l! It uses the principle of reading out the load to the output amplifier section.

The CCD type imaging device has a relatively simple structure and two
Considering the noise that can be generated, only the capacitance Jl value of the charge detector consisting of the floating diffusion in the final stage contributes to random noise, so it is a relatively low-noise imaging device and is capable of low-light photography. . However, CC
Due to process constraints for manufacturing a D-type imaging device, an MO5-type amplifier is placed on-chip as an output amplifier, and therefore noticeable l/f noise is generated from the interface between the silicon and the SiO2 film on the image. Therefore, although it is said to have low noise, there are limits to its performance. In addition, when increasing the number of cells and increasing the density in order to achieve higher resolution, the maximum amount of charge that can be stored in one potential well decreases.
Since the dynamic range cannot be maintained, this will become a major problem as solid-state imaging devices become higher in resolution in the future.

Furthermore, since a CCD-type imaging device transfers accumulated charges by sequentially moving the potential wells, even if one of the cells has a defect, the '+1 charge transfer may stop there, or , it got extremely bad,
! It also has the disadvantage of not increasing manufacturing yield.

On the other hand, MOS type imaging devices are structurally a little more complex than CCD type imaging devices, especially frame transfer type devices, but they can be configured to increase storage capacity.
It has the advantage of having a wide dynamic range.
Furthermore, even if one of the cells has a defect, because of the X-Y addressing method, the defect does not affect other cells, which is advantageous in terms of manufacturing yield. However, in this MOS type image device, wiring capacitance is connected to each photodiode when reading the @ number, so an extremely large signal voltage drop occurs, resulting in a drop in the output voltage, and the wiring capacitance is large. CCD
Compared to conventional imaging devices, these devices have drawbacks such as difficulty in low-light photography.

In addition, as the resolution of imaging devices increases in the future, the size of each cell will be reduced and the charge product will decrease.In contrast, the wiring capacitance determined by the chip size will decrease even if the line width is made thinner. does not fall too much.For this reason, MO3I
Imaging devices become increasingly unsuitable for S/objectives.

Although CCD type and MOS type imaging devices have advantages and disadvantages, they are gradually approaching a level of practical use. However, it can be said that there are essentially major problems in promoting the higher resolution that will be required in the future.

Regarding those solid-state imaging devices, Japanese Patent Application Laid-Open No. 58-15087
8 “Semiconductor imaging device”, JP-A-58-157073
“Semiconductor imaging side”, JP-A-58-185473 “
A new method has been proposed for "semiconductor imaging devices".CC
D type.

While a MOS type imaging device stores charges generated by incident light in the main transistor (e.g. source of a MOS transistor), the method proposed here stores charges generated by incident light in Control electrode (e.g. the base of a bipolar transistor).

It is based on a new concept of controlling the flowing current using the charges accumulated in the SIT (static induction transistor (SIT) or the gate of a MOS transistor) and generated by light. That is, CCD type, MOS
In contrast to type 2, which reads out the accumulated charge itself to the outside, the method proposed here uses the amplification function of each cell to amplify the charge and then reads out the accumulated charge. Also, looking at it from another perspective, it is read out as a low impedance output by impedance conversion. Therefore,5 the method proposed here has high output, wide dynamic range, and low noise, and because the carriers (charges) excited by the optical signal accumulate in the control electrode,
It has several advantages such as non-destructive readout. Furthermore, it can be said that this method has the potential for higher resolution in the future.

However, this method is basically an X-Y address method, and the element structure described in the above publication combines amplification elements such as bipolar transistors and SIT transistors in each cell of the conventional MO3 type imaging device. The basic structure is as follows. Therefore, it has a relatively complicated structure, and although it has the possibility of achieving high resolution, there is a limit to how high resolution can be achieved as it is.

An object of the present invention is to provide a new photoelectric conversion device that has an amplification function in each cell but has a very simple structure and can sufficiently cope with future increases in resolution.

This purpose is to bring the control electrode regions of a semiconductor transistor, which are made up of two main electrode regions of the same conductivity type and a control electrode region of the opposite conductivity type from the main electrode regions, into a floating state, and to remove the control electrodes in the floating state. an accumulation operation in which carriers generated by light are accumulated in the floating control electrode region by controlling the potential of the region via a capacitor;
In a photoelectric conversion device having a structure that performs a readout operation for reading out the accumulated voltage generated in the control electrode region by an accumulation operation and a refresh operation for extinguishing carriers accumulated in the control electrode region, the control electrode is placed in a floating state. A photoelectric conversion device characterized in that a highly impurity region of the same conductivity type as the region is provided and a control electrode region in a floating state forms a transistor structure.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram illustrating the basic structure and operation of a photosensor cell that constitutes a photoelectric conversion device according to an embodiment of the present invention.

FIG. 1(a) shows a plan view of the optical sensor cell, and FIG. 1(b) shows a plan view of the optical sensor cell.
) is a cross-sectional view of the AA' part of the plan view of Fig. 1(a), and f
Figure J41 (C) shows its equivalent circuit, and parts common to Figures 1 (a), (b), and (c) are given the same numbers.

In the WSt diagram,! I! Although the column layout layout diagram is shown,
Of course, in order to increase the horizontal resolution, a pixel shifting method (interpolation arrangement method) can also be used.

As shown in FIGS. 1(a) and (b), this optical sensor cell is made of a silicon substrate doped with impurities such as phosphorus (P), antimony (sb), and arsenic (As) to make it n-type or n0-type. In step 1, there is a passivation film 2 usually made of PSG, etc.: an insulating oxide film 3 made of silicon oxide JPJ (SiO2);
: Element isolation region 4 made of an insulating film made of S+02 or SilN, or a polysilicon film, etc. for electrically insulating between adjacent photosensor cells; Impurity formed by epitaxial technology etc. j! ! A low concentration n-region 5: A p-region 6, which becomes the base of a bipolar transistor, doped with an impurity such as poron (B) using an impurity diffusion technique or an ion implantation technique. n” region 7 which becomes the emitter of a bipolar transistor formed of aluminum; for example, aluminum (At
), At-9i, Al-Cu-3i, or other conductive material 8; Pole 9; its wiring 10; N+ region t with high impurity concentration formed by impurity diffusion technique 1 to make ohmic contact with the back surface of substrate 1;
l Give the potential of the substrate. That is, it is composed of an "electrode 12" made of a conductive material such as aluminum for applying the collector potential of the bipolar transistor.

Incidentally, reference numeral 19 in FIG. 1(a) is a contact portion for connecting the n-region 7 and the wiring 8. Further, the alternating portions of the wirings 8 and 10 are so-called two-layer wirings, and are insulated from each other by insulating regions formed of an insulating material such as Si02. That is, it has a two-layer metal wiring structure.

Capacitor Cox13 in the equivalent circuit of 7JIJ1 diagram (c)
is composed of an MO3 structure including an electrode 9, an insulating layer 3, and a P region 6, and the bipolar transistor 14 has an n region 7 as an emitter, an n- region 5 with a low pWWB2 impurity concentration as a base, and an n region 5 as a collector. Or, it is composed of each part of n area l. As is clear from these drawings, the P region 6 is made into a floating m region.

The second equivalent circuit in FIG. 1(C) includes a bipolar transistor 14, a base-emitter junction capacitance Cbc17, a base-emitter pn junction diode Dbe16. This is expressed using a base-collector junction capacitance Cbc17 and a base-collector pn junction diode Dbc18.

The basic operation of the optical sensor cell will be explained below with reference to FIG.

The basic operation of this photosensor cell consists of a charge accumulation operation based on two-first incidence, a readout operation, and a refresh ash operation. In charge storage operation, for example, the emitter is grounded through wire 8 and the collector is biased to a positive potential through wire 12. Also, the base has a capacitor in advance! It is assumed that a positive pulse voltage is applied to the emitter 13 through the wiring 10 to give it a negative potential, that is, a reverse bias state with respect to the emitter 7. The operation of biasing the base 6 to a negative potential by applying a pulse to the Cox 13 will be explained in detail later when the refresh ash operation is explained.

In this state, when light 20 enters from the front side of the photosensor cell as shown in FIG. 1, electron-hole pairs are generated within the semiconductor.

Of these, electrons flow toward n-region 1 because n-region 1 is biased to a positive potential, but holes are rapidly accumulated in the pm region. As a result, the potential of p region 6 gradually changes toward a positive potential.

In FIGS. 1(a) and 1(b), the lower surface of the light-receiving surface of each sensor cell is mostly occupied by the p region, with a portion becoming the n◆ region 7. Naturally, the degree of electron-hole pairs excited by light is larger the closer to the surface, and therefore many electron-hole pairs are excited by light also in the P region 6. The photoexcited electrons in the p region immediately flow out of the p@ region 6 without recombining,
If the structure is such that they are absorbed in the nfi region, the holes excited in the P region 6 will be accumulated as they are, and the holes will be absorbed in the P region 6.
changes towards positive potential. When the impurity concentration in p region 6 is made uniform, electrons excited by light diffuse to the pn'''' junction between p region 6 and n- region 5, and then flow into the n- region. It is absorbed by the n collector region 1 due to the drift caused by the applied strong electric field. Of course, it is possible for electrons to travel within the p region 6 by diffusion alone, but if the structure is configured so that the p-based impurity concentration decreases from the surface to the inside, this impurity concentration difference , electric field E in the base from inside to the surface
d.

occurs. Here, W is the depth from the light incident surface of the p region 6, k is the Portzmann constant, T is the absolute temperature, q is the unit type/load, NAl is the impurity concentration in the p base region 6, and NAI is the impurity concentration of the p base region 6. Non-N! at the interface with the n-high resistance region 5 of the pffl region 6! It is the substance concentration.

Here, if N As /N 4 > 3, the movement of electrons in p region 6 is performed by drift rather than diffusion. That is, in order to effectively operate the carriers excited by light in the p-region 6 as a signal, the impurity concentration of the p-region 6 must decrease from the light-incidence side surface toward the inside. If the p region 6 is formed by diffusion, the impurity concentration decreases toward the inside compared to the surface on the light incident side.

A portion below the light-receiving surface of the sensor cell is occupied by the n+ region 7. The depth of n9 region 7 is usually 0.2 to 0.3
, an increase or less, the amount of light absorbed in the n area 7 is originally not very large, so there is no problem.

However, for light on the short wavelength side, especially blue light, the presence of the n area 7 causes a decrease in sensitivity. The impurity concentration of n+ region 7 is usually I x 10! It is designed to be about ocm-3 or higher. The diffusion distance of holes in the n region 7 doped with impurities at such a high concentration is 0.15~
0.27A11. Therefore, in order to effectively flow the holes photoexcited in the n+ region 7 into the p region 6, the n4'' region 7 must also have a structure in which the impurity concentration decreases from the light incident surface toward the inside. It is desirable that n+
If the impurity concentration phase separation of region 7 is as described above, a strong drift electric field will be generated inward from the light incident side surface, and the holes photoexcited in n" region 7 will immediately drift to p region 6. If the impurity concentration of the flowing n-region 7 and p-region 6 is configured to decrease inward from the light-incidence side surface, the n-region 7, which exists on the light-incidence side surface of the sensor cell, All of the optically excited carriers in the P region 6 function effectively as optical signals. Due to impurity diffusion from the silicon oxide film or polysilicon film doped with As or P at a high concentration, this n
By forming the region 7, it is possible to obtain an n region having the desired impurity gradient as described above.

Eventually, due to the accumulation of holes, the base potential changes to the emitter potential, in this case to the ground potential,
There he will be crissive.

To put it more precisely, the base and emitter are biased deeply in the forward direction, and the holes accumulated in the base are crisscrossed at a voltage that starts flowing out to the emitter. That is, the saturation potential of the photosensor cell in this case is approximately given by the potential difference between the bias potential when p region 6 is initially biased to a negative potential and the ground potential. When n-region 7 is not grounded and accumulates charges generated by optical input in a floating state, charges can be implanted in p-region 6 to approximately the same potential as n-region l.

Although Shio 2-hi is a qualitative and general explanation of the charge storage operation, a more specific and quantitative explanation will be given below.

The spectral sensitivity distribution of this optical sensor cell is given by the following equation.

X (1-exp(-αy)) ・T [A/
WlHowever, the input is the wavelength of light [gm! , α is the attenuation coefficient of light in the silicon crystal [gs-'], and x is the attenuation coefficient at the semiconductor surface. 1 ■ Causes coupling loss and does not contribute to sensitivity
ad 1ater (dead area) thickness rgm],
y is the thickness of the shrimp layer fIL*), T is the transmittance, i.e.
Each shows the ratio of the amount of light that effectively enters the semiconductor, taking into account reflection and the like with respect to the amount of incident light. Spectral sensitivity S (on) and irradiance E of this optical sensor cell
Using e(in), the photocurrent KP is calculated by the following formula.

Ip = f-S (in) eEa (in) - d in [μA/cm”
l Irradiance Ee (in) [gW * am-”
s nm-' ] is given by the following equation.

[←w e am-"・nm-'] However, E is the illuminance [Lux] of the sensor's light-receiving surface, and P (in) is the p-spectrum of light incident on the sensor's light-receiving surface. is the relative luminous sensitivity of the human eye.

Using these formulas, the shrimp thickness I't! 4kr
In an optical sensor cell with m, A light [(2854'K)
The sensor light receiving surface illuminance is 1 [Luxl, approximately 280 nA/ca+ -” cr) light 71!FQ
flows, and the number of incident photons or the number of electron-hole pairs generated is 1.8 XIO"770m
It is about 2 seconds.

Further, at this time, the potential Vp generated by the accumulation of holes erected by light in the base is given by Vp=Q/C. Q is the amount of accumulated hole I4, and C
is the junction capacitance obtained by adding Cbc15 and Cbc17.

Now, the impurity concentration of n◆ region 7 is 1020 am−', the impurity concentration of p region 6 is 5×10” cm−’,
The impurity concentration of n- region 5 is set to 10 cm-'', n+
The area of region 7! 6gm”, the area of p region 6 is 84pm
2. The junction capacitance when the thickness of the n-region 5 is set to 3 layers is approximately 0.014 pF, and the number of holes accumulated in the p-region 6 is determined by the accumulation time 1/eQsec,
If the effective light-receiving area, that is, the area obtained by subtracting the area of electrodes 8 and 9 from the area of p-region 6, is approximately 58 JJ, 11'', it becomes 1.7 x 10'. Therefore, the potential Vp generated by light incidence is approximately 190 mV. Become.

What should be noted here is that as the resolution increases and the cell size decreases, the amount of light incident on each photosensor cell decreases, and the accumulated +ta charge IQ decreases as well. With the reduction of the cell size, the junction capacitance also decreases by a small amount in proportion to the cell size, so the potential Vp generated by light incidence remains almost constant.

This is because the optical sensor cell according to the present invention, as shown in FIG. 1, has an extremely simple structure, making it possible to have an extremely large effective light-receiving surface.

This is one of the reasons why the photoelectric conversion device of the present invention is advantageous compared to interline type COD.
In a D-type TI image device, in order to secure the amount of charge to be transferred, the area of the transfer section becomes relatively large, which reduces the effective light-receiving surface and reduces the sensitivity, that is, the voltage generated by light incidence. It turns out. In addition, in the interline type CCDyIJ and the 9-position imaging system, the saturation voltage is limited by the size of the transfer section and gradually decreases, whereas in the optical sensor cell according to the present invention,
As mentioned above, the saturation voltage is determined by the bias voltage when p-region 6 is initially biased to a negative potential, and a large saturation voltage can be ensured.

The operation of reading out the voltage generated by the charges accumulated in p region 6 to the outside will be described below.

In the read operation state, the wires 8, 8, and 8 are in a floating state, and the collector is held at a positive potential Vcc.

An equivalent circuit is shown in FIG. 2. Now, if the potential when the base 6 is biased to a negative potential before light irradiation is -vI, and the accumulated voltage generated by light irradiation is Vp, the base potential is as follows. The potential is -V@+Vp. In this state, when a positive voltage Q for reading is applied to the electrode 9 through the wiring lO, this positive potential Vll is changed to the oxide film capacitance Cox1.
3, the base-emitter junction capacitance JiCbe15, and the base-collector junction capacitance Cbc7, and a voltage is added to the base.

Therefore, the base potential becomes. If the following conditions are satisfied, the base potential becomes exactly the accumulated voltage Vp generated by light irradiation. When the base potential is biased in the positive direction with respect to the emitter potential in this way, electrons are injected from the emitter to the base, and since the collector potential is positive, they are accelerated by the drift electric field. Reach the collector. The current flowing at this time is given by the following equation.

However, Aj is the junction area between base and emitter.

is the unit charge (t, 8×10 coulombs), Dn is the electron diffusion constant in the base, nl is the electron concentration as minority carriers at the emitter end of the p base, W is the base width, and NAe is the emitter of the base. acceptor concentration at the edge, NAe is the acceptor concentration at the collector edge of the base, k is Portzmann's constant, T
is the absolute temperature and Ve is the emitter potential.

It is clear from the above equation that this current flows until the emitter potential Ve becomes equal to the base potential, that is, the accumulated voltage Vp generated by light irradiation here. At this time, the temporal change in the emitter potential Ve is calculated by the following equation.

X (11!P (Vp -Ve)
-1)T However, here, the wiring $ -l Cs is the capacitance 21 of the wiring 8 connected to the emitter.

The m3 diagram shows an example of a temporal change in emitter potential calculated using the above formula.

According to FIG. 3, it takes about 1 second for the emitter potential to become equal to the base potential. This is because when the emitter potential We approaches Vp, less current flows. Therefore, the means to solve this problem is to first apply a positive voltage V to the electrode 9.

Although the following conditions have been set, it is possible to consider a method of inserting a condition in place of this condition and biasing the base potential by an extra amount of Vsia* in the forward direction.

The current flowing at this time is given by the following equation.

X (exp −(Vp + Vs+as −V
@) -1)T In Figure 4(a), when Vm+asxO, 8V,
After a certain period of time, vR applied to the electrode 9 is returned to zero volts and the flowing current is stopped. This shows the relationship between the readout voltage, that is, the emitter potential, and the accumulated voltage vP. ), a constant potential depending on the read time due to the bias voltage component is always added to the read voltage, but the value obtained by subtracting the gain is plotted. When the positive voltage vyoi applied to the m-pole 9 is returned to zero volts, a voltage opposite to that when applied is added to the base potential, so the base potential becomes the same as before applying the positive voltage vyoi. state, i.e., -V, and the emitter is reverse biased, so current flow stops. According to FIG. 4(a), if a readout time of about 100ns or more (i.e., the time during which the electric current is applied to the electrode 9) is obtained, the linearity of the storage voltage Vp and the readout voltage can be ensured over a range of about 4 digits. This shows that high-speed reading is possible. In Figure 4(a), 45
The line ' is the result when sufficient time is taken for reading. The line ' is the result when sufficient time is taken for reading. In the above calculation example, the capacitance C8 of wiring 8 is set to 4 pF, This is 0.014p of the junction capacity of Cbe+Cbe
Although P is about 300 times larger than F.
The accumulated voltage Vp generated in region 6 does not undergo any attenuation,
Furthermore, FIG. 4(a) shows that the data can be read out at extremely high speed due to the effect of the bias voltage. This is because the amplification function, that is, the charge amplification function, of the photosensor cell related to M4t& described above is working effectively.

On the other hand, in the conventional MO5 type imaging device, the accumulated voltage V
p is the influence of the wiring capacitance C3 in such a read process cj 11Vp / (Cj +Cs) (however, C
j is the pn junction capacitor of the light receiving part of the MO5 type image pickup device), which has the disadvantage that the read voltage value drops by about 52 digits. For this reason, in the MO3 type camera, static pattern noise due to variations in the parasitic capacitance of the sweeping MOS transistor for external readout, or random noise generated due to wiring heat, that is, large output capacitance, is large. However, in the optical sensor cells having the configurations shown in FIGS. 1(a), (b), and (C), the stored @ voltage itself generated in the p region 6 is transmitted to the outside. Since this voltage is quite large, fixed pattern noise and random noise caused by the output capacitance are relatively small, making it possible to obtain a signal with an extremely good S/N ratio.

Previously, it was shown that when the bias voltage Vs+aS was set to 0.6V, linearity of about 4 lines could be obtained with a high-speed readout time of about 100nsec. The results of calculating the relationship are shown in more detail in FIG. 4 (1)).

In FIG. 4(b), the horizontal axis is the bias voltage Visas, and the vertical axis is the read time.

The parameters are: when the M product voltage is l mV, the read voltage is 80%, 290%, and 95% of 1 mV.

It shows the time dependence until it reaches 98%. Figure 4 (
As shown in a), when the storage voltage is 1 mV, it is 80%, 90%, 95%, and 98%, respectively, and it is clear that the values are even better at higher storage voltages. It is.

According to this FIG. 4(b), the bias voltage Vllia3
For o, ev, the readout time is 0.12gg for the readout voltage to be 80% of the storage voltage, 0.27as for the readout voltage to be 90%, 0.541J for the readout voltage to be 95%,
3. It can be seen that it takes 1.4 μs to reach 98%. Furthermore, it is shown that even higher speed reading is possible if the bias voltage V aias is made larger than O and SV. In this way, once the readout time and required linearity are determined from the overall design of the imaging device, the required bias voltage V sias can be determined using the graph in FIG. 4(b). can.

Another advantage of the optical sensor cell having the above configuration is that the holes accumulated in the p region 6 can be read out nondestructively because the probability of recombination of electrons and holes in the p region 6 is extremely small. That is, when the voltage Vll applied to the electrode 9 during reading is returned to zero volts, the potential of the p region 6 becomes the reverse bias state before applying the voltage v, and the accumulated voltage Vp generated by light irradiation is
It will remain as it is unless exposed to new light. This means that when the optical sensor cell according to the above configuration is configured as a photoelectric conversion device, new I functions can be provided in terms of system operation.

The time during which the M product voltage Vp can be held in the P region 6 is extremely long, and the maximum holding time is rather limited by the dark current thermally generated in the depletion layer of the junction.

In other words, this thermally generated dark current saturates the optical sensor cell. However, in the photosensor cell according to the above configuration, the region where the depletion layer spreads is the n- region 5 which is a low impurity concentration region, and this n'' region 5 has a range of 10"am-' to 10"Cs-' Since the impurity concentration is extremely low, the crystallinity is good, and fewer electron-hole pairs are thermally generated compared to MOS type and CCD5!11fi! devices.

For this reason, the dark current is small compared to other conventional devices, that is, the optical sensor cell according to the above configuration has an essentially low dark current noise structure.

Next, an explanation will be given of the operation of refreshing/throwing the charges accumulated in p region 6.

1-, 21 In the optical sensor cell according to E&, as already mentioned, fc! accumulated in the p region 6! , the charge is not erased by the read operation, so in order to input new optical information, a refresh operation is required to erase the previously accumulated charge. At the same time, it is necessary to raise the potential of p-region 6, which is in a floating state, to a predetermined negative voltage.

In the optical sensor cell having the above configuration, the refresh 1/refresh operation is also performed by applying a positive voltage to the electrode 9 through the wiring 10, similarly to the read operation. At this time, the emitter is grounded through the wiring 8. The collector is grounded or kept at a positive potential through the electrode 12. An equivalent circuit for a refresh operation is shown in FIG. 5, in which the collector side is grounded.

When a positive voltage VIIH is applied to the electrode 9 in this state, the base 22 has an oxide film capacitance SLCox 13, a base emmy 2 1tJ1m total capacitance 1cbel 5, and a base-collector junction capacitance cbc17. voltage is applied instantaneously as in the previous read operation. Due to this voltage, the base-emitter junction diode Dbe16 and the base◆collector junction diode Dbc18 are forward biased and become conductive, current begins to flow, and the base potential gradually decreases.

At this time, the change in the potential V of the base in a floating state is approximately expressed by the following equation.

However, 1> is the current flowing through the diode Dbc, and 12 is the current flowing through the diode Dbe. A~ is base mentei, Ae
is the emitter area, DP is the diffusion constant of the hole in the collector, p is the hole 11 degrees in the thermal equilibrium state in the collector, Lp is the mean free path of the hole in the collector, and DPI is the hole in the thermal equilibrium state in the base. Work 1
/cutrone concentration. In i, the current due to hole injection from the base side to the emitter can be ignored because the impurity concentration of the emitter is sufficiently higher than that of the base.

The formula shown in (a) is an approximation of stepwise bonding, and in actual devices, it deviates from stepwise bonding, and the base thickness is thin, and... 1. Although it is not strict as it has a rough concentration intervention, the reflex action can be controlled by a considerable 'fLQ.
1 can be explained.

Of the current i flowing between the base and collector in L&, q”
DP" PIll/LP indicates a current due to holes, that is, a component in which holes flow from the base to the collector side. In order to facilitate the flow of current due to holes, in the optical sensor cell with the above configuration, the impurity concentration of the collector is normally set to 1. It is designed to be a little lower than bipolar transistors.

An example of the time dependence of the base potential calculated using this formula is shown in FIG. 6. The horizontal axis is the refresh voltage V 1l
14 is applied to the electrode 9, that is, the refresh time, and the vertical axis indicates the base potential, and the initial potential of the base is used as a parameter.

The initial potential of the base is the riff 1/-/sh voltage Vllll
At the moment when is applied, the potential exhibited by the base on the floating J island is V11@.

It depends on Cox, Cbs, Cbc and the charge IMed on the base.

If you look at Figure 6, the base potential will always reach one v on the semi-logarithmic graph after a certain period of time, regardless of the initial potential.
r, descending along the line.

Figure 6(b) shows experimental values of base potential change with respect to refresh time.Compared to the calculation example shown in Figure 6(a), the test device used in this experiment has considerably larger dimensions. Although the absolute value does not match the calculation example, it has been demonstrated that the base potential change with respect to the refresh time changes linearly on a semi-logarithmic graph. This experimental example shows the value when both the collector and emitter are grounded.

Now, due to light irradiation? The maximum value of I product voltage Vp is set to 0.4[V
If the voltage V applied to the base by the refresh voltage ViIH is 0.4[Vl, the maximum value of the initial base potential is 0.8[Vl] as shown in FIG. is on the jll\ line, the base potential begins to fall, and 10-
'After [sec], the change in potential matches the change in potential when no light is applied, that is, when the initial base potential is 0.4 [Vl].

There are two ways in which the p region 6 can be charged to a negative potential by applying a positive voltage for a certain period of time through the MOS capacitor Cox and removing the positive voltage. One is p region 6
n, where holes with positive charges are mainly in a stacked state
This is an operation in which negative charges are accumulated by flowing out into region 1.

Holes in p region 6 flow unilaterally to ngA region 1, and n
In order to prevent too many electrons from region l from flowing into pwi region 6, the impurity density of p region 6 may be made higher than the impurity density of n region l. On the other hand 5 n7 region 7
Electrons from the p-region 1 and n-region 1 flow into the p-region 6 and recombine with holes, thereby allowing negative charges to accumulate in the p-region 6. In this case, the impurity density of n region 1 is higher than that of p region 6. The operation of accumulating negative charges due to holes flowing out from p-region 6 is much faster than the operation of accumulating negative charges due to electrons flowing into the base of p-region 6 and recombining with holes. However, according to previous experiments, even a refresh operation in which electrons are flowed into the p region 6 has a negative effect on the operation of the photoelectric conversion device.

It has been confirmed that the time response is sufficiently fast.

When a photoelectric conversion device is constructed by arranging a large number of optical sensor cells according to the L configuration in the x and Y force directions, the stored voltage Vp in each sensor cell is 0-0.4 in the above example according to the image.
V], but the refresh voltage VII
It can be seen that at 10-'[5eel after H is applied, a constant voltage of about 0.3[V1 remains at the base of all sensor cells, but all changes in the accumulated voltage Vp due to the image disappear. . That is, in the photoelectric conversion device using photosensor cells having the above configuration, there is a complete refresh mode in which the base potential of all sensor cells is brought to zero volts by a refresh operation (in this case, in FIG. 6(a)
), there are two modes: 10 (requiring secl) and a transient refresh mode in which a certain constant voltage remains at the base potential but the fluctuation component due to the accumulated voltage Vp disappears (in this case, as shown in Figure 6). In example (a), 1
0 [μ5ecl ~ lO [5ecl glue 7L/y pulse] 0 In the above example, the voltage V^ applied to the base by the refresh voltage VRH was set to 0.4 [V], but this voltage V^ was set to 0. .8 [V], the above transient refresh mode is 1[n5] according to FIG.
ec] and can be refreshed extremely quickly. The choice of whether to operate in complete refresh mode or transient refresh mode is determined by the purpose of use of the photoelectric conversion device.

If the voltage remaining on the base in this J-transient refresh mode is vt, then in the transient state at the moment when the refresh voltage vl11.4 is returned to zero volts, a negative voltage is added to the base as follows. After the refresh operation by the refresh pulse, the base potential becomes , and the base becomes reverse biased with respect to the emitter.

Feast ψ′4I-σto (1 encouragement 7M f” # a-IJ
I explained that the base is in a reverse bias state in the accumulation state when creating Aka Shit Vote agh, but this refresh operation performs two operations: refreshing and bringing the base to a reverse bias state. This is done at the same time.

! FIG. 1R6 (C) shows experimental values of the change in base potential after the refresh operation with respect to the refresh voltage Vllll+. The value of Cow is set as a parameter from 5 pF to 100 pF. The circles are experimental values, and the solid lines are more calculated values. At this time VK
−0.52V, and Cbc+Cbe=4
There is pF. However, the probe capacitance of 13 pF of the m-measurement oscilloscope is connected in parallel to Cbc+Cbe. In this way, the calculated value and the experimental value are in complete agreement, and the no-fresh operation has been experimentally confirmed. Although an example has been described, it is also possible to carry out the operation with the collector at a positive potential. At this time, the base-collector junction diode Db
Even if c18 is applied with a refresh pulse, if the positive potential applied to the collector is greater than the potential applied to the base by this refresh pulse, it remains non-conducting, so the current flows between the base and c18. It flows only through the emitter junction diode Dbe16. For this reason,
The base potential decreases more slowly, but
Basically, the operation is exactly the same as that described above.

In other words, the relationship between the base potential and the refresh time in FIG. 6(a) is such that the diagonal straight line when the base potential decreases in FIG. 6(a) shifts to the right, that is, in the direction that requires more time. Become.

Therefore, if you use the same refresh Ta EE V ax as when the collector is grounded, it will take time to refresh, but if you slightly increase the refresh voltage vIIH, you can achieve a high-speed refresh operation just like when the collector is grounded. It is possible.

The above is an explanation of the basic operation of the photosensor cell according to the above configuration, which consists of a charge accumulation operation, a readout operation, and a refresh operation by light incidence.

As explained above, the basic structure of the optical sensor cell according to the above configuration is disclosed in the previously mentioned Japanese Patent Application Laid-open No. 58-150878, No. 58-157073, and No. 58-111547.
Compared to 3, it has an extremely MTS structure and can fully support future higher resolutions, and its excellent features such as low noise, high output, wide dynamic range, non-destructive readout, etc. due to the amplification function. It preserves the benefits of

Next, an embodiment of the photoelectric conversion device of the present invention, which is configured by two-dimensionally arranging the optical sensor cells according to the configuration described above, will be described with reference to the drawings.

vinegar.

The basic optical sensor cell 30 surrounded by the dotted line already explained
(This shows that the collector of the bipolar transistor is connected to the substrate and the substrate electrode.), horizontal lines 3131' and 31# for applying read pulses and refresh pulses, and vertical lines 3131' and 31# for generating read pulses. Shift register 32, vertical shift register 3
Buffer M between 2 and horizontal lines 31.31', 31"
O3) Terminal 34 for applying a pulse to the gate of Rangemetal 33.33 33", buffer MOS transistor 35, 35', 35" for applying a refresh pulse, and terminal 34 for applying a pulse to its gate. Terminal 36, terminal 37 for applying refresh pulse, basic optical sensor cell 3
Vertical line 38.38' for reading the stored voltage from 0
, 38'' Horizontal shift register 39 that generates pulses to select each vertical line, MO5) transistor for gates to open and close each vertical line 40° 40', 40
″, an output line 41 for reading out the accumulated voltage to the amplifier section
．． After reading, a MOS transistor 42. is used to refresh the charge added to the output line. MOS transistor 42 terminal 43 for applying a refresh pulse, bipolar for amplifying the output signal, MOS
, FET, J-FET, etc. transistor 44. A load resistor 45, a terminal 46 for connecting the transistor and the power supply,
Transistor output terminal 47, MOS for refreshing the charge accumulated in the vertical lines 40, 40', 40'' during read operation) range meta 48, 48', 4
B'', and MO3I-Randimeta48.48', 4
This photoelectric conversion device is constituted by a terminal 49 for applying a pulse to the gate of 8''.

Regarding the operation of this photoelectric conversion device, FIG. 7 and pf! J
This will be explained using the pulse timing diagram shown in FIG.

In FIG. 8, a section 61 corresponds to a replay, a first operation section 62 corresponds to an accumulation operation, and a section 63 corresponds to a read operation.

At time ti, the substrate potential, that is, the collector potential 64 of the photosensor cell portion is kept at the ground potential or positive potential, and FIG. 8 shows it kept at the ground potential. Regardless of whether it is a ground potential or a positive potential, as already explained, the time required for refreshing differs, and there is no change in the basic operation.
5 is in high state, MOS) range meta 48°4
8', 48N are kept conductive, and each photosensor cell is
It is grounded through the vertical lines 38, 38', 38''.
S) A voltage is applied that makes the transistor conductive, and the buffer MOS transistor 35 for full screen-batch refresh is applied.
．． 35' and 35'' are in a conductive state. When a pulse as shown in waveform 67 is applied to the terminal 37 in this state,
A voltage is applied to the base of each sensor cell through the horizontal lines 31, 31', 31'', and as explained above, a refresh operation is entered, in which the previously accumulated charge is transferred to either a complete refresh mode or a transient refresh mode. Whether the complete replay mode or the transient refresh mode is selected is determined by the pulse loss of the waveform 67.

At time t2, as described above, the base of the transistor of each photosensor cell is reverse biased with respect to the emitter, and the next accumulation period 62 is entered. In this refresh period 61, as shown in the figure, all other applied pulses are kept in a low state.

In the accumulation operation period 62, the substrate voltage, ie, the collector potential waveform 64 of the transistor is set to the IE potential.

As a result, electrons of the electron◆hole pairs generated by light irradiation can quickly flow toward the collector side. However, keeping this collector potential at a positive potential is not an essential condition because the base is biased in the reverse direction with respect to the emitter, that is, at a negative potential, and the ti image is maintained. Even if the potential is changed to a slightly negative potential state, there is no change in the significant 'II product operation.

In the a y1a production state, MOS) Langimeta 48
．． The potential 65 of the gate terminal 49 of 48', 48" is kept high as in the refresh period, and each MOS transistor is kept conductive. Therefore, the emitter of each photosensor cell is connected to the vertical line 38, 38'. , is grounded through 38". When holes are accumulated in the base and saturated, that is, when the base potential becomes biased in the desired direction with respect to the emitter potential (ground potential). , the hole is vertical line 3838',
38'', where the base potential change is stopped and stopped.

Therefore, even if the emitters of photosensor cells adjacent to each other in the vertical direction are commonly connected by the vertical lines 38.38', 38'', the vertical lines 38.38', 38''
If 8'' is grounded, no blooming phenomenon will occur.

To avoid this blooming phenomenon, even if the MOS transistors 48, 48', 48'' are made non-conductive and the vertical lines 38, 38', 38'' are made floating, the substrate potential, that is, the collector potential 64, may be slightly reduced. This can also be achieved by setting the potential to be negative, and when the base potential changes to a positive potential due to accumulation of holes, the potential flows toward the collector side before the emitter.

Following the accumulation section 62, a readout section 63 begins at time t3. At this time t3, 1M0S) Langimeta 48
．． 48', 48'' gate terminal 49 potential 65 is low
Then, the potential 68 of the gate terminals of the bar 2 FAR MOS transistors 33, 33', 33'' of the horizontal lines 31, 31', 31'' is set to high, and the respective MOS transistors are made conductive. However, this gate terminal 34
The timing of setting the potential 68 to high is not necessarily at time t3, but may be any earlier time.

At time t4, among the outputs of the vertical shift register 32, those connected to the horizontal line 31 have a waveform 69 (
Since the MOS transistor 33 is in a conductive state at this time, each of the three photosensor cells connected to the horizontal line 31 is read out. This readout operation is as described above, and the signal voltage generated by the signal charge accumulated in the base region of each photosensor cell is directly transferred to the vertical line 38.38'38''
appears in At this time, the pulse width of the pulse voltage from the vertical shift register 32 is as shown in FIG.
The read voltage for one voltage is set to a pulse width that maintains linearity by f·min. Further, as explained above, the pulse voltage is adjusted so that a forward bias is applied to the emitter by v@ias.

Next, at time t, among the outputs of the horizontal shift register 39, only the output to the gate of the MoS transistor 40 connected to the vertical line 38 has a waveform 70 (
becomes high, the range metal 40 becomes conductive, and the output signal passes through the output line 41 and enters the output transistor 44, where the current is amplified and output from the output terminal 47. After the signal is read out in this way, the output line 4
1, there remains signal charge due to wiring capacitance.

At time M t a, a pulse is applied to the gate terminal 43 of the MOS transistor 42 as shown in the pulse waveform 71,
Mo5) Make the range metal 42 conductive and connect the output line 4.
1 is grounded to refresh this remaining signal charge. Similarly, the switching MO
The S transistors 40', 40'' are made conductive in sequence to read out the signal outputs of the vertical lines 38', 38''. After reading out the signals from each horizontally arranged line of photosensor cells in this way, the tumor line 38.38'38'' receives a signal due to its wiring capacitance, similar to the output line 41.
Since the load remains, each vertical line 38.38', 3
MOS transistor 48.48' connected to 8'', 4
8. '' is made high and conductive at its gate terminal 49 as shown by a waveform 65 to refresh this residual signal charge.

Then, at time t, the vertical shift register 32
Among the outputs, the output connected to the horizontal line 31' becomes waveform 69' (high), and the accumulated voltage of each party sensor cell connected to the horizontal line 31' becomes 38, 38', 38"' on each vertical line. Thereafter, the @ sign is read out from the output terminal 47 by the same operation as before.

In the above explanation, the am section 62 and the read section 63
We have explained the operating conditions applied to application fields where L4 is clearly classified, for example, still video, which is currently being actively researched and developed. The present invention can also be applied to fields of application where operations in section 63 are performed simultaneously by changing the pulse timing shown in FIG. However, the refresh at this time is not a full-screen refresh, but requires a line-by-line refresh function.For example, after the signals of each photosensor cell connected to the horizontal line 3i are read, at time 1. In order to erase the charge remaining on each vertical line, the MOS transistors 48 and 48'48'' are made conductive, and at this time a refresh pulse is applied to the horizontal line 31. That is, in the waveform 69, even at time tl, the time IAt 4
Similar to pulsed voltage. This can be achieved by using a vertical shift register configured to generate pulses of different pulse widths. In this way, in addition to double-pulse operation, instead of the device that applies a batch refresh pulse installed on the right side of Figure 7, a second vertical shift register similar to the one on the left side is installed on the right side, and the timing is changed to the left side. This can also be achieved by operating with offset from the vertical register provided.

In this case, in the IIm condition as already explained,
The degree of freedom in controlling blooming by controlling the potentials of the emitter and collector of each photosensor cell is reduced. However, as explained in the basic operation section, in the read state, the configuration is such that high-speed reading can only be performed when a bias voltage V ei as is applied to the base, so as can be seen from the graph in Figure 3. , Vmi
Due to the saturation of each photosensor cell when as is not applied,
The signal type load flowing into the vertical (α lines 28, 28', 28'') is extremely small, and the blooming phenomenon is not a problem at all.

゛Also, the photoelectric conversion device according to this embodiment can obtain extremely excellent characteristics with respect to the double smear phenomenon. The smear phenomenon is an operational and structural problem that occurs in CCO5 imaging devices, especially frame transfer type, in which charge is transferred to the area irradiated with light. This problem occurs because carriers generated deep in the semiconductor due to light are accumulated in the charge transfer section.

Furthermore, in the MO3 type imaging device, this problem arises because carriers generated deep in the semiconductor due to long wavelength light are accumulated on the drain side of the switching MO3) transistor grounded to each photosensor cell.

On the other hand, in the photoelectric conversion device according to this embodiment, there is no smear phenomenon that occurs due to its operation and structure, and the phenomenon that carriers generated deep in the semiconductor are accumulated by Ia due to long wavelength light does not occur at all. However, there is a concern that electrons are accumulated among the electrons and holes generated relatively near the surface of the emitter of the photosensor cell. Since the electrode is grounded, electrons are not accumulated and no smear phenomenon occurs.Also, during the line refresh operation applied in ordinary television cameras, the 11WMk voltage is applied to the vertical line during the horizontal blanking period. Before reading, the vertical line is grounded and refreshed, so at the same time, the electrons accumulated in the emitter during one horizontal scanning period flow out, so the Sumi 7 phenomenon hardly occurs. In the photoelectric conversion device according to this embodiment, the smear phenomenon occurs only to an essentially negligible extent due to its structure and operation, which is one of the major advantages of the photoelectric conversion device according to this embodiment.

Further, although the operation of suppressing the blooming phenomenon by manipulating the emitter and collector potentials in the storage operation state has been described above, it is also possible to use this to control the γ characteristics.

φ In other words, during the storage operation, the potential of the emitter or collector is temporarily set to a certain negative potential, and of the carriers accumulated in the base, more carriers are accumulated than the number of carriers that give this negative potential. This causes holes to flow toward the emitter or collector. As a result, the relationship between the accumulated voltage and the amount of incident light shows the characteristic of γ = 1 of silicon crystal when the amount of incident light is small, and shows the characteristic that γ becomes smaller than 1 when the amount of incident light is large. , it is possible to provide the characteristics of γ-0.45 normally required for television cameras using a polygonal approximation. If the above operation is performed once in the middle of the storage operation, it becomes a one-fold line approximation, and if the negative potential applied to the emitter or collector is changed twice as appropriate, it is also possible to have a 5-bifold line type γ characteristic.

In one or more of the embodiments, the silicon substrate is used as a common collector, but a structure may also be used in which an n+ region is provided and the collector is divided for each line, as in a normal bipolar I transistor.

In addition to the pulse timing shown in FIG. 8, the actual operation requires the vertical shift register 32 and the horizontal shift register 3.
A clock pulse is required to drive 9.

FIG. 9 shows an equivalent circuit related to the output signal.

The capacitance Cma80 is the wiring capacitance of the vertical line 38.38'38'', and the v quantity C181 is the wiring capacitance of the output line 41.The equivalent circuit on the right side of FIG.
This is in the read state, and the switching MOS
) Rangemetal 40. 40', 40'' are in a conductive state,
Its resistance value in the conductive state is indicated by resistor RM82. Further, the amplification transistor 44 is shown as an equivalent circuit using a resistor r, 83 and a current source 84. The MOS range metal 42 for refreshing the charge accumulation caused by the wiring capacitance of the output line 41 is non-conductive in the read state and has high impedance, so it is omitted in the equivalent circuit on the right side.

Each parameter of the equivalent circuit is determined by the size of the photoelectric conversion device actually constructed. For example, the capacitance C 80 is about 4 pF, and the capacitance C 81 is about 4 pF.
The conductive state resistance R182 of the transistor (MOS) is 3
about Ω, the current amplification factor β of the bipolar transistor 44
An example in which the output signal waveform observed at the output terminal 47 is calculated is shown in FIG.

In Fig. 10, the horizontal axis represents the time from the moment when the switching MOS) range metals 40, 40', 40'' become conductive!
gsl, the vertical axis is a vertical line 38° 38', 38'' wiring capacitance Cma 80, output terminal 4 when signal charges are read out from each party sensor cell and a voltage of 1 volt is applied.
The output voltage (Vl) appearing at 7 is shown, respectively.

The output signal waveform 85 is the load resistance R, 45 is IOKΩ, 86
The load resistance R745 is 5Ω, and the load resistance R545 is 87Ω.
is 2Ω, and in both cases the peak value is 0.5 due to the capacitance division of Cma80 and Ct+81.
It is set to vfillf. Naturally, the larger the load resistance R1145 is, the smaller the attenuation amount is, resulting in a desirable output waveform.

The rise time is approximately 20 n for the above parameter values.
It is fast at 5ec. Even higher-speed reading is possible by reducing the resistance RM in the conductive state of the switching MOS transistors 40, 40', 40'' and by reducing the wiring capacitances C and CH.

In the photoelectric conversion device using the photosensor cells with the above configuration, the voltage appearing at the output is large due to the amplification atS of each photosensor cell, so the final stage amplification amplifier is also MOS
It is quite simple compared to a type imaging device. In the case of Crime E, an example using a one-stage bipolar transistor type was explained, but it is of course possible to use other systems such as a two-stage structure. When bipolar transistors are used as in this example, the problem of l/ffi noise that is noticeable on images generated from the MOS transistor of the final stage amplifier in a COD imaging device can be solved.
It does not occur in the photoelectric conversion device on the Kinio side, and the S/N is extremely low.
It is possible to obtain image quality with good ratio.

As mentioned above, in the photoelectric conversion device using the photosensor cell according to the above JMffl, the amplification amplifier in the final stage can be extremely simple, so the configuration shown in FIG. 7 in which only one amplification amplifier in the final stage is provided Instead of the type shown in the embodiment shown, it is also possible to install a plurality of amplification amplifiers so that one screen can be divided into a plurality of parts and read out.

FIG. 11 shows an example of a divided readout system. The embodiment shown in FIG.
This is an example of installing one. The basic operation is almost the same as that described using the embodiment of FIG. 7 and the timing diagram of FIG. 8.

In the embodiment shown in FIG. eye.

At the 0th-order point in time, when the outputs of the sensor cells connected to the (2n+1)th column (n is an integer and the number of pixels in the horizontal direction is 3n in this example) are read out simultaneously, 2 Column ft, (n+2)th column. The (2n+2)th column will be read.

According to this embodiment, when the time to read out - horizontal lines is fixed, the horizontal scanning frequency is 1/3 compared to the system with one final stage amplifier.
, the horizontal shift register is easy to use,
And photoelectric transformation 11! ! A high-speed analog-to-digital converter is not necessary for applications in which the output signal from the device is converted into analog-to-digital data for signal processing, which is a major advantage of the divided readout method.

In the embodiment shown in FIG. 11, three equivalent horizontal shift registers are provided, but the same function can be provided with only one horizontal register. An example in this case is shown in FIG.

The embodiment shown in FIG. 12 differs from the embodiment shown in FIG. 11 in that only the horizontal switching MOS (MOS) run sister and the intermediate part of the final stage amplifier are provided, and the other parts are
Since it is the same as the embodiment shown in FIG. 11, it is omitted.

In this embodiment, the output from one horizontal shift register 104 is divided into the 1st column, (n+1) column, (2n+1)
) is connected to the gate of the switching MOS transistor in column 0 so that those lines can be read out simultaneously.
At the next point in time, the second column, (n+2) column, (2n+2)
The column is read out.

According to this embodiment, although the number of wirings to the gates of each switching MO3) run sister increases, it is possible to operate with only one horizontal shift register.

In the examples shown in FIGS. 11 and 12, three output amplifiers are provided, but it goes without saying that this number may be increased depending on the purpose.

! In both the embodiments shown in FIGS. 1811 and 12, the starting pulse and clock pulse for the horizontal shift register and vertical shift register are omitted, but like other refresh pulses, they are provided within the same chip. It can be supplied from a clock pulse generator, a clock pulse generator, or another on-chip clock pulse generator.

In this split readout method, horizontal lines - all or the entire screen -
When performing a bulk refresh, there is a slight difference in storage time between the n-th and (nil)-th row photosensor cells, which causes a slight discontinuity in the 4B & current component and signal component, which can be seen on the image. Although there is a possibility that this may occur, it is very small and poses no problem in practice.Also, even if this exceeds the allowable limit, it is difficult to correct it using an external circuit. This can be easily accomplished by using conventional correction techniques of generating a wave, subtracting it from the dark current component, and multiplying and dividing it by the signal component.

When capturing a color image using such a photoelectric conversion device, a 5-stripe filter or a mosaic filter is placed on-chip on top of the photoelectric conversion device, or a separately made color filter is pasted on top of the photoelectric conversion device. It is possible to obtain color signals.

As an example, when R, G, and B stripe filters are used, in a photoelectric conversion device using the photosensor cell according to the above configuration, the R signal,
It is possible to obtain G@ signal and B signal. An example of this is shown in FIG. 13, which, like FIG. 12,
Only the area around the horizontal register is shown. The rest is the same as Figures 7 and 11, except that the first row is the R color filter, the second row is the G color filter, the third row is the B color filter, and the fourth row is the R color filter. It is assumed that a color filter is attached, such as a filter. As shown in Figure 13, the 1st row, 4th row, 7th row ---
--- each vertical line is connected to an output line 110;
This takes out the R signal, and also the 2nd, 5th, and 8th columns.
---- Each prefectural road line is connected to the output line 111, which takes out the G signal, and similarly, the third row 6
Each vertical line in the 9th and 9th columns is connected to an output line 112 to take out the B signal, an output line 110
, 111, and 112 are connected to an on-chip refresh MOS transistor and a final stage amplifier, for example, an emitter follower type bipolar transistor, and each color signal is output separately.

Photoelectric transformer # according to another embodiment of the present invention! A diagram for explaining the basic structure and operation of another example of the optical sensor cell constituting the device is shown in FIG. 14, and its equivalent circuit and overall circuit configuration diagram are shown in FIG. 15(a).

The optical sensor cell shown in FIG. 14 is an optical sensor cell that can simultaneously perform a read operation and a line refresh 1/-/sh using the same horizontal scan pulse.

The difference in FIG. 14 from the configuration in which w4 has already been shown in the diagram is that in FIG. A MOS capacitor electrode 120 is also connected to the sensor cell side, and when viewed from one optical sensor cell, it is a double capacitor type, and the emitter 7 of the vertically adjacent optical sensor cell in the figure
．． 7' is wiring ■8 and wiring ■12, which are two-layer wiring.
1 (In Figure 14, the vertical line appears to be one, but
(2 lines are arranged through an insulating layer), that is, the emitter 7 is connected to the wiring 8 through the contact hole 19, and the emitter 7' is connected to the wiring 1 through the contact hole 1.
The difference is that they are respectively connected to the wiring 121 through 9'.

This becomes clearer when looking at the equivalent circuit shown in FIG. 15(a). That is, the MOS capacitor 150 connected to the base of the photosensor cell 152 is connected to the horizontal line 31, and the MOS capacitor 151 is connected to the horizontal line 31'. In addition, in the diagram of the optical sensor cell 152, the MOS capacitor 15 of the optical sensor cell 152' adjacent to the bottom
0' is connected to a common horizontal line 31'.

The emitter of the photosensor cell 152 is placed on the vertical line 38, the emitter of the photosensor cell 152 is placed on the vertical line 13B,
The emitters of the photosensor cells 152 are connected alternately in vertical lines 38.In the equivalent circuit of FIG. The difference is that
A switching MO3) switching MO3) for refreshing the vertical line 138 in addition to the switching MO3) range meta 48 for refreshing the vertical line 38, and a switching MOS transistor 40 for selecting the vertical line 138 Switching MO3) range meta 140 to select line 138
has been increased, and one output amplifier system has been added.

The configuration of this output system includes switching MO3) range meta 48 and 148 for refreshing each line.
It is also possible to use a configuration in which the output amplifiers are connected to each other, and further to use only one output amplifier as shown in FIG. 15(b) using horizontal scanning sweeping and switching MOS transistors. Figure 15('b) shows that Figure 15(a)
) only the vertical line selection and output amplifier system parts are shown.

According to the optical sensor cell shown in FIG. 14 and the embodiment shown in FIG. 15(a), the following operations are possible. That is, when the readout operation of each optical sensor cell connected to all the horizontal lines 31 is completed and the horizontal blanking period in the 2-TV operation is in progress, when the output pulse from the vertical shift register 32 is output to the horizontal line 31', the MOS Through the capacitor 151, the optical sensor cell 15 that has been read out
Refresh 2. At this time, the switching MOS
Transistor 48 is rendered conductive and vertical line 38 is grounded.

Also, a MOS capacitor 1 connected to the horizontal line 31'
The output of photosensor cell 152' is read out to vertical line 138 through 50'. At this time, naturally, the switching MO3) range metal 148 is rendered non-conductive, and the vertical line 138 is in a floating state. In this way, one vertical scan pulse refreshes the photosensor cells that have already finished reading.
It is possible to read out the photosensor cells of the next line simultaneously with the same pulse. At this time, as already explained, the voltage for refreshing and the voltage for reading differ because a bias voltage is applied during reading due to the necessity of high-speed reading. They are distantly related by changing the area of the electrode 9 and the MOS capacitor electrode 120 so that even if the same voltage is applied to each electrode, different voltages are applied to the base of each sensor cell.

In other words, the area of the refresh MOS capacitor is
The area is smaller than that of the read MOS capacitor. As in this example, if you do not refresh all the sensor cells at once but refresh each line one by one, pF4 should be configured with an n-type collector or a substrate of this type, as shown in Figure (b). However, it may be desirable to provide separate collectors for each horizontal line. When the collector is a substrate, the collectors of all the photosensor cells are a common area, so that a constant bias voltage is applied to the collectors in the storage and light reception/readout states. Of course, as already explained, floating base refresh can be performed between the emitters even with a bias voltage applied to the collector. However, in this case, at the same time as the base region is refreshed, a wasteful current flows between the emitter and collector of the cell to which the refresh pulse is applied, increasing power consumption. In order to overcome this problem, the collectors of all the sensor cells are not made into a common area, but the collectors of the sensor cells arranged in each horizontal line are made common, but the collectors of each horizontal line are structured to be separated from each other. That is, to explain this in relation to the structure shown in Fig. 2, the substrate is of a p-type, and collectors are separated from each other for each horizontal line in the p-type substrate.
? Create a structure with a 4-inclusive area. The N buried regions of adjacent horizontal lines may be separated by a structure in which a p region is interposed between them.Insulator isolation is better for reducing the collector capacitor buried along the horizontal lines. . In Figure 1, since the collector is composed of a substrate,
The isolation regions surrounding the sensor cells are all provided to approximately the same depth. On the other hand, in order to separate the collectors of each horizontal line from each other, the separation area in the horizontal line direction is made deeper than the separation area in the vertical line direction by a necessary value.

If the collector is separated for each horizontal line, if the voltage of the collector of that horizontal line is grounded when reading is finished and the refresh operation starts, the emitter-collector current as described above will not flow, and the power consumption will be reduced. When the refresh operation that does not result in an increase in charge is completed and a charge storage operation based on an optical signal is started, a predetermined bias voltage is again applied to the collector region.

Further, according to the equivalent circuit shown in FIG. 15(a), the outputs are outputted to the output terminals 47 and 147 in an intersection 114 for each horizontal line. As already explained, it is also possible to take out the output from one amplifier by using a configuration as shown in FIG. 15(b).

As explained above, according to this embodiment, line refreshing is possible with a relatively simple configuration, and it can also be applied to fields of application such as ordinary television cameras.

Other embodiments of the present invention include a structure in which a photosensor cell is provided with a plurality of emitters, or a structure in which a single emitter is provided with a plurality of contacts.

A type that takes out multiple outputs from one optical sensor cell is considered.

This is because each sensor cell of the photoelectric conversion device according to the present invention has an amplification function, so in order to extract a plurality of outputs from one photosensor cell, 1. This is due to the fact that even if a plurality of wiring capacitances are connected to each photosensor cell, the accumulated voltage Vp generated inside the photosensor cell can be read out to each output without being attenuated at all.

In this way, by having a configuration in which multiple outputs can be taken out from each optical sensor cell, many advantages can be added to the photoelectric conversion device formed by arranging a large number of each optical sensor cell in terms of signal processing, noise countermeasures, etc. is possible.

Next, an example of a method for manufacturing a photoelectric conversion device according to the present invention will be described. Figure 16 shows selective epitaxial growth (N,
E+do at, Novel device 1
Solation technology! ogy with 5
selected epitaxial growth”
〒ech, old g, of 11a821 E D M
, PP, 24! An example of the manufacturing method using (see 244) is shown below.

An n+ region 1 for contact is formed on the back side of an n-type Si substrate 1 with an impurity concentration of about 1 to 10×10” cm−3.
1 by diffusion of As or P. Although not shown in FIG. 2, an oxide film and a nitride film are usually provided on the back surface to prevent autodoping of the n+ region and the like.

The substrate 1 used has impurity concentration and oxygen concentration controlled to be uniform. That is, a crystal wafer having a sufficiently long and uniform carrier line time is used. For example, a crystal produced by the MCZ method is suitable as such a material. An oxide film of about Ig1 is formed on the surface of the substrate 1 by weight oxidation. That is, H, O atmosphere or (H.

+Of) Oxidizes in the atmosphere. In order to obtain a good oxide film without causing defects in the FA layer, high-pressure oxidation at a temperature of about 900° C. is suitable.

On top of that 1. For example, 810 with a thickness of about 2 to 4 mm,
Deposit the film by CVD* (Nt + SiH4+
02) In a gas system, deposit a desired thickness of Sin at a temperature of about 300 to 500°C.The molar ratio of Ot/SiH4 is set to about 4 to 40, although it depends on the temperature. Through the photolithography process, the oxide film in the other areas is left behind (C layer 4
+ layer 2), c, F@, CH,F.

For example, IOX10 is removed by reactive ion etching using a gas such as (step (a) in FIG. 16).
When one pixel is provided in Bm2, the width of the e5iOt film that leaves the S+02 film in a mesh shape with an io#L-pitch is selected to be, for example, about 2 tsubo-. The damaged layer and contaminant layer on the surface due to reactive ion etching are
/CI, after removal by gas-based plasma etching or wet etching, a) evaporation in a high vacuum or sputtering with a sufficiently clean atmosphere in a load-lock format, or 5i) GO in l4 gas,
Depositing amorphous silicon 301 using reduced pressure CvD using laser beam irradiation (step (b) in FIG. 16);
By anisotropic etching using a gas such as CB r layer 3, CC1xFt, ci, or active ion etching, amorphous silicon other than those deposited on the side surfaces of S+I) and 9 is removed (step (C) in FIG. 16). )). As before, after sufficiently removing the damage and contamination layer, the silicon substrate surface is thoroughly cleaned, and (n, +
(SiH2, C exchange, +HC) Selective growth of the silicon layer is performed using a gas system, r & length is performed under a reduced pressure of several 107 or'r, the substrate temperature is 800 to 1000 °C, and the molar ratio of Hl is set to a higher value than a certain level. Set. If the amount of HC cross-over is too small, selective growth will not occur. A silicon crystal layer grows on the silicon substrate, but the silicon on the Si02 scraps is etched away by If and Q.
No silicon is deposited on the 5i02 layer (Fig. 16(d)
)) The thickness of the n-layer 5 is, for example, about 3 to 5 squares.

The impurity concentration is preferably between 101'' and 10''am-'
Set to a certain degree. Of course, it is possible to deviate from this range, but if the pn junction is completely depleted at the diffusion potential or an operating voltage is applied to the collector, at least n
``It is desirable to select an impurity concentration and thickness such that the region is completely depleted.

Since the commonly available I'IC gas contains a large amount of water, an oxide film is constantly formed on the silicon substrate surface, making it impossible to expect high-quality epitaxial growth. A large amount of HCl reacts with the material of the cylinder while it is in the cylinder and contains a large amount of heavy metals, mainly iron, and is used in optical sensor cells that tend to become contaminated with heavy metals. The shrimp layer is 2
Since it is desirable that the dark current component be as small as possible, it is necessary to suppress contamination by heavy metals to the utmost. 5iJC1,
Of course, we use ultra-high purity materials, but
) For lCfL, one with particularly low moisture content, preferably at least 0.5 ppm or less of moisture content, is used. Of course, the lower the water content, the better.

In order to further improve the quality of the epitaxially grown layer, the layer plate is first treated at a high temperature of about 1,150 to 1,250 degrees Celsius to remove oxygen from near the surface, and then subjected to a long-term heat treatment at about 800 degrees Celsius, which generates many micro-defects inside the substrate. It is also extremely effective to use a substrate that has a denuded zone and is capable of indolithic gettering.Since the epitaxial growth is performed in the presence of the 5i02 layer 4 as the 0 isolation region, the 5i
In order to reduce the incorporation of Iv elements from 02, the lower the growth temperature is, the better. In the commonly used high-frequency heating method, there is a lot of contamination from the carbon susceptor, and it is difficult to lower the temperature further. The wafer direct heating method using lamp heating without using a susceptor provides the cleanest growth atmosphere and allows high-quality shrimp layers to grow at low temperatures.

For supporting the wafer in the reaction chamber, ultra-high purity fused sapphire, which has a lower atmospheric pressure, is suitable. Thermal strike 1 makes it easy to preheat the raw material gas and even out the temperature within the wafer surface even when the gas in a large flow field is undulating.
The wafer direct heating method using lamp heating, which generates almost no gas, is suitable for obtaining high-quality shrimp layers. UV irradiation on the wafer surface during growth further improves the quality of the shrimp layer.

Amorphous silicon is deposited on the sidewalls of the Sin layer that will become the isolation region 4 (step (C) in Figure 16).
The crystal near the interface with the i02 isolation region 4 becomes very good. After forming the high resistance n-layer 5 by selective epitaxial growth (step (d) in FIG. 16), the surface concentration l
A P region 6 of approximately 20×10″C1′ is formed to a predetermined depth by diffusion from doped oxide or by diffusion using a low-dose ion-implanted layer as a source.

The depth of the p-region 6 is, for example, approximately o, e-tg.

The thickness and impurity concentration of p region 6 are determined based on the following considerations. In order to increase the sensitivity, it is desirable to lower the impurity concentration in the p region 6 to reduce Cbe.Cbe is approximately given as follows.

Cbe = Aee ("NA", ) 2eVb+ where Vbi is the emitter-base diffusion potential and is given by: Here, (is Anl of silicon crystal, N
C1 is the impurity concentration of the emitter, NA is the impurity density of the portion of the base adjacent to the emitter, and n= is the intrinsic carrier concentration. The smaller the NA, the smaller the Cbe, and the higher the sensitivity, but if the NA is made too small, the base region will be completely depleted in the operating width, resulting in a punch-through state, so it cannot be made too low. It is set to such an extent that the base region is not completely depleted and a punch-through state occurs.

Thereafter, a thermal oxide film 3 having a thickness of several tens of amperes to several hundred eights is formed on the surface of the silicon substrate by (H2+o2) gas-based steam oxidation at a temperature of approximately 800 to 900°C. On top of that, nitriding with CvD of (SiHa + NJ) type gas (S is NA) 302 to 500
It is formed to a thickness of about 1500 A. Formation temperature is 70
The temperature is about 0 to 800°C. NH, gas, etc.) Products that are normally available along with gas contain a large amount of water. If NH or gas with a high moisture content is used as a raw material, it will result in a nitride film with a high oxygen concentration, resulting in poor reproducibility.
The subsequent selective etching with the SiO□ film results in an inability to obtain a selectivity.

The NH3 gas should also have a water content of at least 0.5 ppm or less. It goes without saying that the lower the moisture content, the more desirable it is.
00 is deposited by CVD. For example, gas systems are
Using (N, + 5i) + 4+ O, +PH,),
2000-3000A at a temperature of about 300-450℃
Deposit pscs with a thickness of about
rA step (e)), As-doped polysilicon 5304 is deposited on the n'' region 7 and on the refresh and read pulse application electrodes by a photolithography process including two mask alignment steps. In this case, p A doped polysilicon film may be used, for example, by two photophosphorography steps, the ps
All of the c6°Si3N4M, 5ift film was removed, and the underlying 5iO1 film was left in the areas where the refresh and read pulse application electrodes were to be provided.
s and Si3 N 4 f! '! Etching only. After that, As-doped polysilicon was made of (N2 +SiH
4+Ad 3 ) or (N2 + 5tH4+
The film is deposited by CVD using AsH3) gas. Deposition temperature is about 550℃~700℃, film thickness is 1000~200O
It is A. Non-doped polysilicon is made by CVD method.
After that, the polysilicon film in other parts except for the emitter and the refresh and read pulse applying electrodes, which may be diffused with As or P, is removed by etching after a mask alignment photolithography process. Furthermore, when PSGg is etched, the polysilicon deposited on the PSG film is removed in a self-aligned manner due to lift-off (step (f) in FIG. 16).
Etching of polysilicon film is CB C1! Fa,
(CB t F, +c It ), etc., and the Si3N''4 film is etched with CH.

F? Etching with gas such as

Next, after PSGllQ305 is deposited by the gas-based CVD method as described above, a contact hole is formed in the polysilicon film for the refresh pulse and read pulse electrodes by a mask alignment process and an etching process. Under these conditions, AI, AI-Sr, AM
-Cu -Si and other metals are deposited by vacuum evaporation or sputtering. Multiply or (CH3) s
Plasma CVD using AM or AfLCI as raw material gas
method, or also the above raw material gas bond - C bond or A
Light irradiation CV that cuts Sen-C1 bond by direct light irradiation
AfL is deposited by method D. (C) [ko) 3A
CV as above using Miya Ai c+ as raw material gas
When performing method D, hydrogen is allowed to flow in large quantities in order to deposit pattern A into a narrow and steep contact hole.
3 in a clean atmosphere with no moisture or oxygen contamination.
A CVD method in which the substrate temperature is raised to a film thickness of 00 to 400°C is superior. After completing the patterning of the metal wiring 10 shown in FIG. 1, a living room insulating film 306 is deposited by the CVD method.

306 is the above-mentioned PSG film or CVD method Si
02 film or when it is necessary to take water resistance into consideration, it is Si384 N formed by a (SiH4+NJ) gas-based plasma CVD method. Sil N
4 ft5 [In order to keep the hydrogen content low,
(Si)+4+N2) plasma CVD in gas system
use the law.

Si3N4 is formed by plasma CVD to increase the electrical breakdown voltage and reduce leakage current.
The membrane is excellent. There are two types of photo-CVD methods. (SiH4+NH3+8g) A method of externally irradiating 2537A ultraviolet rays from a mercury lamp in a gas system, and (S
This is a method of irradiating the 3-gas system with ultraviolet light from a mercury lamp. In both cases, the substrate temperature is 15
The temperature is about 0 to 350°C.

Through the mask alignment process and etching process, an insulator 1151305.3Of3 is formed on the polysilicon on the emitter 7.
After forming a contact hole through reactive ion etching, Ai is etched using the method described above. An-S i,A
A metal such as Cu-9i is deposited. In this case, since the contact hole has a large 7 spectral ratio, deposition by CVD is superior. After finishing the patterning of the metal wiring 8 in Fig. 1, CV
Land area is determined using the D method (Figure 16 (g)).

In this case as well, the film produced by the two-light CVD method is superior. 12
is a metal electrode made of AI, Al-5r, etc. on the back surface.

The method for manufacturing the photoelectric conversion device of the present invention involves a wide variety of steps, and FIG. 16 shows only one example.

An important point of the photoelectric conversion device of the present invention is how to suppress leakage current between p region 6 and n- region 5 and between p region 6 and n+ region 7 to a minimum.

In addition to improving the quality of the n''' region 5 and reducing dark current, the isolation region 4 made of an oxide film, etc.
It is the interface between the n-region 5 and the n-region 5 that is the problem. In Figure 16,
For this purpose, a method has been described in which amorphous Si is deposited on the side wall of the separation region 4 in advance and growth is performed. In this case, amorphous Si is made into a single crystal by solid phase growth from the Si substrate during growth. Shrimp growth occurs at a relatively high temperature of about 8,500 to 1,000°C. Therefore, before amorphous Si is made into a single crystal by solid phase growth from X-plate Si, 5
In many cases, microcrystals begin to grow during the process, which causes poor crystallinity. At lower temperatures, the rate of solid phase growth is relatively much higher than the rate at which microcrystals begin to elongate in amorphous Si. 5. If amorphous Si is made into a single crystal, the characteristics of the interface will be improved. At this time, the substrate Si and the amorphous Si
If there is a layer such as an oxide film between the two grooves, the start of solid phase growth will be delayed, so an ultra-high cleanliness process is required to prevent such a layer from being present at the boundary between the two grooves.

In addition to the above-mentioned furnace growth, solid phase growth of amorphous Si is performed by heating the substrate with a flash lamp or infrared lamp while keeping the substrate at a certain temperature. For example, a rapid annealing technique for several seconds to several tens of seconds is also effective. When using such technology, the Si deposited on the sidewalls of the layer may be polycrystalline, but it is deposited using a very clean process and does not contain oxygen, carbon, etc. at the grain boundaries of the polycrystalline material. It is necessary to set it to Si.

After the Si on the SiO2 side is single crystallized, the Si
This will result in selective growth.

If leakage current at the interface between the SiO2 am region 4 and the high-resistance n-region 5 becomes a problem, increase the n-type impurity concentration only in the portions of the high-resistance n'' region 5 adjacent to the Sin and isolation regions 4. For example, only a region of about 0.3 to IILs thickness of the n- region 5 that contacts the separated!9i0.region 4, for example, 5 to IOX 10" Cl- The n-type impurity concentration is increased to 38 degrees. This structure can be formed relatively easily. After forming a thermal oxidation film of approximately 1-1 on the substrate 1, a 5ift full film is first made into a S+02 film containing a predetermined amount of P to a required thickness by SUa using the CVD method. Furthermore, 1ti of 5102 was added on top of that by CVD method.
The isolation region 4 is created by ffl, and in the subsequent high-temperature process, phosphorus is diffused into the high resistance n-region 5 from the phosphorus-containing 5iOy M present in a sandwich form in the isolation region 4. Creates a good impurity distribution with the highest impurity concentration at the interface.

That is, the isolation region 4, which is configured as shown in FIG. 17, is configured in a three-layer structure.
5t (l ff film, 301 is a CVD SiO2 film. Adjacent to the separation region 4, between the inside of the n-region S,
An n region 307 is formed by diffusion from the SiO2 film 309 containing phosphorus. 307 is formed all around the cell. With this structure, the base-collector capacitance Cbc
Although it gets bigger.

Leak between base and collector? TI style will be drastically reduced.

In FIG. 16, an example has been described in which the isolation insulating region 4 is formed in advance and selective epitaxial growth is performed. U-group isolation technology (A, H
a2asakaet al, “U-groove
1solation technique forh
igh 5peed bipolar VLSI'S
” ,↑ech, Dig, ofIEDM, P, f
l2.1982. This can also be done using (see).

A photoelectric conversion device according to the present invention forms a bipolar transistor in which a base region, most of which is adjacent to the semiconductor wafer surface, is in a floating state in a region surrounded by an isolation region made of an insulator. , the potential of the floating base region is provided to a part of the base region through a thin insulating layer 1! By controlling the poles,
This is a device that converts optical information photoelectrically. An emitter region made of a high impurity concentration region is provided in a part of the base region, and the emitter region is controlled by a MOS transistor operated by a horizontal scan pulse. As mentioned above. An electrode provided on a portion of the floating base region via a thin insulating layer is connected to a horizontal line. The collector provided inside the wafer may be composed of a substrate, or depending on the purpose, it may be composed of high-concentration impurity physical regions separated for each horizontal line on a high-resistance substrate of the opposite conductivity type. . Compared to the pulse voltage when refreshing the floating base region with the electrode provided through the insulating layer, the pulse voltage applied when reading out the signal is substantially larger, in fact, it has a voltage of 2M class. By applying a refresh pulse, a pulse train may be used, or as explained in the double capacitor structure, the capacitance CO of the readout MOS capacitor electrode may be made larger than the capacitance Cot of the refresh MOS capacitor electrode. , store a signal based on an optical signal by accumulating optically excited carriers in a floating base region that is in a reverse biased state,
When reading out the signal, a reading pulse voltage is applied so that the base-emitter is deeply biased in the forward direction, so that the signal can be read out at high speed. As long as it has these characteristics, the photoelectric conversion device of the present invention may be realized in any structure, and it is needless to say that it is not limited to the structure described in the above embodiments.

For example, the structure is similar even if the conductivity type is completely reversed from that described in the above embodiment. however,
At this time, it is necessary to completely reverse the polarity of the applied voltage. :4 In a structure in which the electric type is completely reversed, the region becomes n-type. That is, the impurities constituting the base are As and P. When the surface of the region containing AseP is oxidized, AseP
P is Si/Sin.

Pile up on the Si side of the interface. That is, a strong drift electric field is generated inside the 5-base from the surface to the inside, and the photo-excited holes immediately escape from the base to the collector side, and electrons are efficiently accumulated in the base.

If the base is p-type, the commonly used impurity is poron. When the p-region surface containing poron is thermally oxidized, poron is incorporated into the oxide film, so Si/SiOz
The poron concentration in the Si near the interface is slightly lower than the poron concentration inside. Although this depth depends on the oxide film thickness, it is usually several hundred eights. A reverse drift electric field for electrons is generated near this interface, and electrons photoexcited in this region tend to be collected on the surface.

If this continues, the region where this reverse drift electric field occurs will become an insensitive region, but in the photoelectric conversion device of the present invention, there is an n+ region along a part of the surface, so the S region of the P region is present.
The electrons gathered at the i/5iOz interface, this n+
It flows into the region before being recombined, so even if there is a region where poron is reduced near the Si/5i02 interface and a reverse drift electric field occurs, it will hardly become a dead region. , rather, these regions are S i
/S i02 interface, the accumulated holes are
Since i/Sin is pulled from the interface and exists inside, the effect of holes disappearing at the interface is eliminated, and the hole accumulation effect at the base of the p layer is improved.
Highly desirable.

As described above, the photoelectric conversion device of the present invention accumulates carriers excited by light in the base region, which is the control electrode region in a floating state. That is, Ba5e 5tore ImageSenso
It is a device to be called r, and is abbreviated as BAS[S.

Since the photoelectric conversion device of the present invention can configure an L pixel with one transistor, it is extremely easy to increase the density, and at the same time, due to its structure, it has less blooming and smearing, has high sensitivity, and has a wide dynamic range. Since it has an internal amplification function, it generates a large signal voltage regardless of the wiring capacitance, so it has the characteristics of low noise and easy peripheral circuitry. The value is extremely high.

In addition to the above-mentioned solid-state imaging device, the photoelectric conversion device according to the present invention can be applied to, for example, an image input device, a facsimile,
7- Image input devices such as station, digital copying machine, word processor, OCR, barcode reading device, camera.

It can also be applied to photoelectric conversion object detection devices for autofocus of video cameras, 8mm cameras, etc.

FIG. 8(b) shows a transient refresh operation, an accumulation operation,
The graph shows the potential levels at each part of the emitter 1 base and collector during a read operation and a transient refresh operation.

The voltage level of each part is the potential seen externally.

There are some areas that do not match the internal potential level.

To simplify the explanation, the emitter-base diffusion potential is excluded. Therefore, when the emitter and base are shown at the same level in FIG. 8(b), there actually exists a diffusion potential applied between the emitter and the base.

In FIG. 8(b), states ■ and ■ perform a refresh operation, state ■ a storage operation, states ■ and ■ a read operation,
State ■ indicates the operating state when the emitter is grounded. Also, the potential level is negative on the upper side with O port as the border,
It is assumed that the lower side indicates a positive potential and that the base potential ζ before entering state (2) is zero volts, and that the collector potential is all biased at about 1ETTt from state (2) to state (3).

The above series of operations will be explained with reference to the timing diagram of FIG. 8(a).

As shown in waveform 67 in FIG. 8(a), at time t,
A positive voltage is applied to the terminal 37, that is, the refresh pressure ■Ii
When a voltage is applied, the potential 200 is applied to the state Φ in FIG.
As explained above, a partial pressure is applied to the base. This potential is at time 1. During the period from t2 to t2, the potential gradually decreases by 1 toward zero potential, and at time t, the potential becomes 201 as shown by the dotted line in FIG. 8(b). As explained earlier, in the transient refresh mode, at time 0, which is the potential vK remaining at the base, this potential is set to the refresh voltage VR14 as shown by the waveform 67.
At the moment when V returns to zero voltage, a voltage of VK is generated at the base by capacitance division, similar to the quotient, so the base becomes the potential that is the sum of the remaining voltage VK and the newly generated voltage. In other words, this is the base potential 202 shown in state (2).

ow ” ”-Cox+Cbe+Cbc ”'.

When light is incident on such an emitter in a reverse bias state, the holes generated by this light are accumulated in the base region, so that the intensity of the incident light increases as shown in state t). Accordingly, the base potential 202 gradually changes toward a positive potential as the base potential 203.203'203''.The voltage generated by this light is defined as Vp.

Next, as shown in waveform 69, when a voltage is applied from the vertical shift register to the 5 horizontal lines, that is, the readout voltage Vl, a voltage of C0 + Cbe + Cbc is added to the base, so the base potential when no light is irradiated is 204 becomes.The potential 204 at this time is as explained earlier.
It is set so that the emitter is biased in the closing direction by about 0.5 to 0.ev. Also.

Base potentials 2051, 205' and 205'' are respectively It can be done.

When the base potential is biased in the forward direction with respect to the emitter in this way, electron injection occurs from the emitter side, and the emitter potential gradually moves in the positive potential direction. Base position 2 when no light is irradiated
The emitter potential 207 for 04 is such that when the forward bias is set to 0.5 to 0.6 V), the read pulse width is
At about 2 gs, it is about 50 to 100 OIV, and if this voltage is VR, the emitter potential is 207.207'
207'', as in the previous example, linearity is sufficiently ensured if the pulse width is 0.1 gs or more, so each Vp +
VB, vp'-t-V, , vp -+ v, becomes.

After a certain readout time, when the readout voltage VR reaches zero level as shown in waveform 69, the voltage that becomes the base is added to the base, so that the voltage (
YOL becomes the state 8 degrees before the application of the successive pulses, that is, becomes a reverse bias state, and the potential change of the emitter accompanies it. That is, at this time, the base voltage A&, 208 is the base voltage 209.209', and the base voltage 209' is OX"+vp-'Cox+Cbe+Cb, respectively. @ V a
sot v, +vρ −Cox+ Cbe+ Cbc″VQHa
t ” ” vpCol+ Cbe+ Cbc” ”” This is the state of 11 power where reading begins.
is exactly the same.

In this state (5), the optical information signal on the emitter side is read out to the outside. After this readout is completed, each switching MOS transistor 48, 48', 48''
becomes conductive, the emitter is grounded, and as Φ, the emitter is at zero level. This completes a cycle of refresh operation, storage operation, and read operation, and then returns to state ①.At this time, although before starting the refresh operation for the first time, the base acid level started from zero potential. On the other hand, after the - cycle, the base level is ow ■, -Cox+Cbe+Cbc '"', and W1 with VP, VP', and VP " added to it, respectively.
This means that there has been a change in position. Therefore, in this state, even if the refresh voltage V1114 is applied, the base potential is V.

V< +Vp, Vl +Vp', VK+Vp''
In this case, sufficient bias in the ship direction is not applied to the base, and the light information disappears because the j forward bias is large in areas where the light hits strongly, but the information in areas where the light is weak is It is clear from the calculation example of the refresh operation shown in FIG. 6 that it remains without disappearing.

This kind of phenomenon is il! This is a special feature of 5fiIt-like Refre5/Shyurefure5, and in complete refresh mode, such a problem does not occur because it takes a long refresh time until the base potential becomes zero potential. A method that uses refresh mode and does not cause such inconvenience will be described below.

One way to solve this problem is to bring the base potential 210 generated in state (2) of FIG. 8(b) to zero potential. In this way, when a refresh pulse is applied in state (3), the base potential is zero potential as in the first state, so reliable transient refresh mode operation becomes possible.

FIG. 18 shows an embodiment for achieving this, fi
IJts diagram (a) shows the cross-sectional structure diagram of the optical sensor cell.
Figure 8(b) shows its equivalent circuit.

The emitter region 7 and the n4'' region 270 of the basic photosensor cell shown in FIG.
It forms the drain and source of the S transistor, and has a structure controlled by a gate 271 made of polysilicon or the like. Further, the n''ma 270 is connected to the base region 6 of the basic photosensor cell by a wiring 272.

The other parts are the same as the basic photosensor cell shown in FIG.

FIG. 18(b) is an equivalent circuit of the structural diagram of FIG. 18(a), in which a MOS transistor 273 consisting of a drain region 7, a gate 271, and a source region 270 common to the emitter region of the photosensor cell is connected to the base region 6 of the photosensor cell. and wiring 27
2, the drain region is common to the emitter region, and the gate 271 is connected to the wiring 274, forming a 4111 hole so that a pulse can be applied from the outside.

In the refresh operation, accumulation operation, and read operation, the wiring 2 is connected to the gate 271 of this MOS transistor.
It is assumed that a negative voltage is applied through 74 so that the channel of the MOS transistor becomes sufficiently non-conductive.

When the potential 210 of the base region is negative in state I operation in WIJ8 figure (b), the emitter is grounded, and if the gate 271 is set to zero potential or positive potential in this state, the MO
S) It is clear that the channel of the transistor becomes conductive, current flows and the base potential becomes zero potential.

In this way, the base level becomes zero potential in state ①, so in the next refresh operation, as shown in Fig. 8 (b
), the transient refresh mode operation is reliably performed and high-speed refresh is possible.

As described above, according to this embodiment, although the number of lines increases, an image sensor capable of high-speed operation can be obtained by simply adding one simple MOS transistor.

In the embodiment shown in FIG. 18, a MOS capacitor electrode 9, a wiring for connecting the source region 270 of the MOS transistor and the base region 6 of the photosensor cell, MOS)
For convenience of explanation, the wiring 8 for the gate 271 of the transistor and the emitter region 7 of the optical sensor cell are all drawn in the same cross section, and there are very few windows through which light enters. In the actual device, 1Tjj
- It is possible to arrange each of them in other parts of the optical sensor cell in consideration of the shape of the window through which the light enters, the convenience of wiring, etc.

In the above explanation, both refresh and read
Although the explanation is about the mode in which refresh is performed by the TrL pole 9 on the P base through the gate, it is also possible to perform refresh by the nMOS. That is, in this case, 1! Only a read pulse is applied to pole 9. Reading is completed - To refresh the sensor cells on the horizontal line, apply a positive voltage to 271 to make nMO3 conductive during the blanking period before reading out the sensor cells along the horizontal line of the first stage. vertical line 38.38
', . . . apply a negative voltage -Vp.

The P base region is charged to -(Vp-Vts'), and refreshing is completed. ■↑輔 is the threshold voltage of nMOS. This n MOS operates in such a way that the channel and the n''fI region 270 are at the same potential.

It is also possible to create a completely independent nM O3 for P-base refresh, in which case the n4'' emitter is completely independent, and two more n4'' regions 27 in the p-base.
0 and 275 are provided to constitute the nM OS.

Similar to what is shown in FIG. 18(a), the n"ffi castle 270 is connected to the P base 6 by electrode wiring,
The other n'' electrode 275 is connected to the gate 2 by electrode wiring.
When a voltage is applied to 71, a predetermined negative voltage -Vp is applied.

The circuit configuration diagram is shown in FIG. 19, along the horizontal line are lines 281 and 282 for applying a negative voltage.

・・・・・・・・・ is provided.

When a read pulse is applied to the horizontal line 275 to read out the sensor cells along this horizontal line, and then a read pulse is applied to 276 to read the horizontal line below, the read pulse is applied to the gate of the refresh nMOS transistor of the sensor cell along horizontal line 275, and is completed while reading the sensor cell along horizontal line 275 since a negative voltage -Vp is applied to line 281 at that time.

[Brief explanation of drawings]

t51 to FIG. 6 are diagrams for explaining the main structure and basic operation of a photosensor cell according to an embodiment of the present invention. Figure 1 (a) is a plan view, (b) is a sectional view, (C
) is an equivalent circuit diagram, 5 Figure 2 is an equivalent circuit diagram during read operation, Figure 3 is a graph showing the relationship between read time and read voltage, and Figure 4 (a) is the graph showing the relationship between the stored IITL pressure and read time. Figure 4 (b) is a graph showing the relationship between bias voltage and read time, gFSs is an equivalent circuit diagram during refresh operation, and Figures 6 (a) to (c) are graphs showing the relationship between bias voltage and read time. It is a graph showing the relationship with the base potential. FIG. 7-b) to FIG. 1O are explanatory diagrams of a photoelectric conversion device using the optical sensor cell shown in FIG. FIG. 8(b) is a graph showing the potential distribution during each operation. M.S.
FIG. 9 is an equivalent circuit diagram related to the output signal, and FIG. 1O is a graph showing the output voltage from the moment of conduction in relation to time. 11.12 and 13 are circuit diagrams showing other photoelectric conversion devices. FIG. 14 is a plan view for explaining the main structure of another optical sensor cell according to an embodiment of the present invention. FIG. 15 is a circuit diagram of a photoelectric conversion device using the optical sensor cell shown in FIG. ff114. Figures 16 and 17 are cross-sectional views showing an example of a method for manufacturing a photoelectric conversion device of the present invention. FIG. 18 shows an optical sensor cell according to an embodiment of the present invention, in which (a) is a cross-sectional view and (b) is an equivalent circuit diagram thereof. FIG. 19 is a circuit configuration diagram using the optical sensor cell shown in FIG. 18. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... psag, 3... Insulating oxide film, 4... Element # region, 5... n- region (
collector area), 6... p area (pace area), 7.
7'...n''' region (emitter region), 8... Wiring, 9... Electrode, 10... Wiring, 11... n' area 12... Electrode, 13... Capacitor, 14...
Bipolar transistor, 15.17... Junction capacitance,
16.18...Diode, 19.19'...Contact part, 20...Light. 28... Vertical line, 30... Optical sensor cell, 31
...Horizontal line, 32...Vertical shift register, 3
3.35...MOS) transistor, 36.37...
Terminal 38...Vertical line, 39...Horizontal shift register 40...MOS transistor, 41...Output line 42...MOS) transistor, 43...Terminal,
44...Transistor, 44.45...Load resistance
, 46... terminal, 47... terminal, 48... MOS
) Ranjistal 9... terminal, 61, 62.63...
Section, 64... Collector potential, 67... Waveform,
80.81...8 steepness 82.83...resistance, 84...
・Current source, LOO, 101, 102...Horizontal shift register, 111°112...Output line, 1
38... Vertical line 140... MOS transistor, 148... MOS transistor, 150.150'
...MOS capacitor, 152,152'...Photo sensor cell, 202°203.205...Base potential,
220...p0 region. 222°225...Wiring, 251...p+ region 2
52... n4P region, 253... wiring, 300...
・Amorphous silicon, 302...Nitride 11,30
3...psc membrane, 304...polysilcon, 305
... psc s, 306... interlayer insulating film.

Claims (1)

[Claims] 1. A control electrode region of a semiconductor transistor consisting of two main electrode regions of the same conductivity type and a control electrode region of an opposite conductivity type to the main electrode region is brought into a floating state, and the potential of the control electrode region brought into the floating state. an accumulation operation in which carriers generated by light are accumulated in the control electrode region set in a floating state by controlling via a capacitor, a readout operation in which the accumulated voltage generated in the control electrode region by the accumulation operation is read out; In a light conversion device having a structure capable of performing a refresh operation to eliminate carriers accumulated in the control electrode region, a part of the control electrode region in a floating state has a conductivity type opposite to that of the control electrode region. At least one high concentration region is provided adjacent to the surface other than the main electrode region, and the high concentration region of the opposite conductivity type is used as the main electrode region of an insulated gate transistor for controlling the potential of the control electrode region. A photoelectric conversion device characterized by: