JPH0447983B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device that accumulates carriers generated by incident light and reads out signals based on the accumulated carriers.

[Prior Art] In recent years, research on photoelectric conversion devices, particularly solid-state imaging devices, has been actively conducted along with the progress of semiconductor technology, and some of them have begun to be put into practical use.

These solid-state imaging devices can be broadly classified into
It is classified into two types: CCD type and MOS type. A CCD type imaging device forms a potential well under a MOS capacitor electrode, stores charges generated by incident light in this well, and during readout, these potential wells are sequentially moved by pulses applied to the electrode. The principle is that the accumulated charge is transferred to the output amplifier section and read out. Also
Some CCD imaging devices use a pn junction diode structure for the light receiving section and a CCD structure for the transfer section. On the other hand, a MOS type imaging device accumulates the charge generated by the incidence of light on each photodiode made of a pn junction that constitutes the light receiving section, and when reading out the charge, the MOS switching transistor connected to each photodiode is activated. It uses the principle that the accumulated charge is read out to the output amplifier section by sequentially turning on the transistors.

CCD type imaging device has a relatively simple structure,
In addition, considering the noise that can be generated, only the capacitance value of the charge detector consisting of the floating diffusion in the final stage contributes to random noise, so it is a relatively low-noise imaging device and is capable of low-light photography. be. However, due to process constraints in manufacturing CCD type imaging devices, MOS is used as the output amplifier.
Since the type amplifier is on-chip, 1/f noise, which is easily noticeable on images, is generated from the interface between silicon and SiO ₂ film. Therefore, although it is said to have low noise, there are limits to its performance. Furthermore, if the number of cells is increased to achieve higher density in order to achieve higher resolution, the maximum amount of charge that can be stored in one potential well will decrease, making it impossible to maintain a dynamic range. This becomes a big problem as resolution increases. Furthermore, since a CCD-type imaging device transfers accumulated charge by sequentially moving the potential wells, even if there is a defect in one of the cells, charge transfer may stop at that point, or It also has the disadvantage that the manufacturing yield cannot be improved.

On the other hand, MOS type imaging devices are structurally
Although it is a little more complicated than a CCD type imaging device, especially a frame transfer type device, it has the advantage of being able to be configured to have a large storage capacity and having a wide dynamic range. Furthermore, even if one of the cells has a defect, because of the X-Y addressing method, the defect does not affect other cells, which is advantageous in terms of manufacturing yield. However, this
In MOS type imaging devices, wiring capacitance is connected to each photodiode during signal readout, which causes an extremely large signal voltage drop and a drop in the output voltage.The wiring capacitance is large, which causes random noise. It also has disadvantages such as fixed pattern noise mixed in due to variations in the parasitic capacitance of each photodiode and MOS switching transistor for horizontal scanning, and that low-light photography is difficult compared to CCD type imaging devices. have.

Furthermore, in the future, as the resolution of imaging devices increases, the size of each cell will be reduced and the amount of accumulated charge will decrease. On the other hand, the wiring capacitance, which is determined by the chip size, does not decrease much even if the line width is made thinner. For this reason, the MOS type imaging device becomes increasingly disadvantageous in terms of S/N.

Although CCD type and MOS type imaging devices have the above-mentioned advantages and disadvantages, they are gradually approaching the level of practical use. However, it can be said that there are essentially major problems in promoting the higher resolution that will be required in the future.

On the other hand, regarding solid-state imaging devices,
−150878 Publication “Semiconductor Imaging Device”, Japanese Unexamined Patent Publication No. 1983-
Publication No. 157073 “Semiconductor imaging device”, Japanese Patent Application Laid-open No. 1983-
A new method is proposed in Publication No. 165473 "Semiconductor imaging device". CCD type and MOS type imaging devices are
Charges generated by incident light are transferred to the main electrode (e.g.
In contrast, the method proposed here stores the charge generated by incident light on the control electrode (e.g., the base of a bipolar transistor, the SIT (static induction transistor) or the MOS transistor). gate)
It is based on a new concept of controlling the flowing current using the charges accumulated in the light and generated by light. That is, CCD type, MOS type,
In contrast to reading out the accumulated charge itself to the outside, the method proposed here uses the amplification function of each cell to amplify the charge before reading out the accumulated charge. If the output is changed, the impedance is converted and the output is read out as a low impedance. Therefore, the method proposed here has high output, wide dynamic range, and low noise, and because the carriers (charges) excited by the optical signal accumulate on the control electrode, non-destructive readout is possible. It has several advantages such as: Furthermore, it can be said that this method has the potential for higher resolution in the future.

[Technical Problems to be Solved by the Invention] However, this method is basically an X-Y addressing method, and the element structure described in the above publication is a bipolar transistor in each cell of a conventional MOS type imaging device. The basic configuration is a combination of amplification elements such as , SIT transistors, etc.
Therefore, it has a relatively complicated structure, and although it has the possibility of achieving high resolution, there is a limit to how high resolution can be achieved as it is.

There are also limitations in the points described below. The above-mentioned Japanese Patent Application Publication No. 150878, Japanese Patent Application Publication No. 56-1508-
No. 157073, Japanese Patent Application Laid-open No. 165473, and “Application to SIT (Static Injection Transistor) Image Sensor, Technical Report of the Television Society (hereinafter referred to as
``TV Society Journal'' is a typical example of the prior art in which one of the inventors of the present invention was involved.

JP-A-56-150878 and JP-A-56-157073 disclose that charges are added to the P ⁺ region of a hook structure consisting of N ⁺ , P ⁺ , I (or P ^- , N ^- ), and N ⁺ regions. accumulate,
N ⁺ forming a capacitor with ground potential
A configuration is described in which the potential of a region is read out using a switching transistor.

However, with this configuration, high-speed readout with good linearity is not possible, and sensitivity is also limited.

On the other hand, Japanese Patent Application Laid-open No. 56-165473 describes the N ⁺ region,
N + , P ⁺ , I (or P ^{- ,} N ^- ), N ⁺ , consisting of a floating P ⁺ region, a high resistance region and an N ⁺ region connected to a transparent electrode to which a pulsed voltage is applied. The hook structure of the region is shown. The floating N ⁺ region also serves as one of the main electrode regions of the readout transistor, and during readout, the transistor is turned on and electrons flow into the positively charged N ⁺ region, and the voltage change is used as a signal. Perform reading. However, this method also does not allow high-speed readout with good linearity, and has a limit in sensitivity.

The TV Society Journal describes gate storage type photocells and base storage type photocells. Among these, the gate storage type photocell has a configuration in which the gate is placed in a floating state, the gate region is reverse biased to a predetermined voltage via a refresh line via an insulating film, and the voltage is read out to an output circuit with a grounded source resistive load.

On the other hand, the base storage type photocell has N ⁺ , P ⁺ ,
It has an N ^- , N ⁺ phototransistor structure, and has a floating base (P ⁺ ), a collector (N ⁺ ) to which a pulsed voltage is applied, and an emitter follower output that includes a capacitor and a switching MOSFET. It consists of an emitter (N ⁺ ) to which a circuit is connected. In any case, these methods cannot perform high-speed readout with good linearity, and their sensitivity is also limited.

In addition to the above-mentioned conventional technology, there is also a U.S. patent
In the specification of No. 3624428 and Japanese Patent Publication No. 50-38531, an output circuit with a grounded emitter resistor load is connected to a transistor whose base is provided with an electrode via an insulating layer, and the base is reverse biased to perform an accumulation operation. A configuration is shown in which the current is read out using the output circuit of the emitter-grounded resistive load. However, since this is a current readout from a destructive sensor, linearity and afterimage characteristics are poor. Also, the sensitivity is not good.

[Object of the Invention] An object of the present invention is to provide an improved photoelectric conversion device using a carrier accumulation method, which has an amplification function in each cell, has an extremely simple structure, and can sufficiently cope with future increases in resolution. There is a particular thing.

Another object of the present invention is to provide a photoelectric conversion device with excellent sensitivity and high speed, which can obtain an output signal with good linearity with respect to irradiated light in a very short time. be.

This purpose is to form a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type different from the first conductivity type.
It has a semiconductor region, a high-resistance semiconductor region, a third semiconductor region of a first conductivity type, and a fourth semiconductor region of a second conductivity type, and the first semiconductor region and the second semiconductor region are adjacent to each other. The third semiconductor region and the fourth semiconductor region are arranged adjacent to each other, and the high-resistance semiconductor region is located between the second semiconductor region and the third semiconductor region. The first semiconductor region, the second semiconductor region, the third semiconductor region, and the high-resistance semiconductor region constitute a first transistor, and the second semiconductor region and the third semiconductor region constitute a first transistor. A second transistor is configured by the fourth semiconductor region and the high-resistance semiconductor region, and one of the second semiconductor region and the third semiconductor region is a carrier composed of electrons and holes generated by photoexcitation. A photoelectric conversion device in which one side accumulates holes and the other side accumulates electrons, the first electrode capacitively coupled to the second semiconductor region, and the second electrode capacitively coupled to the third semiconductor region.
electrodes, and readout means for reading out signals based on electrons and holes accumulated in the second and third semiconductor regions, respectively, and the readout means includes electrodes in the second and third semiconductor regions. and the third semiconductor region, independently apply a potential to the first and fourth semiconductor regions by the first and second electrodes, and the second semiconductor region and the first semiconductor region and the third
This is achieved by a photoelectric conversion device characterized in that the junction portion between the semiconductor region and the fourth semiconductor region is biased in the forward direction to read out the signal.

[Function] According to the present invention, both electrons and holes as carriers generated by optical excitation can be accumulated and read out while increasing the gain, making it possible to perform extremely sensitive photoelectric conversion. can.

[Example] An outline of a preferred embodiment according to the present invention will be described below.

Its most characteristic configuration is expressed in the embodiments shown in FIGS. 1 to 13, particularly in the embodiments shown in FIGS. 10 to 13. The details will be described later, but the outline will first be explained using FIG. 1 as an example.

The NPN transistor as the first transistor indicated by the reference numeral 360 in FIG. 1c includes an n ⁺ region 7 as the first semiconductor region in FIG. It is composed of an n ⁺ region 351 as a region and an n ⁻ region 5 as a high resistance semiconductor region.

A PNP transistor 361 as a second transistor includes a p region 6 as a second semiconductor region,
n ⁺ region 351 as the third semiconductor region and the fourth
It is composed of a p ⁺ region 350 as a semiconductor region and an n ⁻ region 5 as a high resistance semiconductor region.

Here, the p region 6 accumulates holes among carriers composed of electrons and holes generated by photoexcitation, and the n ⁺ region 351 accumulates electrons.

In order to facilitate understanding of the photoelectric conversion device according to the present invention, a type of carrier that stores only holes among carriers composed of electrons and holes will be described below, including its peripheral circuits.

First, referring to FIGS. 14 and 15, an output circuit is connected to one of the main electrode regions (emitter) of a photoelectric conversion cell including a transistor as shown by the reference numeral 30 in FIG. This output circuit includes vertical lines 38, 38', 38'', horizontal shift register 39, MOS transistors 40, 40',
40″, output line 41, MOS transistor 4
2, an output transistor 44, a load resistor 45, etc., and each of the vertical lines 38, 38', 38'' has a wiring capacitance as a capacitive load, such as Cs indicated by reference numeral 21 in FIG.

Further, a vertical shift register 32, a buffer MOS transistor 33, a vertical shift register 32, a buffer MOS transistor 33,
33', 33'', terminal 34, horizontal line 31, 3
1', 31'' is provided.

During storage operation, the emitter is grounded and the other main electrode region (collector) is biased to a positive potential. Further, the control electrode region (base) is placed in a reverse bias state with respect to the emitter, and the saturation voltage can be determined by controlling the base potential at this time. By appropriately setting the bias voltage in this manner, the cell itself can have a switching effect.

During a read operation, the emitter is left floating and the collector is biased to a positive potential. The potential of the control electrode region is controlled by the readout means independently of the main electrode region. If the base is biased in the forward direction with respect to the emitter, high-speed readout can be achieved while ensuring good linearity. The operation at this time will be explained with reference to FIG. At the time of reading, a positive voltage _VR is applied independently from the wiring 10 to the emitter in a floating state and the collector held at a positive potential, thereby biasing the base potential in the forward direction with respect to the emitter potential. This causes the emitter-base junction to be deeply biased in the forward direction. In this way, a current flows until the emitter potential becomes equal to the base potential, that is, the accumulated voltage generated by light irradiation.The time required for this is further shortened by the action of the voltage _VR , allowing high-speed readout. Also, excellent linearity can be ensured.

The refresh operation is as follows.

The emitter is connected to a first reference voltage source, indicated by the earth symbol, and grounded by means of MOS transistors 48, 48', 48'' as switching means.The collector is then connected to a second reference voltage source, i.e. The voltage is set to positive potential or ground potential.The case where the collector is grounded is shown in Fig. 16.In such a state, a voltage of positive _{potential VRH} is applied to raise the potential of the base as the control electrode region. Through control, at least a forward bias is applied between the base and emitter, holes accumulated in the base region flow out, electrons flow into the base region, and the accumulated charge disappears. Forward bias means for applying forward bias include MOS transistors 48, 48', 48'', buffer MOS transistors 35, 35', 35'',
It is configured by providing terminals 36, 37, etc.

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, prior to explaining the photoelectric conversion device of the present invention, the basic structure and operation of a photosensor cell that constitutes the photoelectric conversion device of the present invention will be explained.

FIG. 17 is a diagram illustrating the basic structure and operation of a photosensor cell that constitutes a photoelectric conversion device according to the present invention.

FIG. 17a shows a top view of the optical sensor cell in the first
7b is a cross-sectional view of a portion AA' in the plan view of FIG. 17a, and FIG. 17c is an equivalent circuit thereof. In addition, the same numbers are given to the parts common to FIGS. 17a, b, and c in each part.

Although FIG. 17 shows a plan view of the aligned arrangement method, it goes without saying that the pixel shifting method (interpolation arrangement method) can also be used to increase the horizontal resolution.

As shown in FIGS. 17a and 17b, this optical sensor cell is constructed on a silicon substrate 1 doped with impurities such as phosphorus (P), antimony (Sb), and arsenic (As) to make it n-type or n ⁺ type. In addition, a passivation film 2 usually made of a PSG film or the like; an insulating oxide film 3 made of a silicon oxide film (SiO ₂ ); and a SiO ₂ or Si ₃ N ₄ film for electrically insulating between adjacent photosensor cells. an element isolation region 4 made of an insulating film or a polysilicon film, etc.; an n ^- region 5 with a low impurity concentration formed by epitaxial technology, etc.; P region 6 doped with impurities such as boron (B), which becomes the base of the bipolar transistor; n ⁺ which becomes the emitter of the bipolar transistor formed by impurity diffusion technology, ion implantation technology, etc.
Region 7; Wiring 8 made of a conductive material such as aluminum (Al), Al-Si, Al-Cu-Si, etc. for reading out signals to the outside; P region made in a floating state through the insulating film 3 electrode 9 for applying a pulse to the substrate 1; its wiring 10; an n ⁺ region 11 with a high impurity concentration formed by impurity diffusion technology to establish ohmic contact with the back surface of the substrate 1; , that is, an electrode 12 made of a conductive material such as aluminum for providing a collector potential of a bipolar transistor;

Note that 19 in FIG. 17a indicates the n ⁺ region 7 and the wiring 8.
This is the contact part for making the connection. Also, the alternating portions of the wiring 8 and the wiring 10 are so-called 2
They are layered interconnects, and are insulated from each other by insulating regions made of an insulating material such as SiO ₂ . That is, it has a two-layer metal wiring structure.

The capacitor Cox 13 in the equivalent circuit of ^FIG .
It is composed of an n ^- region 5 having a low impurity concentration and an n or n ⁺ region 1 serving as a collector.
As is clear from these drawings, p region 6 is made into a floating region.

The second equivalent circuit in FIG. 17c shows the bipolar transistor 14 with base-emitter junction capacitance.
Cbe15, base-emitter pn junction diode
Dbe16, base-collector junction capacitance Cbc1
7. Base-collector pn junction diode Dbc1
This is expressed using 8.

Here, as the original equivalent circuit diagram, pn junction diode Dbe16 and pn junction diode Dbc18
Symbols indicating two different orientations of current sources that should be written in parallel with are omitted.

The basic operation of the optical sensor cell will be explained below using FIG. 17.

The basic operation of this photosensor cell consists of a charge accumulation operation by light incidence, a readout operation, and a refresh operation.

First, charge storage operation will be explained.

In charge storage operation, for example, the emitter is
It is grounded through a wiring 8, and its collector is biased to a positive potential through a wiring 12. In addition, the base is connected to the capacitor Cox13 in advance, and the wiring 10
It is assumed that by applying a positive pulse voltage through the emitter 7, a negative potential is applied, that is, a reverse bias state is applied to the emitter 7. The operation of biasing the base 6 to a negative potential by applying a pulse to the Cox 13 will be explained in detail later when the refresh operation is explained.

In this state, when light 20 is incident from the front side of the photosensor cell as shown in FIG. 17, a pair of retectron holes is generated within the semiconductor. Of these, electrons flow toward the n-region 1 side because the n-region 1 is biased to a positive potential, but holes are rapidly accumulated in the p-region 6. Due to the accumulation of holes in the p region, the potential of the p region 6 gradually changes toward a positive potential.

In FIGS. 17a and 17b, the lower surface of the light-receiving surface of each sensor cell is mostly occupied by the p region, and some n ⁺
It has become area 7. Naturally, the concentration of electron-hole pairs excited by light increases as it approaches the surface. Therefore, many electron-hole pairs are excited in the p-region 6 by the light.
If the structure is such that electrons photoexcited in the p-region immediately flow out of the p-region 6 without recombination and are absorbed in the n-region, the holes excited in the p-region 6 will be accumulated as they are. p
The region 6 is changed to a positive potential direction. When the impurity concentration of p region 6 is uniform, electrons excited by light are diffused and are connected to p region 6 and n ^-
It flows to the pn ^- junction with region 5, and is then absorbed by n collector region 1 due to drift due to the strong electric field applied to the n ^- region. Of course, it is possible for electrons to travel within the p region 6 by diffusion alone, but if the structure is configured so that the p-based impurity concentration decreases from the surface to the inside, this impurity concentration difference , an electric field Ed, Ed=1/W _B・kT/q・lnN _AS /N _Ai , is generated in the base from the inside toward the surface. Here, W _B is the depth from the light incident surface of the p region 6, k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, N _AS is the surface impurity concentration of the p base region 6, and N _Ai is the p Region 6 n ^- High resistance region 5
is the impurity concentration at the interface with

Here, if N _AS /N _Ai >3, the movement of electrons in p region 6 will be performed by drift rather than diffusion. That is, in order to effectively operate carriers excited by light in p-region 6 as signals, the impurity concentration of p-region 6 must decrease from the light-incidence side surface toward the inside. is desirable. When p region 6 is formed by diffusion, its impurity concentration decreases toward the inside compared to the light incident side surface.

A portion below the light-receiving surface of the sensor cell is occupied by the n ⁺ region 7 . The depth of n ⁺ region 7 is typically 0.2
Since the thickness is designed to be approximately 0.3 μm or less, the amount of light absorbed by the n ⁺ region 7 is not so large to begin with, so there is no problem. just,
For light on the short wavelength side, especially blue light, the presence of the n ⁺ region 7 causes a decrease in sensitivity. The impurity concentration of the n ⁺ region 7 is usually designed to be about 1×10 ²⁰ cm ⁻³ or more. The diffusion distance of holes in the n ⁺ region 7 doped with impurities at such a high concentration is about 0.15 to 0.2 μm. Therefore, in order to effectively flow the holes optically excited in the n ⁺ region 7 into the p region 6, the n ⁺ region 7 must also have a structure in which the impurity concentration decreases from the light incident surface toward the inside. desirable. If the impurity concentration distribution in the n ⁺ region 7 is as described above, a strong drift electric field will be generated from the surface on the light incidence side toward the inside, and the holes photoexcited in the n ⁺ region 7 will immediately become p
Flows into area 6. If the impurity concentration of both the n ⁺ region 7 and the p region 6 decreases from the light incident side surface toward the inside, then the n ⁺ region 7 and the p region existing on the light incident side surface side of the sensor cell 6
All optically excited carriers function effectively as optical signals. If this n ⁺ region 7 is formed by impurity diffusion from a silicon oxide film or polysilicon film doped with As or P at a high concentration, it is possible to obtain an n ⁺ region with the desired impurity gradient as described above. It is.

Eventually, the accumulation of holes will cause the base potential to change to the emitter potential, in this case to ground potential, where it will be clipped.
More precisely, the base and emitter are biased deeply in the forward direction, and the holes accumulated in the base are clipped at a voltage that begins to flow to the emitter. That is, the saturation potential of the photosensor cell in this case is approximately given by the potential difference between the bias potential when p region 6 is initially biased to a negative potential and the ground potential. When n ⁺ region 7 is not grounded and accumulates charges generated by optical input in a floating state, p region 6 can accumulate charges to approximately the same potential as n region 1 .

The above is a qualitative and general explanation of the charge accumulation operation, but a more specific and quantitative explanation will be given below.

The spectral sensitivity distribution of this optical sensor cell is given by the following equation.

S (λ) = λ/1.24・exp(−αx) × {1−exp(−αy)}・T [A/W] However, λ is the wavelength of light [μm], and α is the light wavelength in the silicon crystal. x is the attenuation coefficient [μm ^-1 ], x is the thickness of the “dead layer” on the semiconductor surface that causes recombination loss and does not contribute to sensitivity [μm], y
is the thickness of the epitaxial layer [μm], and T is the transmittance, that is, the ratio of the amount of light that effectively enters the semiconductor, taking into account reflection and the like with respect to the amount of incident light. Using the spectral sensitivity S (λ) and irradiance Ee (λ) of this optical sensor cell, we calculate the photocurrent
Ip is calculated using the following formula.

Ip＝∫ ^∞ ₀ S(λ)・Ee(λ)・dλ [μA/cm ² ] However, irradiance Ee (λ) [μW・cm ^-2・nm ^-1 ]
is given by the following equation.

Ee (λ) = E _V・P (λ) / 6.80∫ ^∞ / ₀ V (λ) P (
λ)・dλ [μW・cm ^-2・nm ^-1 ] However, E _V is the illuminance of the sensor's light receiving surface [Lux], P
(λ) is the spectral distribution of light incident on the light receiving surface of the sensor, and V(λ) is the relative luminous efficiency of the human eye.

Using these equations, for an optical sensor cell with an epitaxial layer of 4 μm, when irradiated with light source A (2854°K) and the sensor light receiving surface illuminance is 1 [Lux], approximately
A photocurrent of 280 nA/cm ^-2 flows, and the number of incident photons or the number of generated electron/hole bodies is approximately 1.8×10 ¹² /cm ² ·sec.

Also, at this time, the potential Vp generated by the accumulation of holes excited by light in the base is Vp=
It is given by Q/C. Q is the amount of accumulated hole charge, and C is the junction capacitance that is the sum of Cbe15 and Cbc17.

Now, the impurity concentration of n ⁺ region 7 is 10 ²⁰ cm ^-3 , the impurity concentration of p region 6 is 5×10 ¹⁶ cm ^-3 , the impurity concentration of n ^- region 5 is 10 13 cm -3 , and the impurity concentration of n ⁺ region 7 is 10 ¹³ cm ^-3 . The area is 16μm ² , p
When the area of region 6 is 64 μm ² and the thickness of n ^- region 5 is 3 μm, the junction capacitance is approximately 0.014 pF. On the other hand, the number of holes accumulated in p region 6 is determined by the accumulation time 1/ 60sec, effective light receiving area, i.e. p region 6
The area obtained by subtracting the area of electrodes 8 and 9 from the area of
If it is about 56μm ² , it will be 1.7×10 ⁴ pieces. Therefore, the potential Vp generated by light incidence is about 190 mV.

What should be noted here is that as the resolution increases and the cell size decreases, the amount of light incident on each photosensor cell decreases, and the amount of accumulated charge Q also decreases. As the cell size decreases, the junction capacitance also decreases in proportion to the cell size, so the potential Vp generated by light incidence remains almost constant. This is because the optical sensor cell according to the present invention has an extremely simple structure, as shown in FIG. 17, and has the possibility of having an extremely large effective light-receiving surface.

This is one of the reasons why the photoelectric conversion device of the present invention is advantageous compared to the case of an interline type CCD. If an attempt is made to ensure this, the area of the transfer section becomes relatively large, which reduces the effective light-receiving surface, resulting in a decrease in sensitivity, that is, the voltage generated by light incidence. In addition, in the interline type CCD type imaging device, the saturation voltage is limited by the size of the transfer section and gradually decreases, whereas in the optical sensor cell of the present invention, as mentioned earlier, the saturation voltage The saturation voltage is determined by the bias voltage when p-region 6 is biased to a negative potential, and a large saturation voltage can be ensured.

The operation of reading out the voltage generated by the charges accumulated in p region 6 as described above to the outside will be described next.

In the read operation state, the emitter and wiring 8 are held in a floating state at the collector positive potential Vcc.

FIG. 15 shows an equivalent circuit.

Also here, symbols indicating two current sources in different directions that should originally be written in parallel with the pn junction diode Dbe16 and the pn junction diode Dbc18 as an equivalent circuit are omitted.

Now, if the potential when the base 6 is biased to a negative potential before light irradiation is -V _B , and the accumulated voltage generated by light irradiation is V _P , then the base potential is
The potential is −V _B +V _P. In this state, a positive voltage V _R for reading is applied to the electrode 9 through the wiring 10.
is applied, this positive potential V _R is applied to the oxide film Cox1
3, the base-emitter junction capacitance Cbe15, and the base-collector junction capacitance Cbc7, and the voltage Cox/Cox+Cbe+Cbc·V _R is added to the base. Therefore, the base potential becomes −V _B −V _P +Cox/Cox+Cbe+Cbc·V _R. Here, if the condition -V _B +Cox/Cox+Cbe+Cbc·V _R =0 is established, the base potential becomes the accumulated voltage V _P generated by light irradiation. When the base potential is biased in a positive direction with respect to the emitter potential in this way, electrons are injected from the emitter to the base, and since the collector potential is positive, they are accelerated by the drift electric field and flow into the collector. reach. The current flowing at this time is given by the following equation.

i=A _j・q・Dn・n _pe /W _B (1+lnN _Ae /N _Ac
)×{expq/kT(V _P −V _e )−1} where A _j is the junction area between the base and emitter, q
is the unit charge (1.6×10 ^-19 coulombs), D _o is the electron diffusion constant in the base, n _pe is p
Electron concentration as a minority carrier at the base emitter end, W _B is the base width, N _Ae is the acceptor concentration at the base emitter end, N _Ac
is the acceptor concentration at the collector end of the base,
k is Boltzmann's constant, T is absolute temperature, and V _e is emitter potential.

This current has an emitter potential V _e as a base potential,
In other words, here the accumulated voltage generated by light irradiation
It is clear from the above equation that the flow continues until it becomes equal to V _P. At this time, the temporal change in the emitter potential V _e is calculated using the following formula.

Cs・dV _e /dt=i=A _j・q・Dn・n _pe /W _B (1+lnN _Ae /N _AC )×{expq/kT (V _P −V _e )−1} However, here, the wiring capacitance Cs is the capacitance 21 of the wiring 8 connected to the emitter.

FIG. 18 shows an example of a temporal change in emitter potential calculated using the above formula.

According to FIG. 18, it takes about 1 second for the emitter potential to become equal to the base potential. This is because when the emitter potential V _e approaches V _P , less current flows. Therefore, the means to solve this problem is to set the condition −V _B +Cox/Cox+Cbe+Cbc·V _R =0 when applying the positive voltage V _R to the electrode 9, but instead of this condition − One possible method is to insert the condition that V _B +Cox/Cox+Cbe+Cbc・V _R =V _Bias and bias the base potential by V _Bias in the forward direction.
The current flowing at this time is given by the following equation.

i=A _j・q・Dn・n _pe /W _B (1+lnN _Ae /A _AC
)×{expq/kT(V _P +V _Bias −V _e )−1} In Figure 19a, when V _Bias = 0.6V, after a certain period of time, the V _R applied to the electrode 9 is reduced to zero volts. The relationship between the read voltage, that is, the emitter potential, and the accumulated voltage V _P when the current is restored and the flowing current is stopped is shown. However, in Figure 19a,
A constant potential depending on the read time due to the bias voltage component is necessarily added to the read voltage, but the value obtained by subtracting the gain is plotted. When the positive voltage V _R applied to the electrode 9 is returned to zero volts, a voltage of -Cox/Cox+Cbe+Cbc・V _R is added to the base potential, which is the opposite of when it was applied, so the base potential becomes the positive potential V It becomes the state before applying _R , that is, -V _B , and the emitter is reverse biased, so the flow of current stops. 19th
According to Figure a, if the readout time is about 100ns or more (that is, the time during which V _R is applied to the electrode 9),
The linearity of the storage voltage V _P and the read voltage is ensured over a range of about 4 digits, indicating that high-speed read is possible. In Figure 19a, the 45° line is the result when sufficient time is taken for reading.In the above calculation example, the capacitance Cs of the wiring 8 is set to 4pF, which is the junction capacitance of Cbe + Cbc.
Although it is about 300 times larger than 0.014 pF, the accumulated voltage V _P generated in the p region 6 is not attenuated in any way, and due to the effect of the bias voltage,
Figure 19a shows that the reading is extremely fast.
shows. This is because the amplification function, that is, the charge amplification function, of the photosensor cell according to the above configuration is working effectively.

On the other hand, in a conventional MOS type imaging device, the accumulated voltage V _P is Cj・V _P /(Cj + Cs) (however, Cj is
p-n junction capacitance of the light receiving part of the MOS type image pickup device),
It has a drawback that the read voltage value decreases by about 2 digits. For this reason, in MOS type imaging devices,
Fixed pattern noise due to variations in parasitic capacitance of switching MOS transistors for external readout, or random noise caused by large wiring capacitance, that is, output capacitance, is large, and S/
Although there was a problem that the N ratio could not be obtained, in the photosensor cells having the configurations shown in FIGS. 17a, b, and c, the accumulated voltage itself generated in the p region 6 is read out to the outside, and this voltage Since it is quite large, fixed pattern noise and random noise caused by the output capacitance are relatively small, making it possible to obtain a signal with an extremely good S/N ratio.

Previously, we showed that when the bias voltage V _Bias is set to 0.6 V, linearity of about 4 orders of magnitude can be obtained with a high-speed readout time of about 100 nsec, but the relationship between this linearity, readout time, and bias voltage V _Bias is The calculated results are shown in more detail in FIG. 19b.

In Figure 19b, the horizontal axis is the bias voltage
V _Bias , and the vertical axis shows the read time. Also, the parameters are that when the storage voltage is 1mV, the readout voltage is 80%, 90%, 95% of 1mV,
It shows the time dependence until it reaches 98%. 1st
As shown in Figure 9a, when the storage voltage is 80%, 90%, 95%, and 98% at a storage voltage of 1 mV, it is clear that the values are even better at higher storage voltages. It is.

According to this FIG. 19b, the bias voltage V _Bias
When is 0.6V, the readout time is 0.12μs for the readout voltage to be 80% of the storage voltage, and the readout time to be 90% is
0.27μs, 95% is 0.54μs, 98% is
It can be seen that the time is 1.4μs. Also, the bias voltage
This shows that even higher speed reading is possible if V _Bias is made larger than 0.6V. Like this,
Once the readout time and required linearity are determined from the overall design of the imager, the required bias voltage V _Bias can be determined by using the graph of FIG. 19b.

Another advantage of the optical sensor cell having the above configuration is that the holes accumulated in the p region 6 can be read out non-destructively since the probability of recombination of electrons and holes in the p region 6 is extremely small. That is, when the voltage V _R applied to the electrode 9 during readout is returned to zero volts, the potential of the p region 6 becomes the reverse bias state before applying the voltage V _R , and the accumulated voltage V _P generated by light irradiation becomes , it will be preserved as is unless it is exposed to new light. This means that when the optical sensor cell according to the above configuration is configured as a photoelectric conversion device, new functions can be provided in terms of system operation.

The time that the accumulated voltage V _P can be held in the p region 6 is extremely long, and the maximum storage time is rather
It is limited by the thermally generated dark current in the junction depletion layer. In other words, this thermally generated dark current saturates the optical sensor cell. However, in the photosensor cell having the above configuration, the region in which the depletion layer spreads is the n ^- region 5 which is a low impurity concentration region, and this n ^- region 5 is 10 ¹² cm ^-3 to 10 ¹⁴ cm ^-3 Due to its extremely low impurity concentration, its crystallinity is good.
Compared to MOS and CCD type imaging devices, fewer electron-hole pairs are thermally generated. Therefore, the dark current is small compared to other conventional devices. That is, the optical sensor cell according to the above configuration essentially has a structure with low dark current noise.

Next, the operation of refreshing the charges accumulated in p region 6 will be explained.

In the photosensor cell having the above configuration, as already mentioned, the charges accumulated in the p region 6 are not eliminated by the read operation. Therefore, in order to input new optical information, a refresh operation is required to eliminate the previously accumulated charges.
At the same time, it is necessary to charge the potential of p region 6, which is in a floating state, to a predetermined negative voltage.

In the optical sensor cell having the above configuration, the refresh operation is also performed by applying a positive voltage to the electrode 9 through the wiring 10, similarly to the read operation. At this time, the emitter is grounded through the wiring 8. The collector is grounded or at a positive potential through the electrode 12. FIG. 16 shows an equivalent circuit for refresh operation. However, an example is shown in which the collector side is grounded.

When a positive voltage V _RH is applied to the electrode 9 in this state, the oxide film capacitance Cox1 is applied to the base 22.
3. Due to the capacitance division of the base-emitter junction capacitance Cbe15 and the base-collector junction capacitance Cbc17, a voltage of Cox/Cox+Cbe+Cbc·V _RH is instantaneously applied as in the previous read operation. Due to this voltage, the base-emitter junction diode Dbe16 and the base-collector junction diode Dbc18 are forward biased and become conductive, current begins to flow, and the base potential gradually decreases.

At this time, the change in the potential V of the base in a floating state is approximately expressed by the following equation.

(Cbe + Cbc) dV/dt = - (i ₁ + i ₂ ) However, i ₁ = Ab (qD _{P poe} / Lp + qD _o n _pe / W _B ) × {exp (q / kTV) - 1} i ₂ = AeqD _o n _pe /W _B ×{exp(q/kTV)−1} i ₁ is the current flowing through the diode Dbc, and i ₂ is the current flowing through the diode Dbe. A _b is the base area,
Ae is the emitter area, Dp is the hole diffusion constant in the collector, p _oe is the hole concentration in the collector at thermal equilibrium, Lp is the mean free path of holes in the collector, n _pe is the electron concentration in the base at thermal equilibrium It is. i ₂ ,
The current due to hole injection from the base side to the emitter can be ignored because the impurity concentration of the emitter is sufficiently higher than that of the base.

The equation shown above is an approximation of a stepwise junction, and the actual device deviates from the stepwise junction, and the base is thin and has a complicated concentration distribution, so it is not exact. , the refresh operation can be explained with a fair approximation.

Of the current i ₁ flowing between the base and the collector in the above equation, q·Dp· _poe /Lp indicates a current due to holes, that is, a component in which holes flow from the base to the collector side. In order to facilitate the flow of current due to these holes, in the optical sensor cell having the above configuration, the impurity concentration of the collector is designed to be slightly lower than that of a normal bipolar transistor.

FIG. 20 shows an example of the time dependence of the base potential calculated using this formula. The horizontal axis shows the passage of time from the moment the refresh voltage V _RH was applied to the electrode 9, that is, the refresh time, and the vertical axis shows the base potential. In addition, the initial potential of the base is used as a parameter. The initial potential of the base is the potential exhibited by the floating base at the moment the refresh voltage V _RH is applied, and V _RH , Cox,
It depends on Cbe, Cbc and the charge stored in the base.

Looking at FIG. 20, the potential of the base always falls along a straight line on the semi-logarithmic graph after a certain period of time, regardless of the initial potential.

FIG. 20b shows experimental values of base potential change with respect to refresh time. Compared to the calculation example shown in Figure 20a, the test device used in this experiment has a much larger dimension, so although the absolute value does not match the calculation example, the base potential change with respect to the refresh time is semi-logarithmic. It has been demonstrated that it changes linearly on the graph.
This experimental example shows the value when both the collector and emitter are grounded.

Now, set the maximum value of the accumulated voltage V _P due to light irradiation to 0.4
[V], and the voltage V applied to the base by the refresh voltage V _RH is 0.4 [V], as shown in Fig. 20, the maximum value of the initial base potential is 0.8 [V], and after the refresh voltage is applied, the voltage V is ^0.4 [V]. After [sec], the base potential begins to fall in a straight line and becomes 10 ^-5
After [sec], the potential change coincides with that when no light was applied, that is, when the initial base potential was 0.4 [V].

There are two ways in which the p region 6 can be charged to a negative potential by applying a positive voltage for a certain period of time through the MOS capacitor Cox and removing the positive voltage. One is an operation in which holes with positive charges flow from p region 6 to n region 1 which is mainly in a grounded state, thereby accumulating negative charges.
In order to prevent holes from flowing unilaterally from p-region 6 to n-region 1 and to prevent electrons from n-region 1 from flowing into p-region 6 too much, the impurity density of p-region 6 must be set to the impurity density of n-region 1. It should be higher. On the other hand, electrons from n ⁺ region 7 and n region 1 are
By flowing into the p region 6 and recombining with holes, negative charges can also be accumulated in the p region 6. In this case, the impurity density of n region 1 is higher than that of p region 6. The operation of accumulating negative charges due to holes flowing out from p-region 6 is much faster than the operation of accumulating negative charges due to electrons flowing into the base of p-region 6 and recombining with holes. However, according to experiments conducted so far, it has been confirmed that even the refresh operation in which electrons flow into the p region 6 exhibits a sufficiently fast time response for the operation of the photoelectric conversion device.

When a photoelectric conversion device is constructed by arranging a large number of optical sensor cells having the above configuration in the XY direction, the image shows that the accumulated voltage V _P of each sensor cell varies between 0 and 0.4 [V] in the above example. , 10 ^-5 [sec] after applying the refresh voltage V _RH , a constant voltage of approximately 0.3 [V] remains at the base of all sensor cells, but all changes in the accumulated voltage V _P due to the image disappear. I understand that. That is, in the photoelectric conversion device using optical sensor cells according to the above configuration, there is a complete refresh mode in which the base potential of all sensor cells is brought to zero volts by a refresh operation (in this case, in the example of FIG. 20a, 10 [sec]). There are two modes: 1) and a transient refresh mode in which a certain constant voltage remains at the base potential but the fluctuation component due to the accumulated voltage V _P disappears (in this case, in the example of Fig. 20a, 10 [μsec] ~ 10 [sec] refresh pulse). In the above example, the voltage V _A applied to the base by the refresh voltage V _RH was set to 0.4 [V], but if this voltage V _A is set to 0.6 [V], the above transient refresh mode According to Figure 20,
It occurs in 1 [ns] and can be refreshed extremely quickly. The choice of whether to operate in the complete refresh mode or the transient refresh mode is determined by the purpose of use of the photoelectric conversion device.

If the voltage remaining at the base in this transient refresh mode is V _K , then the refresh voltage V _RH
In the transient state at the moment when V _RH is returned to zero volts after applying , a negative voltage of -Cox/Cox+Cbe+Cbc・V _RH is added to the base, so the base potential after the refresh operation by the refresh pulse is V _K -Cox /Cox + Cbe + Cbc・V _RH , and the base becomes reverse biased with respect to the emitter.

It was explained earlier that during the accumulation operation of accumulating carriers excited by light, the base is in a reverse bias state in the accumulation state, but this refresh operation brings the refresh and base to a reverse bias state. These two operations are performed simultaneously.

FIG. 20c shows experimental values of changes in the base potential V _K −Cox/Cox+Cbe+Cbc·V _RH after the refresh operation with respect to the refresh voltage V _RH . The parameter Cox value is set from 5pF to 100pF. The circles are experimental values, and the solid lines are calculated values calculated from V _K −Cox/Cox+Cbe+Cbc·V _RH . At this time
V _K =0.52V, and Cbc+Cbe=4pF. However, the probe capacity of the observation oscilloscope
13pF is connected in parallel to Cbc + Cbe. In this way, the calculated values and experimental values are in complete agreement, and the refresh operation has been experimentally confirmed.

In the above refresh operation, an example has been described in which the collector is grounded as shown in FIG. 16, but it is also possible to perform the refresh operation with the collector at a positive potential. At this time, even if a refresh pulse is applied to the base-collector junction diode Dbc18, if the positive potential applied to the collector is higher than the potential applied to the base by this refresh pulse, it will not work. Since it remains conductive, current flows only through the base-emitter junction diode Dbe16. For this reason, the base potential drops relatively more slowly than when the collector is grounded, but basically the same high-speed refresh operation as explained earlier is performed. be.

In other words, the relationship between the base potential and the refresh time in FIG. 20a is such that the diagonal straight line when the base potential decreases in FIG. 20a is on the right side, that is,
This will result in a shift to a direction that requires more time.
Therefore, if you use the same refresh voltage V _RH as when the collector is grounded, it will take time to refresh, but if you slightly increase the refresh voltage V _RH , you can achieve a high-speed refresh just like when the collector is grounded. Operation is possible.

The above is an explanation of the basic operations of the photosensor cell according to the above configuration, which consists of a charge accumulation operation, a readout operation, and a refresh operation by light incidence.

As explained above, the basic structure of the optical sensor cell according to the above configuration is
Publication No. 150878, Japanese Patent Publication No. 56-157073, Japanese Patent Publication No. 157073, Japanese Patent Publication No. 157073
Compared to Publication No. 56-165473, it has an extremely simple structure and is fully compatible with future higher resolutions, and its excellent characteristics include low noise, high output, wide dynamic range, and a wide dynamic range due to the amplification function.
Advantages such as non-destructive readout are preserved.

Next, a configuration example of the photoelectric conversion device of the present invention, which is configured by two-dimensionally arranging the optical sensor cells according to the configuration described above, will be described with reference to the drawings. FIG. 14 shows a circuit configuration diagram of a photoelectric conversion device in which basic optical sensor cell structures are two-dimensionally arranged in a 3×3 arrangement.

The basic photosensor cell 30 surrounded by the dotted line already described (this time indicates that the collector of the bipolar transistor is connected to the substrate and the substrate electrode), and the horizontal line 31 for applying read pulses and refresh pulses. ,31',3
1'', vertical shift register 32 for generating read pulses, buffer MOS between vertical shift register 32 and horizontal lines 31, 31', 31''
Terminal 34 for applying pulses to the gates of transistors 33, 33', 33'', buffer MOS transistors 35, 35', 35'' for applying refresh pulses, and terminals for applying pulses to their gates. 36, a terminal 37 for applying a refresh pulse, a vertical line 38, 3 for reading out the stored voltage from the basic photosensor cell 30;
8', 38'', horizontal shift register 39 that generates pulses for selecting each vertical line, gate MOS transistors 40, 40', 40'' for opening and closing each vertical line, and reading the accumulated voltage to the amplifier section. An output line 41 for outputting the output, and an output line 41 for refreshing the charge accumulated in the output line after reading.
MOS transistor 42, MOS transistor 42
Terminal 4 for applying refresh pulse
3. Bipolar for amplifying the output signal,
Transistors 44 such as MOS, FET, J-FET,
A load resistor 45, a terminal 46 for connecting the transistor and the power supply, an output terminal 47 of the transistor, and vertical lines 40, 40', 4 in the read operation.
0″ to refresh the charge accumulated in
MOS transistors 48, 48', 48'', and
This photoelectric conversion device is constituted by a terminal 49 for applying a pulse to the gates of MOS transistors 48, 48', 48''.

The operation of this photoelectric conversion device will be explained using the pulse timing diagrams shown in FIG. 14 and FIG. 21a. In FIG. 21a, a section 61 corresponds to a refresh operation, a section 62 corresponds to an accumulation operation, and a section 63 corresponds to a read operation.

At time _t1 , the substrate potential, ie, the collector potential 64 of the photosensor cell portion, is kept at the ground potential or positive potential, and FIG. 21a shows it kept at the ground potential. Regardless of whether the ground potential or the positive potential is applied, as already explained, the only difference is the time required for refreshing, and there is no change in the basic operation. Potential 65 of terminal 49
is in a high state, and the MOS transistors 48, 4
8', 48'' are kept conductive and each photosensor cell is grounded through a vertical line 38, 38', 38''. In addition, a voltage is applied to the terminal 36 that makes the buffer MOS transistor conductive as shown by a waveform 66, and the buffer MOS transistors 35, 35', and 35'' for refreshing the entire screen at once are in a conductive state.In this state, the terminal When a pulse is applied to 37 as shown in waveform 67, a voltage is applied to the base of each photosensor cell through the horizontal lines 31, 31', 31'', and as explained above, a refresh operation is entered and the previously accumulated data is The charged charges are refreshed according to the complete refresh mode or the transient refresh mode. The pulse width of the waveform 67 determines whether the mode is a complete refresh mode or a transient refresh mode.

At time _t2 , as already explained, the base of the transistor of each photosensor cell is reverse biased with respect to the emitter, and the next accumulation period 62
Move to. In this refresh section 61,
As shown in the figure, all other applied pulses are kept low.

In the accumulation operation section 62, the substrate voltage, that is, the collector potential waveform 64 of the transistor is set to a positive potential. This allows electrons among electron-hole pairs generated by light irradiation to flow quickly toward the collector side. However, keeping the collector potential at a positive potential is not an essential condition because the base is biased in the reverse direction with respect to the emitter, that is, the image is taken with a negative potential, and even if it is kept at ground potential or a slightly negative potential, it is basic. There is no change in the storage behavior.

In the storage operation state, the potential 65 of the gate terminal 49 of the MOS transistors 48, 48', 48''
is kept high, similar to the refresh interval, and each
The MOS transistor remains conductive. Therefore, the emitter of each photosensor cell is placed on the vertical line 3.
8, 38', and 38''. When holes are accumulated in the base due to strong light irradiation and the base becomes saturated, that is, the base potential becomes forward biased with respect to the emitter potential (ground potential). As you get older, the holes become vertical lines 38, 38',
38", where the base potential change stops and becomes clipped. Therefore,
Even if the emitters of vertically adjacent optical sensor cells are commonly connected by the vertical lines 38, 38', 38'', the vertical lines 38, 38', 38''
If 38'' is grounded, no blooming phenomenon will occur.

The way to avoid this blooming phenomenon is to
Even if the transistors 48, 48', 48'' are in a non-conductive state and the vertical lines 38, 38', 38'' are in a floating state, the substrate potential, that is, the collector potential 64, is kept at a slight potential to prevent hole accumulation. When the base potential changes towards positive potential due to
This can also be achieved by allowing the flow to flow toward the collector side before the emitter.

Following the accumulation section 62, a readout section 63 begins at time _t3 . At this time _t3 , the potential 65 of the gate terminal 49 of the MOS transistors 48, 48', 48'' is set to low, and the horizontal lines 31, 31',
31″ buffer MOS transistors 33, 33′,
The potential 68 of the gate terminal 33'' is set high to bring each MOS transistor into a conductive state.However, it is not an essential condition that the potential 68 of the gate terminal 34 is set high at time _t3 . It would be better if the time was earlier than that.

At time _t4 , among the outputs of the vertical shift register 32, those connected to the horizontal line 31 have waveform 6.
Since the MOS transistor 33 is in a conductive state at this time, each of the three photosensor cells connected to this horizontal line 31 is read out. This readout operation is as described above, and the signal voltage generated by the signal charge accumulated in the base region of each photosensor cell appears as it is on the vertical lines 38, 38', 38''. As shown in FIG. 19, the pulse width of the pulse voltage from the shift register 32 is set to a pulse width that maintains a sufficient linearity between the read voltage and the accumulated voltage. As shown above, the emitter is adjusted to be forward biased by V _Bias .

Next, at time _t5 , among the outputs of the horizontal shift register 39, the one connected to the vertical line 38
Only the output to the gate of the MOS transistor 40 becomes high as shown in the waveform 70, the MOS transistor 40 becomes conductive, and the output signal passes through the output line 41, enters the output transistor 44, is current amplified, and is output from the output terminal 47. . After the signal is read out in this way, signal charges due to the wiring capacitance remain in the output line 41, so at time _t6 , a pulse as shown in pulse waveform 71 is applied to the gate terminal 43 of the MOS transistor 42. , the MOS transistor 42 is turned on and the output line 41 is grounded to refresh the remaining signal charge. Similarly, the switching MOS transistors 40, 4
0', 40'' are connected in sequence to form vertical lines 38, 3.
8', 38'' is read out. After reading out the signals from each horizontally arranged line of photosensor cells in this way, the signals from the vertical lines 38, 38', 3
Similar to the output line 41, signal charges due to the wiring capacitance of the output line 8'' remain, so the MOS connected to each vertical line 38, 38', 38''
Transistors 48, 48', and 48'' are turned on by having their gate terminals 49 high, as shown by waveform 65, to refresh this residual signal charge.

Next, at time _t8 , among the outputs of the vertical shift register 32, the output connected to the horizontal line 31' becomes high as shown by waveform 69', and the accumulated voltage of each photosensor cell connected to the horizontal line 31' becomes The signals are read out to each vertical line 38, 38', 38''. Thereafter, signals are sequentially read out from the output terminal 47 by the same operation as before.

In the above explanation, the operating conditions applied to application fields where the storage section 62 and the readout section 63 are clearly separated, such as still videos, for which research and development have been actively conducted recently, have been explained. The present invention can also be applied to applications such as cameras where the operation in the storage section 62 and the operation in the readout section 63 are performed simultaneously by changing the pulse timing shown in FIG. 21. However, the refresh at this time is not a one-time refresh of the entire screen, but requires a refresh function for each line. For example, after the signals of each photosensor cell connected to the horizontal line ₃₁ are read out, the MOS transistors 48, 48',
48'' is made conductive, but at this time horizontal line 31
Apply a refresh pulse to. That is, in the waveform 69, at time t ₇ as well as at time t ₄ ,
This can be achieved by using a vertical shift register configured to generate pulses with different pulse voltages and pulse widths. In this way, in addition to double-pulse operation, instead of the device that applies the batch refresh pulse installed on the right side of Figure 14, a second vertical shift register similar to the one on the left side is installed on the right side, and the timing is shifted to the left side. This can also be achieved by operating with offset from the vertical register provided.

At this time, in the accumulation state as described above, the degree of freedom in controlling the blooming by controlling the potentials of the emitter and collector of each photosensor cell is reduced. However, as explained in the basic operation section, in the read state, the base
Since the configuration is such that high-speed reading is possible when a bias voltage of V _Bias is applied, as can be seen from the graph in Figure 18, when V _Bias is not applied, the vertical line 2
The signal charges flowing out to the terminals 8, 28', and 28'' are extremely small, and the blooming phenomenon does not pose a problem at all.

Moreover, the photoelectric conversion device according to this configuration example can obtain extremely excellent characteristics with respect to the smear phenomenon. The smear phenomenon is an operational and structural problem that occurs in CCD type imaging devices, especially frame transfer type, in which charge is transferred to the area irradiated with light. This problem occurs because carriers generated deep in the semiconductor due to light are accumulated in the charge transfer section.

Furthermore, in MOS type imaging devices, this problem arises because carriers generated deep in the semiconductor due to long wavelength light are accumulated on the drain side of the switching MOS transistor grounded in each photosensor cell.

On the other hand, in the photoelectric conversion device according to this configuration example, the smear phenomenon that occurs due to its operation and structure is unlikely to occur, and the phenomenon that carriers generated deep in the semiconductor due to long wavelength light are accumulated does not occur. . However, there is a concern that the electrons and holes generated relatively near the surface of the emitter of the optical sensor cell will accumulate, but this is because the emitter is grounded in the accumulation operation state during the bulk refresh operation. Therefore, electrons are not accumulated,
No smear phenomenon occurs. In addition, during the line refresh operation applied to ordinary television cameras, during the horizontal blanking period, the vertical line is grounded and refreshed before reading out the accumulated voltage on the vertical line, so at the same time the emitter The electrons accumulated during one horizontal scanning period flow out, and therefore almost no smear phenomenon occurs. As described above, in the photoelectric conversion device according to the present example, the smear phenomenon occurs to an essentially negligible extent due to its structure and operation, which is one of the major advantages of the photoelectric conversion device according to the optical configuration example. It is one.

Furthermore, while the operation of suppressing the blooming phenomenon by manipulating the emitter and collector potentials in the storage operation state has been described above, it is also possible to use this to control the γ characteristics.

In other words, during the storage operation, the potential of the emitter or collector is temporarily set to a certain negative potential, and of the carriers accumulated in the base, the holes that are accumulated in a greater number than the number of carriers that give this negative potential are transferred to the emitter or collector. It causes the flow to flow to the collector side. As a result, the relationship between the accumulated voltage and the amount of incident light exhibits the γ=1 characteristic of silicon crystal when the amount of incident light is small.
In a place where the amount of incident light is large, γ becomes smaller than 1. In other words, it is possible to provide the characteristic of γ=0.45, which is normally required for television cameras, using polygonal line approximation. If the above operation is performed once during the storage operation, it becomes a one-fold line approximation, and if the negative potential applied to the emitter or collector is changed twice as appropriate, it is also possible to have a two-fold line type γ characteristic.

Further, in the above configuration example, the silicon substrate is used as a common collector, but a buried n ⁺ region may be provided like a normal bipolar transistor, and the collector may be divided for each line.

In addition, in the actual operation, in addition to the pulse timing shown in FIG. 21a, the vertical shift register 32,
A clock pulse is required to drive the horizontal shift register 39.

FIG. 22 shows an equivalent circuit related to the output signal.

Capacity C _V 80 is vertical line 38, 38', 38''
The capacitance C _H 81 is the wiring capacitance of the output line 4.
The wiring capacitance of 1 is shown respectively. The equivalent circuit on the right side of FIG. 9 is in the read state, and includes the switching MOS transistors 40, 4.
0' and 40'' are in a conductive state, and the resistance value in the conductive state is shown by a resistor R _M 82. Also, the amplifying transistor 44 is shown by an equivalent circuit using a resistor r _e 83 and a current source 84. The MOS transistor 42 for refreshing the charge accumulation caused by the wiring capacitance of the output line 41 is non-conductive in the read state and has high impedance, so it is omitted in the equivalent circuit on the right side.

Each parameter of the equivalent circuit is determined by the size of the photoelectric conversion device actually constructed. For example, the capacitance C _V 80 is about 4 pF, and the capacitance C _H 81
The 23rd example shows an example in which the output signal waveform observed at the output terminal 47 is calculated, assuming that the conduction state resistance R _M 82 of the MOS transistor is about 3KΩ, and the current amplification factor β of the bipolar transistor 44 is about 100. As shown in the figure.

In FIG. 23, the horizontal axis represents the time [μs] from the moment the switching MOS transistors 40, 40', 40'' became conductive, and the vertical axis represents the time from the moment when the switching MOS transistors 40, 40', 40'' became conductive.
The output voltage [V] appearing at the output terminal 47 when a signal charge is read from each photosensor cell and a voltage of 1 volt is applied to the wiring capacitance C _V 80 of 8' and 38'' is shown, respectively.

The output signal waveform 85 shows that the load resistance R _E 45 is 10KΩ,
86 is load resistance R _E 45 is 5KΩ, 87 is load resistance
This is when R _E 45 is 2KΩ, and in both cases, the peak value is about 0.5V due to capacitance division between C _V 80 and _CH 81. Naturally, the larger the load resistance R _E 45 is, the smaller the amount of attenuation is, resulting in a desirable output waveform. The rise time is approximately 20nsec when the above parameter values are used.
And it is fast. Resistance R _M of switching MOS transistors 40, 40', 40'' in conduction state
By reducing the wiring capacitance C _V ,
By reducing _CH , even faster reading is possible.

In a photoelectric conversion device using photosensor cells with the above configuration, the voltage appearing at the output is large due to the amplification function of each photosensor cell, so the final stage amplification amplifier is also quite simple compared to a MOS type imaging device. But that's fine. In the above example, a one-stage bipolar transistor type was used, but it is of course possible to use other systems, such as a two-stage structure. When using bipolar transistors as in this example,
The problem of 1/f noise that is easily noticeable on images generated from the MOS transistor of the final stage amplifier in a CCD imaging device does not occur in the photoelectric conversion device of this configuration example, and image quality with an extremely good S/N ratio can be obtained. is possible.

A photoelectric conversion device of the present invention having even higher sensitivity than the embodiment shown in FIG. 17 having a negative control electrode will be described below with reference to the drawings.

FIG. 1 shows one embodiment. Figure 1a shows a part of a plan view when a large number of basic photosensor cells having a plurality of control electrodes are two-dimensionally arranged, and Figure 1b shows a cross-sectional view taken along the line A-A' in Figure 1a. , 1st
Figure c shows the circuit configuration of the basic photosensor cell, and Figure 1 d
1A and 1B respectively show examples of internal potential states in the BB' cross-sectional direction in FIG. 1B.

In the embodiment shown in FIG.
A high-resistance n ^- region 5, a p region 6, and an n ⁺ region 7 are formed on the phototransistor of an n ⁺ pn ^- n structure, but in the embodiment shown in FIG.
They are configured on the p ⁺ substrate 350, and
The difference is that the n region of the substrate in the embodiment shown in the figure is now an n ⁺ region 351.

In the ^embodiment shown in this FIG.
A first phototransistor consisting of region 6, n ^- region 5, and n ⁺ region 351 has p region 6, n ^-
A second phototransistor made up of region 5, n ⁺ region 351, and p ⁺ region 350 is formed overlappingly to form a thyristor structure. For this reason,
When the horizontal axis represents the direction from the semiconductor surface to the inside, the internal potential state for ^electrons is as shown in FIG. When light is incident while it is biased to a potential,
Among the carriers generated inside the semiconductor due to optical excitation, holes are as explained in the example of FIG.
It is accumulated in the p ⁺ region, ie the base region 6, of the first phototransistor. At this time, in the previous example, the electrons are in the n ^- region 5, which is a high resistance region.
It was accelerated by the electric field generated in the collector and started flowing to the collector substrate 1.
In the embodiment shown, there is a potential well for electrons in front of the substrate p ⁺ region 350.
There are n ⁺ regions. In other words, this n ⁺ area is the second
This is the base region of the phototransistor.
Electrons generated by photoexcitation are accumulated here.

In a CCD type image sensor or a MOS type image sensor, electrons among carriers generated by photoexcitation are accumulated in the main electrode, and in the embodiment shown in Fig. 13, holes are accumulated in the control electrode area. In this way, only one carrier of the electron-hole pair generated by photoexcitation was used, but in the embodiment shown in FIG.
High sensitivity is achieved by accumulating holes in the control electrode region of the second phototransistor and electrons in the control electrode region of the second phototransistor, and utilizing both carriers generated by photoexcitation. The detailed operation will be described later.

The basic sensor cell shown in FIG. 1 differs from the embodiment shown in FIG. 17 in that a pMOS transistor for refresh is further added to each photosensor cell. That is, the pMOS transistor is composed of the base region 6 of the first phototransistor, the channel-doped n region 353, the newly formed p region 354, the gate insulating film 3, and the gate electrode 352. It is sometimes brought into a conductive state and acts to pull out holes accumulated in the base region 6. Wiring 355
is connected to the p region 354, which is the drain region of this pMOS transistor, through a contact hole 359,
It is for connecting to negative power supply. Furthermore, the gate electrode 352 extends widely over the base region 6 and constitutes a MOS capacitor there, and as shown in the embodiment of FIG. It's summery.

Base region 351 of second phototransistor
is exposed to the semiconductor surface in contact with the element isolation region 4, and a MOS capacitor is formed on this base region 351 by the insulating film 3 and the electrode 356, similar to the base region of the first phototransistor.
The potential of the base region of the second phototransistor is also changed via this MOS capacitor. The wiring 357 is for supplying pulses to this MOS capacitor electrode,
Further, the wiring 358 is for supplying pulses to the gate and MOS capacitor.

The emitter region 7 and wiring 8 of the first phototransistor are exactly the same as in the embodiment of FIG.

FIG. 1c is a circuit diagram of the optical sensor cell described above. Transistor 360 includes n ⁺ region 7,
A first phototransistor consisting of a p region 6, an n ⁻ region 5, and an n ⁺ region 351 is connected to a transistor 361.
is a second phototransistor consisting of a p region 6, an n ⁻ region 5, an n ⁺ region 351, and a p ⁺ region 350,
MOS transistor 362 is a p-channel MOS transistor consisting of p region 6, n region 353, p region 354, gate insulating film 3, and gate electrode 352, and capacitor 363 is a MOS transistor consisting of p region 6, insulating film 3, and electrode 352. The capacitor 364 includes an n ⁺ region 351, an insulating film 3,
MOS capacitors each consisting of an electrode 356 are shown.

Below, the operation of this basic photosensor cell will be explained as follows.
This will be explained in detail using the circuit configuration diagram shown in the figure in which optical sensor cells are arranged two-dimensionally, and the pulse waveform and internal potential diagram shown in FIG.

Figure 2 shows a 2x2 array of the basic photosensor cells shown in Figure 1c, which includes a vertical shift register, optical shift register, output amplifier, vertical line refresh MOS transistor, and vertical line selection. MOS transistors etc. for
As in the figure, it is added around this area, but is omitted in the figure. As already explained, the gates of the MOS capacitor 363 and the pMOS transistor 362 are connected in common and are configured to apply a pulse via the horizontal line 358, but this can be applied by providing separate wiring. is also possible. In FIG. 3, waveform A is a pulse waveform applied to horizontal line 357, and waveform B is a pulse waveform applied to horizontal line 357.
58. This is the pulse waveform applied to 58. Waveform C is a waveform showing the potential of vertical line 8, and up to time _t4 , although not shown in the diagram, it was connected to the vertical line.
The MOS transistor is turned on and kept at the ground potential, and from time _t4 onwards, the MOS transistor is placed in a floating state, indicating that a signal is output from the emitter region of each photosensor cell. However, in the configuration shown in FIG. 1, grounding the emitter region of each sensor cell until time _t4 is not an essential condition because the pMOS transistor 362 is used for refreshing. There's nothing inconvenient about it.

The operation will be explained below at each time using pulse waveforms and internal potential diagrams. At this time, it is assumed that the emitter region of the second phototransistor is connected to the positive power source through the electrode 12 on the back surface of the substrate. Among the pulse waveforms in Figure 3, time t ₁
to time _t3 corresponds to a refresh operation, from time _t3 to time _t4 corresponds to an accumulation operation of optically excited carriers, and from time _t4 to time _t8 corresponds to a readout operation.

Time t ₁ is the point at which the read operation ends, and as shown in the diagram at time t ₁ of the internal potential, p
Holes are accumulated in the region, that is, the first base region, in accordance with the intensity of light, and electrons are accumulated in the n ⁺ region, that is, the second base region, in accordance with the intensity of light. At time _t2 , as shown in waveform B, a negative pulse is applied to the gate of the refresh pMOS transistor 362 through the horizontal line 358, making the pMOS transistor conductive. Therefore, the holes accumulated in the first base region begin to flow, and as shown in the internal potential diagram at time _t2 , the first base region is applied to the negative voltage supplied via the wiring 355. . At this time, a negative pulse is simultaneously supplied to the first base region via the MOS capacitor 363, but since the pMOS transistor 362 is in a conductive state, it does not have any effect.

At time _t2 , a refresh pulse is applied to the base region of the second phototransistor via the horizontal line 357 and the MOS capacitor 364 as shown in waveform A. The relationship between the voltage applied at this time, the voltage applied to the second base region, and the refresh operation are exactly the same as those already explained as the refresh operation in the embodiment of FIG. 17. That is, as shown in the internal potential diagram at time _t2 , when the pulse is applied and the base region 351 is forward biased with respect to the emitter region 350,
As time goes on, it will gradually become built-in voltage as shown by the arrow. however,
In this second phototransistor, the junction area between the base region 351 and the emitter region 350 of the second phototransistor is extremely large, as shown in the cross-sectional view of FIG. 1b. The refresh operation is performed faster than when .

Then, when the voltage applied to the second base region returns to ground potential, the potential of the second base region is reverse biased with respect to the emitter region. This is also exactly the same as the refresh operation already explained.

The period from time t ₃ to time t ₄ is the accumulation period of carriers generated by photoexcitation. As already explained, of the carriers generated by photoexcitation, holes are accumulated in the base region of the first phototransistor, and electrons are accumulated in the base region of the first phototransistor. It is stored in the base region of the second phototransistor. The amount of charge accumulated in both at this time is, if we ignore the electrons that escape to the emitter region of the first phototransistor, and the electrons that disappear due to recombination when traveling through the normal resistance region, which is small, and so on. Approximately equal amounts will be accumulated in each base region. Also, the accumulated voltage generated in each base region at this time is determined by the base-emitter capacitance of each phototransistor and the base-emitter capacitance of each phototransistor.
The fact that the accumulated charge amount is divided by the sum of the inter-collector capacitances is equivalent to that already explained in the embodiment shown in FIG. In this way, in the optical sensor cell shown in Figure 1, there are multiple base regions that are control electrodes, but there are two types of base regions: one where there is only one, and the other where there is a difference between electrons and holes, but they can be considered independently. is possible.

The internal potential diagram at time _t4 shows a state in which carriers due to optical excitation are accumulated in each base region. At time _t4 , as shown in waveform C, the emitter region of the first phototransistor is brought into a floating state, and the next signal is read out.

First, at time _t5 , as shown in waveform A, a pulse is applied to the base of the second phototransistor via the horizontal line 357 and the MOS capacitor 364, so that the forward direction as shown in the internal potential diagram at time _t5 Holes are injected from the emitter region of the second phototransistor into the base region of the first phototransistor as shown by the arrow in proportion to the voltage biased and accumulated according to the light intensity. As a result, holes proportional to the electrons accumulated in the second base region are added to the holes generated by photoexcitation into the first base region, and are injected from the emitter region of the second phototransistor. Since the number of holes depends on the time that the second base region is forward biased, it is now possible to control the desired gain. Further, the amount and time of forward bias of the second base at this time are controlled to optimal values in order to ensure linearity of the number of holes injected. The concept at this time is exactly the same as that already explained in the embodiment shown in FIG. At time t ₆ , the voltage applied to the second base has returned to its original state, and as shown in the internal potential diagram at time t ₆ , the second base region is at the voltage applied to the second base before the pulse is applied. The state returns to the reverse bias state for the emitter No. 2, and hole injection stops here.

At time _t7 , as shown in waveform B, a voltage is applied across horizontal line 358 and MOS capacitor 363, forward biasing the first base region with respect to the first emitter. This pulse waveform is a positive pulse, and the MOS capacitor 3
A voltage is also applied to the gate electrode of the pMOS transistor connected in parallel with 63, but since the voltage is positive, the pMOS transistor does not become conductive and no untoward operation occurs.

When the first base region is forward biased, the first emitter region is in a floating state, so electrons are injected from here, the potential of the emitter region changes, and they are accumulated in the first base region. The resulting signal voltage will be read out. This operation is exactly the same as that described in the embodiment shown in FIG. However, in the embodiment shown in FIG. 1, electrons injected from the first emitter region are accumulated in the second base region, and if this amount of charge is large, thyristor operation occurs partially, and the gain is further reduced. This phenomenon causes the signal output to become non-linear, so
Each bias condition etc. is set so that thyristor operation does not occur. Particularly for applications that do not require linearity, it is desirable to increase gain through this thyristor operation.

At time _t8 when reading is completed, the voltage applied to the first base region via the MOS capacitor 364 is removed, so as shown in the internal potential diagram at time _t8 , the first base region is 1
The emitter region returns to the same reverse bias state as before the pulse application, and injection of electrons from the emitter region stops. In this state, each signal output is read out on a vertical line,
After that, as explained using FIG. 14, the horizontal shift register starts operating, each vertical line is selected, and a signal is outputted to the outside through the output amplifier. In the structure shown in Figure 1, the time
When injecting holes into the first base at t ₅ , since the p region 354 of the pMOS transistor is connected to the negative power supply, some of the holes are
A phenomenon occurs in which the region is injected. This p region 35
If 4 is formed small, this amount will not be so large, but in order to further reduce this amount, this pMOS transistor can be formed on the element isolation region using SOI (Silicon On Insulator) technology. This can be solved by Further, the pulse voltage values of waveform A and waveform B are each set to the optimum value in the refresh operation read operation, as explained in the embodiment of FIG.

As explained above, in the embodiment shown in FIG. 1, carriers of both electrons and holes generated by photoexcitation are accumulated in a plurality of control electrode regions and read out from each while increasing the gain. Therefore, a photoelectric conversion device with extremely high sensitivity can be provided.

FIG. 4 shows another embodiment of the structure shown in FIG. 1 having a plurality of control electrode regions. In the embodiment shown in FIG. 1, the base region of the first phototransistor is refreshed using a pMOS transistor, but in the embodiment shown in FIG. 4, the base region of the second phototransistor is refreshed using a pMOS transistor. It is configured to be refreshed. FIG. 4a shows a part of a plan view of a two-dimensional arrangement of basic photosensor cells, and FIG. 4b shows a cross-sectional view of the interior of the semiconductor taken along the line A-A' in FIG. 4a.
FIG. 4c shows the equivalent circuit of the basic photosensor cell.

In Figure 4, the nMOS transistor is SOI
Amorphous silicon formed by sputtering or the like on the element isolation region 4 using technology, or a silicon substrate in which polysilicon deposited by CVD is recrystallized by laser beam annealing, electron beam annealing, etc. formed inside. This nMOS transistor has an n ⁺ region 365,
and n ⁺ region 367, channel doped p region 366, gate insulating film 3, gate electrode 36
8, and the n ⁺ area 365 is the second
is connected to the n ⁺ region 351, which is the base region of the phototransistor, and the other n ⁺ region 367
is connected to the wiring 370 through a contact hole 371, and is configured to be supplied with a positive voltage from a positive voltage power source. Furthermore, the gate electrode 368 is also located above the n ⁺ region 365, and this portion
It constitutes a MOS capacitor. A pulse is applied to this gate electrode 368 via a horizontal line 370.

A MOS capacitor consisting of an insulating film 3 and a base region 6, an electrode for applying a pulse voltage to the base region during refreshing of the base region of the first phototransistor and reading, an emitter region 7 of the first phototransistor; A vertical line 8 from which signals are taken out, and a contact hole 1 for connecting the vertical line and the emitter region 7.
9, etc. are equivalent to those shown in FIG. 17 or FIG.

Although not shown in the figure, the p region, i.e.
The channel region 366 of the nMOS transistor is n ⁺
region, that is, the source region 365.

FIG. 4c shows an equivalent circuit of a basic photosensor cell, with n ⁺ region 7, p region 6, n ^- region 5, and n ⁺ region 3.
A first phototransistor 372 consisting of 51,
p region 6, n ^- region 5, n ⁺ region 351, p ⁺ region 3
a second phototransistor 373 consisting of 50;
MOS capacitor 374 consisting of electrode 9, insulating film 3, p region 6, electrode 368, insulating film 3, MOS capacitor 375 consisting of n ⁺ region 365, n ⁺ region 365, p region 366, n ⁺ region 367, gate insulating film 3 and an n ^- MOS transistor 376 consisting of a gate electrode 368.

FIG. 5 is a circuit configuration diagram of the basic photosensor cells shown in FIG. Line selection MOS transistors and the like are added around the configuration diagram shown in FIG. 5, but these are basically the same as those shown in FIG. 14, and are omitted in this diagram. The operation of this basic optical sensor cell and the operation of the photoelectric conversion device shown in FIG. 5 will be explained in detail below using the pulse waveform and internal potential diagram shown in FIG. 6.

In FIG. 6, waveform A is a pulse waveform applied to horizontal line 370, and waveform B is a pulse waveform applied to horizontal line 10. Waveform C is a waveform showing the potential of the vertical line 8, and until time _t5 , a MOS transistor connected to the vertical line (not shown in the figure) for refreshing the charge on the vertical line is in a conductive state. done,
It is shown that the ground potential is maintained, and from time _t5 onwards, it is in a floating state, and a signal is output from the emitter region of each sensor cell.

Hereinafter, the operation will be explained in order at each time using pulse waveforms and internal potential diagrams. 6th
Of the pulse waveforms shown in the figure, from time t ₁ to t ₄ is used for refresh operation, and from time t ₄ to time t ₅ is used for refresh operation.
The optically excited carrier accumulation operation from time _t5 to time _t8 corresponds to the signal readout operation, respectively. At time _t1 , a negative pulse is applied through the horizontal line 370 as shown in waveform A;
When a negative voltage is applied to the base region of the second phototransistor through the MOS capacitor 375, as shown in the internal potential diagram at time _t1 ,
Since the base region is forward biased with respect to the emitter region of the second phototransistor, holes are injected from the emitter region, causing an operation that changes the potential of the base region of the first phototransistor in a positive direction. do. At this time, the second base potential gradually approaches the built-in voltage from the forward bias state as time passes, which is exactly the same operation as described above. At this point, holes are injected into the first base to change the potential toward a positive potential in order to operate the transient refresh described in the embodiment of FIG. 17 more reliably.

When this negative pulse is applied, the gates of the MOS capacitor 375 and the nMOS transistor 376 are commonly connected, so the nMOS transistor 37
6 is also applied with a negative pulse, but the nMOS transistor does not become conductive and no particular inconvenience occurs.

Then, at time t ₂ , the negative pulse returns to the ground potential, but at the moment when the second base changes from the negative potential to the ground potential, at time t ₂
As shown in the internal potential diagram, the second base becomes reverse biased with respect to the second emitter, and hole injection from the second emitter stops.

At time _t3 , as shown in waveform A, a positive pulse is applied to the gate of the nMOS transistor 376 through the wiring 370, making it conductive, and therefore,
The second base is made equal to the potential of the positive voltage power supply provided by vertical line 369. At this time, a positive pulse is also commonly applied to the MOS capacitor 375, but no particular disadvantageous phenomenon occurs. Also, at time _t3 , as shown in waveform B, wiring 1
0 and a positive voltage is applied to the first base through the MOS capacitor 374. At this time, time t ₃
As shown in the internal potential diagram of change in direction. This is exactly the same operation as when the refresh operation was already explained in the embodiment shown in FIG.
A full refresh mode or a transient refresh mode may be used depending on the application.
At this time, as already explained, since the second base is connected to the positive power supply via the nMOS transistor 376, normal bipolar operation is performed.

At time t ₄ , each pulse returns to ground potential and the first and second bases are reverse biased with respect to their respective emitters, as shown in the internal potential diagram at time t ₄ . The carrier starts accumulating operation.

The period from time t ₄ to time t ₅ is an accumulation period for carriers generated by photoexcitation, in which holes are accumulated in the first base region and electrons are accumulated in the second base region. The operation is exactly the same as that of the embodiment shown in FIG.

The internal potential diagram at time _t5 shows a state in which carriers due to optical excitation are accumulated in each base region. At time _t5 , as shown in waveform C, the emitter region of the first phototransistor is brought into a floating state with the MOS transistor connected to the vertical line rendered non-conductive, and enters the next signal readout state. First, at time t ₆ ,
As shown in waveform A, a negative pulse is applied to the base region of the second phototransistor through the horizontal line 370 and the MOS capacitor 375, so that the _second base The second emitter region is put into a forward bias state, and holes are injected from the second emitter region in proportion to the voltage accumulated according to the light intensity, and enter the first base region as shown by the arrow. , holes other than those generated by optical excitation are accumulated. This is similar to that described in the embodiment of FIG.

At time t ₇ , as shown in waveform A, the horizontal line 37
A positive voltage is applied to the gate of the nMOS transistor 376 through 0, making it conductive. Therefore, the second base is the nMOS transistor 376
Since the first phototransistor is connected to the positive power supply through the vertical line 369, the operation of the first phototransistor is exactly the same as that of the normal bipolar transistor shown in the embodiment of _FIG . The signal readout operation by applying a positive voltage to the first base region through the line 10 and the MOS capacitor 374 is also exactly the same as the embodiment shown in FIG. 17, so a description thereof will be omitted. The internal potential diagram at time _t8 is also the same as the embodiment shown in FIG. 17, so its explanation will be omitted.

As explained above, according to this embodiment, the first
Unlike the embodiment shown in the figure, it is possible to operate like the embodiment shown in Fig. 17 without worrying about the thyristor operation during reading.
Moreover, as in the embodiment shown in FIG. 1, a photoelectric conversion device with extremely high sensitivity can be provided.
Next, in Fig. 7, the pMOS for refresh shown in Fig. 1 is placed in the base region of the first phototransistor.
An equivalent circuit of a basic photosensor cell according to an embodiment in which a transistor is added and a refresh nMOS transistor is added to the base region of the second phototransistor is shown.

The plan view and sectional view shown in FIGS. 1 and 4 are omitted in the embodiment shown in FIG. 7 because the structure is a combination of both. 2 in Figure 8
A diagram showing a circuit configuration arranged in ×2. As before, peripheral circuits are omitted here.

FIG. 9 shows waveforms applied to each line and an internal potential diagram. In FIG. 9, waveform A passes through the horizontal line 377 to the gate of the pMOS capacitor 381 and the MOS capacitor 38.
Waveform B is a pulse waveform applied to the gate of nMOS capacitor 385 and MOS capacitor 386 through horizontal line 378, and waveform C is a pulse waveform applied to vertical line 8 as in the previous embodiment. This is a waveform that indicates the state.

Also, at this time, it is assumed that the vertical line 379 shown in FIG. 8 is connected to the negative power source, and the vertical line 380 is connected to the positive power source.

In the embodiment shown in FIGS. 7 and 8, the read operation from time t ₄ to time t ₆ is exactly the same as the embodiment shown in FIG. 4. The difference from the previous two embodiments is the refresh operation, in which the pMOS transistor 381 and the nMOS transistor 385 are simultaneously turned on at time _t2 , and holes are generated from the first base and electrons are generated from the second base. Each of them flows out, and the refresh operation is completed very easily.

Therefore, in waveform C, the emitter region of the first phototransistor is grounded in the refresh state, but in this refresh operation, it is not necessary to ground it, and any state is fine. it is obvious.

As explained above, the embodiments shown in FIGS. 1, 4, and 7 have two main electrode regions each consisting of an opposite conductivity type region, and two main electrode regions each consisting of an opposite conductivity type region. In an optical sensor cell with a thyristor structure provided adjacent to the main electrode area of each of the two control electrode areas, one of the electron-hole pairs generated by photoexcitation is the first hole.
This system accumulates electrons in the first control electrode region and the second control electrode region, and has a major feature compared to conventional methods that utilize only one of the carriers generated by photoexcitation. We provide highly sensitive photoelectric conversion devices.

In this way, the photoelectric conversion device according to the present invention has two
Double Base Stove has two control electrode areas and accumulates carrier in each.
It is called D-BASIS, an acronym for Image Sensor.

The photoelectric conversion device having the function of amplifying internally optically excited carriers has been described above. So far, we have explained structures in which optically excited carriers are generated within a single crystal, but it is also possible to construct a transistor dedicated to light reception using an amorphous layer on the surface of a readout transistor provided within a single crystal. can. The structure will be described below.

FIG. 10 shows a typical example, in which a is a plan view of a readout transistor provided approximately in a single crystal, b is a cross-sectional view taken along line A-A', and c is an array of such cells. FIG. The plan view of FIG. 10a is basically the same as the plan view shown in FIG. 17a. However, the difference is that a p ⁺ polysilicon region 401, which is to become the collector of a transistor provided for light reception, is provided in the amorphous layer stacked thereon. The p ⁺ polysilicon region 401 is in contact with the p base region of the read transistor through a contact hole 410. In reality, amorphous silicon is deposited on this surface. This situation is shown in figure b. In its operating state, 402 is a high-resistance region that is made to have a low impurity density so as to completely become a depletion layer. Basically, it may be n ^- , p ^- or one area. This is applicable to all the embodiments described so far. The n region 403 and the p ⁺ region 404 are the base region and emitter region of the light receiving transistor. The n base region is kept in a floating state, and its potential is controlled by a MOS capacitor formed of an electrode 407, an insulating layer 406 such as SiO ₂ , and the n base region 404. The impurity concentration of p ⁺ region 404 is usually 1
×10 ²⁰ cm ^-3 or higher. The impurity concentration of the n base region 403 is 1 to 50×
It is set to about 10 ¹⁷ cm ^-3 and is set so as not to punch through in the operating state. The thickness of the high resistance region 402 is determined so as to have a desired light receiving sensitivity spectral distribution. Reference numeral 405 denotes an insulating region for separating the light receiving transistor. It is formed of SiO ₂ , Si ₃ N ₄ , non-doped polysilicon, etc., or a composite layer thereof. 406 is a thin oxide film provided on amorphous silicon. 408 is a PSG film or a CVD SiO ₂ film. 409 is an electrode of the p ⁺ emitter region 404, which is also made of SnO ₂ , In ₂ O ₃ ,
It is a transparent electrode such as InTiO (ITO), and may have a structure that covers the entire surface. 8 and 10 have been considered to be metals mainly composed of Al, but in the embodiment shown in ^FIG . , the wiring material must be able to withstand certain high-temperature processes. Usually high melting point metals such as Mo, W, MoSi ₂ , WSi ₂ , TiSi ₂ or
A material that can withstand high temperatures, such as TaSi ₂ , is chosen. Electrode 4
07 may be Al or a metal mainly composed of Al.
For simplicity, it is assumed that 407 is also the number of the wiring for driving this MOS capacitor.

The circuit configuration diagram of the photoelectric conversion device having the structure shown in FIGS. 10a and 10b is shown in FIG. 10c. The operation of the photoelectric conversion device of the present invention will be explained next. Basically, what has already been explained has been sufficiently described, so I will briefly explain it.

First, the refresh operation will be explained. A negative pulse is applied to the MOS capacitor 407 through the wiring 407. p ⁺ (404) n (403)
The contact is biased in the forward direction by this negative pulse application, and the electrons that have been excessively accumulated in the n-region 403 flow out, and are further charged to a predetermined voltage (positive voltage). At this time, holes simultaneously flow out from the p ⁺ region 404 and flow into the p ⁺ region 401, and as a result, holes accumulate in the p base 6. Next, a positive pulse is applied to wiring 10 to set p base region 6 to a predetermined negative voltage. After this state, the optical sensor cell enters an operation of accumulating optically excited carriers. Holes photoexcited in the amorphous region are
The electrons flow into the p ⁺ region 401, and the electrons flow into the n region 403.
flows into. These carriers are accumulated as optical signals. Next, the read operation begins. First, a negative voltage is applied to the wiring 407, and p ⁺ (4
04) n (403) contact and e.g. 0.5~0.65V
Forward bias. By doing this
With a pulse width of about 1 μsec to 0.1 μsec, holes that are sufficiently excited by the optical signal and proportional to the electron charge accumulated in the n region 403 flow out from the n region 404, causing p ⁺
It flows into region 401. That is, in the p base region 6, not only holes directly excited by light but also holes proportional to photoexcited electrons are accumulated in a superimposed manner. After this internal amplification effect is activated and holes proportional to the optical signal are accumulated in the p-base region, they are passed through the wiring 10 to the MOS capacitor 9.
A positive read voltage is applied to the vertical line 8, and a voltage signal proportional to the optical signal is read out onto the vertical line 8.
We have already given a sufficient explanation of these operations. As already explained, since the voltage to be read out is large, the amplifier can be configured extremely simply, and thus divisional readout can be easily performed. The same positive voltage may be applied to 12 and 409, or different positive voltages may be applied depending on the case.

In FIG. 10, the p base region 6 of the readout transistor and the n base region 4 of the light receiving transistor are shown.
All of 03 were made in a floating state. As already explained, in order to perform the refresh more completely, the p base 6 is used as the main electrode.
It goes without saying that a structure in which a MOS transistor is provided, a structure in which a MOS transistor is provided with the n-base region 403 as the main electrode, or a structure in which both are provided simultaneously can be applied to such a structure in which the readout transistor and isolation transistor are separated. Not even. An example of this is shown in Figure 11,
It is shown in Fig. 2 and Fig. 13. Figure 11 is for refreshing the p-base region of the readout transistor.
This is an example in which a pMOS transistor (drawn on the leftmost side in the cell in the figure) is provided, and one main electrode of this transistor is set to a predetermined negative voltage. Since the refresh pMOS transistors operate by applying a negative voltage to their gates, they can be commonly driven by the horizontal line 10.

Figure 12 shows the n-base 4 of the light-receiving transistor.
The structure is such that an nMOS transistor with 03 as the main electrode is provided to perform refresh. Since the nMOS transistors are refreshed by applying a positive pulse voltage to their gates, the gates can be commonly driven by the horizontal line 407.

One main electrode of the nMOS transistor is set to a predetermined positive voltage (greater than the positive voltage of 409).

FIG. 13 shows an example in which the p base 6 and the n base 403 are each provided with a refresh MOS transistor. These operations have already been explained.

This example uses an amorphous transistor for light reception, and the effective light reception area can be increased, and the amorphous band gap is 1.7.
Since it is large at ~1.8 eV, it has the advantage of high light-receiving sensitivity on the short wavelength side.

The wiring embedded inside is made of a high melting point metal or a silicide of a high melting point metal as described above. A PSG film, a CVD SiO ₂ film, or a sputtered SiO ₂ film is provided thereon. If you plan on flattening the insulating film, you can install a sputterer SiO ₂ at the end, change the voltage between the electrodes (DC bias) within the same chamber, and switch to a mode in which the SiO ₂ on the sample is sputtered. I can do it. after that,
After opening the contact hole 410, p ⁺ polysilicon is deposited by CVD, and after patterning, high-resistance amorphous silicon is deposited to a predetermined thickness (2 to 7 μm). Amulfas silicon is deposited by low-temperature evaporation in ultra-high vacuum,
For example, sputtering using an Ar atmosphere, CVD using SiH ₄ or Si ₂ H ₆ (including plasma CVD), etc. may be used. using organometallic source gas
MOCVD is also one method. After forming the insulation isolation region 405, the n base 403, the p ⁺ emitter 4
04 can be created using diffusion technology, ion implantation technology, etc.

As already mentioned, in a photoelectric conversion device using a photosensor cell having the above-mentioned configuration, the amplification amplifier at the final stage can be extremely simple, so the configuration shown in FIG. 14 in which only one amplification amplifier at the final stage is provided Instead of the type of configuration example shown, it is also possible to install a plurality of amplifiers so that one screen is divided into a plurality of parts and read out.

FIG. 24 shows an example of a divided readout method. The configuration example shown in FIG. 24 is an example in which the horizontal direction is divided into three parts and three final stage amplifiers are installed. The basic operation is almost the same as that explained using the configuration example in FIG. 14 and the timing diagram in FIG. 21, but in the configuration example in FIG. , 102 and a terminal 1 for applying these starting pulses.
When the starting pulse is input to 03, the 1st column, (n+1)
The outputs of the sensor cells connected to the (2n+1)th column (n is an integer, and in this embodiment, the number of picture elements in the horizontal direction is 3n) are read out simultaneously. At the next time, the second column, (n+2) column, and (2n+2) column will be read. According to this configuration example, when the time to read one horizontal line is fixed, the horizontal scanning frequency is 1/3 compared to the system with one final stage amplifier. A high-speed analog-to-digital converter is unnecessary for applications where the frequency is sufficient, the horizontal shift register is simple, and the output signal from a photoelectric conversion device is converted from analog to digital for signal processing. This is a major advantage of the readout method.

In the configuration example shown in FIG. 24, three equivalent horizontal shift registers are provided, but the same function can be provided with only one horizontal shift register. The configuration example in this case is shown in the 25th section.
As shown in the figure.

The configuration example in FIG. 25 uses the horizontal switching MOS transistor of the configuration example shown in FIG.
Only the middle part of the final stage amplifier is shown, and the other parts are omitted because they are the same as the configuration example shown in FIG.

In this configuration example, one horizontal shift register 1
04 in the 1st column, (n+1) column, (2n
+1) are connected to the gates of the switching MOS transistors in the column so that those lines can be read out simultaneously. At the next point in time, the second column, (n+
2) column and (2n+2) column are read out.

According to this configuration example, although the number of wirings to the gate of each switching MOS transistor increases,
It is possible to operate with only one horizontal shift register.

In the examples shown in FIGS. 24 and 25, three output amplifiers are provided, but it goes without saying that this number may be increased depending on the purpose.

In both the configuration examples shown in FIGS. 24 and 25,
The starting pulses and clock pulses of the horizontal shift register and vertical shift register are omitted, but
Like other refresh pulses, these are either a clock pulse generator installed on the same chip or
It is supplied from a cross pulse generator located on another chip.

In this split readout method, when the horizontal line or the entire screen is refreshed at once, the storage time is slightly different between the light sensor cells in the n-th column and the (n+1)-th column, which causes dark current components and signal components to It is conceivable that slight discontinuities may occur and be noticeable on the image, but these amounts are small and pose no practical problem. Furthermore, even if this exceeds the allowable limit, correcting it using an external circuit will generate a square wave, subtracting this from the dark current component, and multiplying and dividing this by the signal component. This is easily possible using conventional correction techniques.

When capturing a color image using such a photoelectric conversion device, a stripe filter or a mosaic filter is placed on-chip on top of the photoelectric conversion device, or a separately manufactured color filter is attached to the photoelectric conversion device. It is possible to get a signal.

As an example, when R, G, and B stripe filters are used, a photoelectric conversion device using a photosensor cell according to the above configuration can obtain the R signal, G signal, and B signal from separate final stage amplifiers. It is possible. An example of this configuration is shown in FIG. Like FIG. 25, FIG. 26 also shows only the area around the horizontal shift register. The others are number 14
Same as Figure and Figure 24, only the first column is R.
color filter, the second row is the G color filter,
It is assumed that color filters are installed in the third column, such as the B color filter and the fourth column, the R color filter. As shown in Figure 26, the first row,
Each vertical line in the 4th column, 7th column, etc. is output line 1
10, which takes out the R signal. Also 2
Each vertical line of the 5th column, 8th column, etc. is connected to an output line 111, which takes out the G signal. Similarly, each vertical line of the 3rd column, 6th column, 9th column, etc. is connected to the output line 112.
Take out the signal. Output lines 110, 111, 1
12 are connected to an on-chip refresh MOS transistor and a final stage amplifier, for example, an emitter follower type bipolar transistor, and each color signal is output separately.

FIG. 27 shows a diagram for explaining the basic structure and operation of another example of a photosensor cell constituting a photoelectric conversion device according to another example of the configuration of the present invention. In addition, the equivalent circuit and the overall circuit configuration diagram are shown in Figure 28a.
Shown below.

The optical sensor cell shown in FIG. 27 is an optical sensor cell that can simultaneously perform a read operation and a line refresh using the same horizontal scan pulse. In Figure 27, the first
The difference from the configuration shown in Fig. 7 is that in Fig. 17, there was only one MOS capacitor electrode 9 connected to the horizontal line wiring 10, but there are also MOS capacitor electrodes on the sides of the vertically adjacent optical sensor cells. 1
20 is connected, and when viewed from one optical sensor cell, it is a double capacitor type.
In the figure, the emitters 7 and 7' of the vertically adjacent optical sensor cells are wired 8, which is a two-layer wiring.
and interconnects 121 (in FIG. 27, it looks like one vertical line, but two lines are arranged through an insulating layer), that is, the emitter 7 is connected to the interconnect 8 through the contact hole 19. The difference is that emitters 7' are connected to wiring 121 through contact holes 19'.

This becomes clearer when looking at the equivalent circuit shown in FIG. 28a. That is, the MOS capacitor 150 connected to the base of the optical sensor cell 152 is connected to the horizontal line 31, and the MOS capacitor 151 is connected to the horizontal line 31'. Furthermore, in the diagram of the optical sensor cell 152, the MOS capacitors 150' of the adjacent optical sensor cells 152' below are connected to a common horizontal line 31'.

The emitter of the optical sensor cell 152 is on the vertical line 3.
8, the emitters of the photosensor cells 152' are connected alternately to the vertical line 138, and the emitters of the photosensor cell 152'' are connected to the vertical line 38, respectively.

In the equivalent circuit of FIG. 28a, other than the basic photosensor cell section described above, the difference in the imaging device of FIG. In addition to the switching MOS transistor 148 for refreshing and the switching MOS transistor 40 for selecting the vertical line 38, a switching MOS transistor 140 for selecting the vertical line 138 is added, and one output amplifier system is added. The configuration of this output system consists of 4 switching MOS transistors for refreshing each line.
8 and 148 are connected, and a switching MOS for horizontal scanning is also installed.
It is also possible to use only one output amplifier as shown in FIG. 28b using transistors. FIG. 28b shows only the vertical line selection and output amplifier system portions of FIG. 28a.

This optical sensor cell of FIG. 27 and FIG. 28a
According to the configuration example shown in , the following operations are possible. That is, when the readout operation of each optical sensor cell connected to the horizontal line 31 is completed and the horizontal blanking period in the TV operation is in progress, the output pulse from the vertical shift register 32 is outputted to the horizontal line 31' by the MOS capacitor. 151, the optical sensor cell 152 that has been read is refreshed. At this time, the switching MOS transistor 48 is made conductive, and the vertical line 3
8 is grounded.

Further, the output of the photosensor cell 152' is read out to the vertical line 138 through the MOS capacitor 150' connected to the horizontal line 31'. At this time, naturally, the switching MOS transistor 148 is rendered non-conductive, and the vertical line 138
is in a floating state. In this way, with one vertical scan pulse, it is possible to simultaneously refresh the optical sensor cells that have already been read out and read out the optical sensor cells of the next line using the same pulse. At this time, as already explained, the voltage at the time of refreshing and the voltage at the time of reading are different because a bias voltage is applied at the time of reading due to the necessity of high-speed reading. This is achieved by changing the areas of the electrode 9 and the MOS capacitor electrode 120 so that even if the same voltage is applied to each electrode, different voltages are applied to the base of each photosensor cell.

That is, the area of the refresh MOS capacitor is smaller than the area of the read MOS capacitor. As in this example, when refreshing one line at a time instead of refreshing all sensor cells at once, the 17th
Although the collector may be formed of an n-type or n-substrate as shown in FIG. b, it may be desirable to separate the collectors for each horizontal line. When the collector is a substrate, the collectors of all the photosensor cells are a common area, so that a constant bias voltage is applied to the collectors in the storage and light reception/readout states. Of course, as explained above, floating-based refresh can be performed between the emitters even when a bias voltage is applied to the collector. However, in this case, there is a drawback that at the same time that the base region is refreshed, a wasteful current flows between the emitter collector of the cell to which the refresh pulse is applied, increasing power consumption.
In order to overcome these drawbacks, instead of making the collectors of all the sensor cells a common area, the collectors of the sensor cells arranged in each horizontal line are common, but the collectors of each horizontal line are structured to be separated from each other. That is, to explain in relation to the structure shown in FIG. 17, the substrate is a p-type, and n ⁺
Create a structure with an embedded area. The n ⁺ buried regions of adjacent horizontal lines may be separated by a structure in which a p region is interposed therebetween. Insulator isolation is better for reducing collector capacitors embedded along horizontal lines. In FIG. 17, since the collector is comprised of a substrate, all isolation regions surrounding the sensor cell are provided to approximately the same depth. On the other hand, in order to separate the collectors of each horizontal line from each other, the separation area in the horizontal line direction is made deeper than the separation area in the vertical line direction by a necessary value.

If the collector is separated for each horizontal line, if the voltage of the collector of that horizontal line is grounded when reading is finished and the refresh operation starts, the emitter-collector current as described above will not flow, and the power consumption will be reduced. does not result in an increase in When the refresh ends and the charge storage operation starts based on the optical signal, a predetermined bias voltage is applied to the collector region again.

According to the equivalent circuit shown in FIG. 28a, outputs are alternately output to the output terminals 47 and 147 for each horizontal line. As already explained, it is also possible to take out the output from one amplifier by using the configuration as shown in FIG. 28b.

As explained above, according to this configuration example, line refresh is possible with a relatively simple configuration,
It can also be applied to fields of application such as ordinary television cameras.

Other configuration examples of the present invention include a configuration in which an optical sensor cell is provided with a plurality of emitters, or a configuration in which one emitter is provided with a plurality of contacts.
A type that takes out multiple outputs from one optical sensor cell is considered.

This is because each optical sensor cell of the photoelectric conversion device according to the present invention has an amplification function, so even if multiple wiring capacitors are connected to each optical sensor cell in order to extract multiple outputs from one optical sensor cell, the optical sensor cell This is due to the fact that the internally generated accumulated voltage Vp can be read out to each output without attenuating too much.

In this way, by having a configuration in which multiple outputs can be taken out from each optical sensor cell, many advantages can be added to the photoelectric conversion device formed by arranging a large number of each optical sensor cell in terms of signal processing, noise countermeasures, etc. is possible.

Next, an example of a method for manufacturing a photoelectric conversion device according to the present invention will be described. Figure 29 shows selective epitaxial growth (N. Endo et al., “Novel device isolation
technology with selected epitaxial growth”
An example of the method for manufacturing the same is shown below.

An n ⁺ region 11 for contact is formed on the back side of an n-type Si substrate 1 with an impurity concentration of about 1 to 10 × 10 ¹⁶ cm ^-3 .
Provided by diffusion of As or P. In order to prevent autodoping from the n ⁺ region, an oxide film and a nitride film (not shown) are usually provided on the back surface.

The substrate 1 used has impurity concentration and oxygen concentration controlled to be uniform. That is, a crystal wafer having a sufficiently long and uniform carrier line time is used. For example, such a thing
Crystals produced by the MCZ method are suitable. An oxide film approximately 1 μm thick is formed on the surface of the substrate 1 by wet oxidation. That is, it is oxidized in an H ₂ O atmosphere or (H ₂ +O ₂ ) atmosphere. High-pressure oxidation at a temperature of about 900°C is suitable for obtaining a good oxide film without producing stacking faults.

On top of that, for example, a layer with a thickness of about 2 to 4 μm is added.
Deposit the SiO ₂ film by CVD. (N ₂ + SiH ₄ + O ₂ ) to the desired thickness at a temperature of about 300 to 500℃ using a gas system.
Deposit the _SiO2 film. The molar ratio of O ₂ /SiH ₄ is set to about 4 to 40, although it depends on the temperature. Through the photolithography process, the oxide film in the other regions is made up of (CF ₄ +
H ₂ ), C ₂ F ₄ , CH ₂ F _2, etc., by reactive ion etching (step a in Figure 29). For example, when one pixel is provided in 10 x 10 μm ² , Leave a SiO ₂ film in the form of a mesh with a pitch of 10 μm. The width of the SiO ₂ film is selected to be, for example, about 2 μm.
After removing the damaged layer and contaminant layer on the surface caused by reactive ion etching by Ar/Cl ₂ gas plasma etching or wet etching, the atmosphere is sufficiently cleaned by evaporation in an ultra-high vacuum or by using a load lock method. Amorphous silicon 301 is deposited by sputtering or low pressure CVD in which SiH ₄ gas is irradiated with a CO ₂ laser beam (step b in Figure 29), CBrF ₃ ,
Amorphous silicon other than those deposited on the side surfaces of the SiO layer is removed by anisotropic etching using reactive ion etching using gases such as CCl ₂ F ₂ and Cl ₂ (step c in Figure 29). Similarly, after sufficiently removing the damaged layer and the contaminant layer, the silicon substrate surface is thoroughly cleaned and (H ₂ + SiH ₂ , C ₂ +
The silicon layer is selectively grown using a HCl) gas system. Growth is performed under reduced pressure of several tens of Torr, the substrate temperature is set at 900 to 1000°C, and the molar ratio of HCl is set to a value higher than a certain level. If the amount of HCl is too small, selective growth will not occur. A silicon crystal layer grows on a silicon substrate, but the silicon on the _SiO2 layer grows.
Because it is etched by HCl, SiO ₂
No silicon is deposited on the layer (FIG. 29d).
The thickness of the n ^- layer 5 is, for example, about 3 to 5 μm. The impurity concentration is preferably set to about 10 ¹² to 10 ¹⁶ cm ^-3 . Of course, you can deviate from this range, but
It is desirable to select an impurity concentration and thickness such that at least the n ^- region is completely depleted at the diffusion potential of the pn ^- junction or when an operating voltage is applied to the collector.

Since commonly available HCl gas contains a large amount of water, an oxide film is constantly formed on the surface of the silicon substrate, making it impossible to expect high-quality epitaxial growth. watery
When HCl is in the cylinder, it reacts with the cylinder material and contains a large amount of heavy metals, mainly iron, which tends to result in an epitaxial layer with heavy metal contamination. Since it is desirable for the epitaxial layer used in the optical sensor cell to have as little dark current component as possible, it is necessary to suppress contamination by heavy metals to the utmost. In addition to using ultra-high purity materials for SiH ₂ Cl ₂ , HCl must also have a particularly low moisture content, preferably at least a low moisture content.
Use 0.5ppm or less. Of course, the lower the water content, the better. For even higher quality epitaxially grown layers, the substrate is first heated to 1150-1250
Oxygen is removed from near the surface by high temperature treatment at around 800°C, followed by long-term heat treatment at around 800°C to generate many micro defects inside the substrate, making it possible to perform intensive getttering with a denuded zone. It is also extremely effective to use it as a substrate. Since epitaxial growth is performed in the presence of the SiO ₂ layer 4 as a separation region, it is desirable that the growth temperature be as low as possible in order to reduce the amount of oxygen taken in from the SiO ₂ . With the commonly used high-frequency heating method, there is a lot of contamination from the carbon susceptor, making it difficult to lower the temperature further.
The wafer direct heating method using lamp heating, which does not involve bringing a carbon susceptor into the reaction chamber, provides a clean growth atmosphere and allows high-quality epitaxial layers to be grown at low temperatures.

Ultra-high purity fused sapphire, which has a lower vapor pressure, is suitable for the wafer support in the reaction chamber. The wafer direct heating method using lamp heating allows for easy preheating of the raw material gas and makes it easy to uniformize the temperature within the wafer surface even when a large flow of gas is flowing.In other words, the wafer direct heating method using lamp heating generates almost no thermal stress. suitable for obtaining. UV irradiation of the wafer surface during growth further improves the quality of the epitaxial layer.

Amorphous silicon is deposited on the sidewalls of the SiO ₂ layer forming the isolation region 4 (step c in FIG. 29). Since amorphous silicon is easily formed into a single crystal by solid phase growth, the crystal near the interface with the SiO ₂ separation region 4 becomes very good. High resistance n ^- layer 5
After forming by selective epitaxial growth (step d in Figure 29), a P region 6 with a surface concentration of about 1 to 20 × 10 ¹⁶ cm ^-3 is formed by diffusion from doped oxide or by low-dose ion implantation. The layer is formed to a predetermined depth by diffusion using the layer as a source. The depth of p region 6 is, for example, about 0.6 to 1 μm.

The thickness and impurity concentration of p region 6 are determined based on the following considerations. In order to increase the sensitivity, it is desirable to lower the impurity concentration in the p region 6 to reduce Cbe. Cbe is approximately given as follows.

Cbe=Aeε(q・N _A /2εVbi) ^1/2 However, Vbi is the emitter-base diffusion potential and is given by Vbi=kT/q1nN _D N _A /n _i ² . Here, ε is the dielectric constant of the silicon crystal, N _D is the impurity concentration of the emitter, N _A is the impurity density of the portion of the base adjacent to the emitter, and n _i is the true carrier concentration. The smaller N _A is, the more Cbe
As N A becomes smaller, the sensitivity increases, but if N _A is made too small, the base region will be completely depleted in the operating state, resulting in a punch-through state, so it cannot be made too low. It is set to such an extent that the base region is not completely depleted and a punch-through state occurs.

Thereafter, a thermal oxide film 3 having a thickness of several tens of Å to several hundred angstroms is formed on the surface of the silicon substrate by (H ₂ +O ₂ ) gas-based steam oxidation at a temperature of approximately 800 to 900°C. On top of that, (SiH ₄ +NH ₃ ) system gas
A nitride film (Si ₃ N ₄ ) 302 is formed to a thickness of about 500 to 1500 Å by CVD. The formation temperature is about 700-900℃. NH ₃ gas, along with HCl gas, also contains a large amount of water in commonly available products. If NH ₃ gas with a high moisture content is used as a raw material, the result will be a nitride film with a high oxygen concentration, resulting in poor reproducibility and an inability to obtain a selective etching ratio with the SiO ₂ film. _NH3 gas also
The moisture content should be at least 0.5 ppm or less. It goes without saying that the lower the water content, the more desirable it is. A PSG film 3 is further formed on the nitride film 302.
00 is deposited by CVD. For the gas system, for example, (N ₂ + SiH ₄ + O ₂ + PH ₃ ) is used,
With a thickness of about 2000 to 3000 Å at a temperature of about 450℃
A PSG film is deposited by CVD (step e in Figure 29). By a photolithography process including two mask alignment processes, an As-doped polysilicon film 304 is deposited on the n ⁺ region 7 and on the refresh and read pulse application electrodes. In this case, a p-doped polysilicon film may be used. For example, by two photolithography steps,
The PSG film, Si ₃ N ₄ film, and SiO ₂ film were all removed from the emitter, leaving the underlying SiO ₂ film in the area where the refresh and readout pulse application electrodes were to be provided.
Only the PSG film and Si ₃ N ₄ film are etched. after that,
As-doped polysilicon (N ₂ + SiH ₄ +
AsH ₃ ) or (H ₂ +SiH ₄ +AsH ₃ ) gas
Deposited by CVD method. Deposition temperature is 550℃~700℃
The film thickness is about 1000 to 2000 Å. Of course, non-doped polysilicon may be deposited by the CVD method and then As or P may be diffused. After the mask alignment photolithography process, the polysilicon film in other parts except on the emitter, refresh and readout pulse application electrodes is removed by etching. Furthermore, when the PSG film is etched,
Due to lift-off, the polysilicon deposited on the PSG film is removed in a self-aligned manner (step f in FIG. 29). The polysilicon film is etched with a gas such as C ₂ Cl ₂ F ₄ or (CBrF ₃ +Cl ₂ ), and the Si ₃ N ₄ film is etched with a gas such as CH ₂ F ₂ .

Next, a PSG film 305 is deposited by the gas-based CVD method as described above, and then a contact hole is formed on the polysilicon film for the refresh pulse and read pulse electrodes by a mask alignment process and an etching process. Under these conditions, Al,
Deposition of metals such as Al-Si, Al-Cu-Si, etc. by vacuum evaporation or sputtering, or plasma using (CH ₃ ) ₃ Al or AlCl ₃ as raw material gas.
CVD method or Al-C of the above raw material gas
Al is deposited using a light irradiation CVD method in which the bond or Al-Cl bond is cut by direct light irradiation.
When carrying out the above-mentioned CVD method using (CH ₃ ) ₃ Al or AlCl ₃ as the raw material gas, a large excess of hydrogen is allowed to flow. For narrow and steep contact holes
An excellent method for depositing Al is the CVD method, which raises the substrate temperature to a film thickness of 300 to 400°C in a clean atmosphere that does not contain moisture or oxygen. After patterning the metal wiring 10 shown in FIG. 17, an interlayer insulating film 306 is deposited by CVD. 3
06 is the above-mentioned PSG film or CVD method SiO ₂
If it is necessary to take film or water resistance into consideration, (SiH ₄ + NH ₃ ) gas-based plasma CVD is used.
This is a Si ₃ N ₄ film formed by the method. In order to keep the hydrogen content in the Si ₃ N ₄ film low, (SiH ₄ +
N ₂ ) Using plasma CVD method in gas system.

In order to increase the electrical withstand voltage of the Si ₃ N ₄ film formed by reducing the damage caused by the plasma CVD method and to reduce the leakage current, the photo CVD method is used.
The Si ₃ N ₄ film is excellent. There are two methods for optical CVD. (SiH ₄ + NH ₃ + Hg) gas system with 2537 Å ultraviolet rays from a mercury lamp from the outside, and (SiH ₄ + NH 3 + Hg) ₃ gas system with 1849 Å ultraviolet rays from a mercury lamp.
This is a method of irradiating UV rays. In both cases, the substrate temperature is about 150 to 350°C.

Through the mask alignment process and etching process,
The polysilicon on the emitter 7 is an insulating film 305,
After drilling a contact hole through 306 using reactive ion etching, Al,
Deposit metals such as Al-Si, Al-Cu-Si, etc. In this case, since the aspect ratio of the contact hole is large, deposition by CVD is superior. After patterning the metal wiring 8 in FIG. 17, a final passivation film is formed.
A Si ₃ N ₄ film or PSG film 2 is deposited by the CVD method (FIG. 29g).

In this case as well, the film produced using the photo-CVD method is excellent. 12 is a metal electrode made of Al, Al-Si, etc. on the back surface.

The method for manufacturing the photoelectric conversion device of the present invention involves a wide variety of steps, and FIG. 29 shows only one example.

The important point of the photoelectric conversion device of the present invention is that the p region 6
The problem lies in how to suppress leakage current between the and n ^- regions 5 and between the p region 6 and the n ⁺ region 7. n ^-
It goes without saying that dark current can be reduced by improving the quality of the region 5, but the problem lies in the interface between the isolation region 4 made of an oxide film or the like and the n ^- region 5. In FIG. 29, for this purpose, the separation area 4 is
We have explained a method in which amorphous Si is deposited on the sidewalls of the substrate and then epitaxially grown. In this case, amorphous Si is made into a single crystal by solid phase growth from the substrate Si during epitaxial growth. Epitaxial growth is performed at a relatively high temperature of about 850°C to 1000°C. Therefore, the board
Before the amorphous Si becomes single crystallized by solid phase growth from Si, microcrystals often begin to grow in the amorphous Si, which causes poor crystallinity. The lower the temperature, the faster the solid-phase growth becomes relatively faster than the speed at which microcrystals begin to grow in amorphous Si. Therefore, before performing selective epitaxial growth, it is necessary to If amorphous Si is made into a single crystal through processing,
The interfacial properties are improved. At this time, if there is a layer such as an oxide film between the substrate Si and the amorphous Si, the start of solid phase growth will be delayed, so an ultra-high cleanliness process is required to prevent such a layer from being included at the boundary between the two.

In addition to the above-mentioned furnace growth, for solid-phase growth of amorphous Si, rapid annealing technology is also effective, for example, by keeping the substrate at a certain temperature and heating it with a fuselage lamp or an infrared lamp, for a period of several seconds to several tens of seconds. When using such techniques, the Si deposited on the sidewalls of the SiO ₂ layer may be polycrystalline. However, it is necessary to use polycrystalline Si that can withstand loads using a very clean process and does not contain oxygen, carbon, etc. in the grain boundaries of the polycrystalline material.

After the Si on these SiO ₂ sides is single-crystalized, the Si
This will result in selective growth.

When leakage current at the interface between the SiO ₂ isolation region 4 and the high resistance n ^- region 5 becomes a problem, the high resistance n ^-
Only the portion of region 5 adjacent to SiO isolation region 4, n
This problem of leakage current can be avoided by increasing the impurity concentration of the semiconductor. For example, the n-type impurity concentration is increased to about 1 to 10×10 ¹⁶ cm ⁻³ only in a region of about 0.3 to 1 μm thick in the n ⁻ region 5 that contacts the isolated SiO ₂ region 4 . This configuration can be formed relatively easily. After forming a thermal oxide film with a thickness of about 1 μm on the substrate 1, it is deposited thereon by CVD. First, the SiO ₂ film is made into a SiO ₂ film having a required thickness and containing a predetermined amount of P. Furthermore, a separation region 4 is created by depositing SiO ₂ thereon by CVD. In the subsequent high-temperature process, phosphorus is diffused from the phosphorus-containing SiO ₂ film that exists in the form of a sandwich in the separation region 4 into the high-resistance n ^- region 5, resulting in a good impurity distribution with a high impurity concentration even at the interface. make.

In other words, the structure is as shown in FIG. 30. The isolation region 4 has a three-layer structure, in which 308 is a thermal oxide film SiO ₂ , 309 is a CVD SiO ₂ film containing phosphorus, and 301 is a CVD SiO ₂ film. Adjacent to the separation region 4 and between the n ^- region 5 and the n-region 307, an SiO ₂ film 309 containing phosphorus is formed.
Formed by diffusion from 307 is formed all around the cell. With this structure, the base
Although the collector-collector capacitance Cbc increases, the base-collector leakage current decreases dramatically.

In FIG. 29, an example was explained in which the isolation insulating region 4 was formed in advance and selective epitaxial growth was performed.
After epitaxial growth of the n ^-layer ,
U-group separation technology (A.Hayasaka
et al, “U-groove isolation technique for
high speed bipolar VLSI′S″, Tech.Dig.of
(see IEDM.P.62, 1982).

A photoelectric conversion device according to the present invention forms a bipolar transistor in which a base region, most of which is adjacent to the semiconductor wafer surface, is in a floating state in a region surrounded by an isolation region made of an insulator, This is a device that photoelectrically converts optical information by controlling the potential of a floating base region with an electrode provided on a part of the base region via a thin insulating film. An emitter region made of a high impurity concentration region is provided in a part of the base region, and this emitter is connected to a MOS transistor operated by a horizontal scan pulse. The aforementioned electrode provided on a portion of the floating base region via a thin insulating layer is connected to a horizontal line. The collector provided inside the wafer may be composed of a substrate, or depending on the purpose, it may be composed of high-concentration impurity embedded regions separated for each horizontal line on a high-resistance substrate of the opposite conductivity type. There is also. The pulse voltage applied when reading out a signal is substantially larger than the pulse voltage when refreshing the floating base region using the electrode provided through the insulating layer. In fact, you can use a pulse train that waits for two types of voltage, or as explained in the double capacitor structure, you can use a pulse train for refreshing.
The capacitance C _px of the read MOS capacitor electrode may be made larger than the capacitance C _px of the MOS capacitor electrode. By applying a refresh pulse, optically excited carriers are accumulated in the floating base region, which is brought into a reverse bias state, and a signal based on the optical signal is stored. When reading out the signal, the base-emitter is deeply biased in the forward direction. The feature is that a readout pulse voltage is applied so that signals can be read out at high speed. As long as it has these characteristics, the photoelectric conversion device of the present invention may be realized in any structure, and it is needless to say that it is not limited to the structure described in the above embodiments.

For example, the same applies to a structure in which the conductivity type is completely reversed from that described in the above embodiment. However, at this time, it is necessary to completely reverse the polarity of the applied voltage. In a structure in which the conductivity types are completely reversed, the region becomes n-type. That is, the impurities constituting the base are As and P. When the surface of a region containing As or P is oxidized, As or P becomes Si/
Pile up on the Si side of the SiO ₂ interface. That is,
A strong drift electric field is generated from the inner surface of the base, and the photoexcited holes immediately escape from the base to the collector side, and electrons are efficiently accumulated in the base.

If the base is p-type, the commonly used impurity is boron. When the surface of the p-region containing boron is thermally oxidized, boron is incorporated into the oxide film, so the boron concentration in the Si near the Si/SiO ₂ interface becomes slightly lower than the boron concentration inside. This depth depends on the oxide film pressure, but is usually several hundred angstroms.
A reverse drift electric field for electrons is generated near this interface, and electrons photoexcited in this region tend to be thickened on the surface. If this continues, the region where this reverse drift electric field is generated will become a dead region, but since the photoelectric conversion device of the present invention has an n ⁺ region along a part of the surface, the p-region Si/ Electrons gathered at the SiO ₂ interface flow into this n ⁺ region before being recombined. Therefore, even if there is a region where, for example, boron is reduced near the Si/SiO ₂ interface and a reverse drift electric field occurs, it hardly becomes a dead region. Rather, if such a region exists at the Si/SiO ₂ interface, the accumulated holes will be transferred to the Si/SiO ₂
By separating the holes from the interface and making them exist inside, the effect of holes disappearing at the interface is eliminated, and the effect of accumulating holes at the base of the p-layer becomes good, which is extremely desirable.

In addition to the solid-state imaging device described above, the photoelectric conversion device according to the present invention can also be used, for example, an image input device,
It can also be applied to image input devices such as facsimiles, workstations, digital copying machines, word processors, OCR, barcode reading devices, photoelectric conversion object detection devices for autofocus of cameras, video cameras, 8mm cameras, etc.

As described above, the photoelectric conversion device of the present invention accumulates carriers excited by light in the base region, which is the control electrode region in a floating state. i.e. Base Store Image
It is a device that should be called a Sensor, and is abbreviated as BASIS.

Since the photoelectric conversion device of the present invention can configure one pixel with one transistor, it is extremely easy to upgrade, and at the same time, its structure allows for less bleeding and smearing, and high sensitivity, allowing for a wide dynamic range. Since it has an internal amplification function, it generates a large signal voltage regardless of wiring capacitance, so it has the characteristics of low recording and easy peripheral circuitry. For example, its industrial value as a future high-quality solid-state imaging device is extremely high.

[Effects of the Invention] According to the present invention, it is possible to obtain gain controllable and highly sensitive photoelectric conversion output.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, in which a is a sectional view, b is an equivalent circuit diagram, c is a circuit configuration diagram, and d is a potential state diagram. FIG. 2 is a circuit configuration diagram using the optical sensor cell shown in FIG. 1. 3 and 6 are pulse waveform diagrams, FIG. 4 shows another embodiment, and FIG. 5 is a circuit configuration diagram. FIG. 7 is an equivalent circuit diagram showing another embodiment, FIG. 8 is a circuit configuration diagram thereof, and FIG. 9 is a pulse waveform diagram. FIG. 10 to FIG. 13 are explanatory diagrams according to embodiments of the present invention. FIG. 14 is a circuit diagram of a configuration example of a photoelectric conversion device according to the present invention. Figures 15 to 20
The figures up to the drawings are diagrams for explaining the main structure and basic operation of the optical sensor cell according to the present invention. 15th
16 is an equivalent circuit diagram during a read operation, FIG. 16 is an equivalent circuit diagram during a refresh operation, FIG. 17 a is a plan view, b is a sectional view, c is an equivalent circuit diagram, and FIG.
The figure is a graph showing the relationship between readout time and readout voltage, FIG. 19a is a graph showing the relationship between storage voltage and readout time, FIG. 19b is a graph showing the relationship between bias voltage and readout time, and FIG. A to C are graphs showing the relationship between refresh time and base potential. Figures 21 to 23 refer to Figure 14.
FIG. 21A is a pulse timing diagram, and FIG. 21B is a graph showing potential distribution during each operation. FIG. 22 is an equivalent circuit diagram related to the output signal, and FIG. 23 is a graph showing the output voltage from the moment of conduction in relation to time. 24, 25, and 26 are circuit diagrams showing other photoelectric conversion devices. FIG. 27 is a plan view for explaining the main structure of a modified example of the present invention. FIG. 28 is a circuit diagram of a photoelectric conversion device constituted by the optical sensor cell shown in FIG. 27. FIGS. 29 and 30 are cross-sectional views showing an example of a method for manufacturing a photoelectric conversion device of the present invention. 1...Silicon, 2...PSG film, 3...Insulating oxide film, 4...Element isolation region, 5...N ^- region (collector region), 6...P region (base region),
7, 7'...n ⁺ region (emitter region), 8...wiring, 9...electrode, 10...wiring, 11...n ⁺ region, 12...electrode, 13...capacitor, 14...
... Bipolar transistor, 15, 17... Junction capacitance, 16, 18... Diode, 19, 19'
... Contact portion, 20 ... Light, 28 ... Vertical line, 30 ... Photo sensor cell, 31 ... Horizontal line, 32 ... Vertical shift register, 33, 35 ...
...MOS transistor, 36, 37...terminal, 3
8... Vertical line, 39... Horizontal shift register, 40... MOS transistor, 41... Output line, 42... MOS transistor, 43...
Terminal, 44...Transistor, 45...Load resistance, 46...Terminal, 47...Terminal, 48...
MOS transistor, 49... terminal, 61, 62,
63... section, 64... collector potential, 67...
Waveform, 80, 81... Capacity, 82, 83... Resistance, 84... Current source, 100, 101, 102...
...Horizontal shift register, 111, 112...Output line, 138...Vertical line, 140...
MOS transistor, 148...MOS transistor, 150, 150'...MOS capacitor, 15
2,152'... Optical sensor cell, 202,203,
205... Base potential, 220... Buried p ⁺ region,
222, 225...Wiring, 251...p ⁺ area,
252...n ⁺ area, 253...wiring, 300...
...Amorphous silicon, 302...Nitride film, 3
03...PSG film, 304...Polysilicon, 3
05...PSG film, 306...Interlayer insulating film, 37
2...first phototransistor, 372...phototransistor.

Claims (1)

[Claims] 1: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type different from the first conductivity type;
It has a high-resistance semiconductor region, a third semiconductor region of a first conductivity type, and a fourth semiconductor region of a second conductivity type, and the first semiconductor region and the second semiconductor region are disposed adjacent to each other. The third semiconductor region and the fourth semiconductor region are arranged adjacent to each other, and the high-resistance semiconductor region is arranged between the second semiconductor region and the third semiconductor region. The first semiconductor region, the second semiconductor region, the third semiconductor region, and the high-resistance semiconductor region constitute a first transistor, and the second semiconductor region, the third semiconductor region, and the fourth semiconductor region constitute a first transistor. A second transistor is configured by the semiconductor region and the high-resistance semiconductor region, and one of the second semiconductor region and the third semiconductor region is a carrier composed of electrons and holes generated by photoexcitation. A photoelectric conversion device in which one electrode accumulates electrons and the other one accumulates electrons, the first electrode capacitively coupled to the second semiconductor region, and the second electrode capacitively coupled to the third semiconductor region.
electrodes, and readout means for reading out signals based on electrons and holes accumulated in the second and third semiconductor regions, respectively, and the readout means includes electrodes in the second and third semiconductor regions. and the third semiconductor region, the first and second electrodes independently apply a potential to the first and fourth semiconductor regions, and the second semiconductor region and the first semiconductor region and the third
A photoelectric conversion device characterized in that the device reads out the signal by forward biasing a junction between a semiconductor region and the fourth semiconductor region.