JPH06197280A - Signal processor - Google Patents

Abstract

PURPOSE:To attain high speed signal processing with simple circuit configuration by using plural relevant signal processing means so as to apply parallel processing to output signals from plural photo sensor arrays. CONSTITUTION:A base store image sensor is employed, in which carriers excited by light are stored in a base region of a control electrode region in the floating state. When a start pulse is inputted to a terminal 103, MOS transistors(TRs) are controlled by equivalent horizontal shift registers 100, 101, 102, and let the number of horizontal pixels be 3n, outputs of sensor cells connected to a 1st row, a (n+1)th row and a (2n+1)th row are simultaneously read out, then, a 2nd row, a (n+2)th row and a (2n+2)th row are read out and they are amplified and outputted by output TRs 44. Thus, the scanning frequency in the horizontal direction is set low and high speed A/D conversion in the signal processing is not required and high speed processing is executed with a simple circuit configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device and a photoelectric conversion method, and more particularly to a photoelectric conversion device and a photoelectric conversion method for accumulating carriers generated by light incidence and reading a signal based on the accumulated carriers. .

[0002]

2. Description of the Related Art In recent years, research on photoelectric conversion devices, particularly solid-state image pickup devices, has been actively conducted with the progress of semiconductor technology, and some have begun to be put to practical use.

These solid-state image pickup devices are roughly classified into two types, CCD type and MOS type. The CCD type image pickup device forms potential wells under the MOS capacitor electrodes, accumulates electric charges generated by the incidence of light in the wells, and at the time of reading, these potential wells are
The principle is that the accumulated charges are transferred to the output amplifier section and read out by sequentially moving them by the pulse applied to the electrodes. Further, in the CCD type image pickup device, the light receiving part is a pn
There is also a type in which a junction diode structure is used and the transfer unit is a CCD structure. On the other hand, the MOS-type image pickup device accumulates charges generated by the incidence of light in each of the photodiodes having a pn junction that constitutes a light receiving portion, and sequentially reads out the MOS switching transistors connected to the photodiodes at the time of reading. It is based on the principle that the charges accumulated by turning on are read out to the output amplifier section.

The CCD type image pickup device has a relatively simple structure, and in view of the noise that can be generated, only the capacitance value of the charge detector consisting of the floating diffusion in the final stage contributes to random noise. It is an imaging device with relatively low noise and is capable of low-illumination imaging. However, due to the process limitation of making a CCD type image pickup device, a MOS type amplifier is on-chip as an output amplifier, so 1 / f noise, which is easily noticeable on the image, is generated from the interface between silicon and the SiO ₂ film. To do. Therefore, although it is called low noise, there is a limit to its performance. Also,
If the number of cells is increased and the density is increased for higher resolution, the maximum amount of charge that can be stored in one potential well decreases, and the dynamic range cannot be obtained.
In the future, there will be a big problem in increasing the resolution of the solid-state imaging device. Further, since the CCD type image pickup device transfers the accumulated charges by sequentially moving the potential wells, even if there is a defect in one of the cells, the charge transfer is stopped there, or an extreme charge is generated. It also has a drawback that the production yield does not increase.

On the other hand, the MOS type image pickup device is a little complicated in structure as compared with the CCD type image pickup device, especially the frame transfer type device, but it can be constructed so as to increase the storage capacity and is dynamic. It has the advantage that it can take a wide range. Further, even if one of the cells has a defect, the defect does not affect other cells due to the XY address system, which is advantageous in terms of manufacturing yield. However, in this MOS type image pickup device, since wiring capacitance is connected to each photodiode at the time of signal reading, an extremely large signal voltage drop occurs, the output voltage drops, and wiring capacitance is large, which causes random noise. Is generated, fixed pattern noise is mixed due to variations in parasitic capacitance of each photodiode and MOS switching transistor for horizontal scanning, and low-illuminance shooting is more difficult than a CCD image pickup device. have.

Further, in the future high resolution of the image pickup apparatus, the size of each cell is reduced and the accumulated charge is reduced. On the other hand, the wiring capacity determined by the chip size does not decrease much even if the line width is reduced. Therefore, the MOS type image pickup device becomes more and more disadvantageous in terms of S / N.

Although the CCD type and MOS type image pickup devices have advantages and disadvantages as described above, they are gradually approaching the level of practical use. However, it can be said that there are inherently large problems in advancing the higher resolution required in the future.

On the other hand, regarding the solid-state image pickup device, JP-A-56-150878, "Semiconductor imager", JP-A-56-157073, "Semiconductor imager", and JP-A-56-165473, " A new method has been proposed for the “semiconductor image pickup device”. An image pickup device of CCD type or MOS type uses a charge generated by light incidence as a main electrode (for example, MO.
In contrast to the accumulation in the source of the S-transistor, the method proposed here is such that the electric charge generated by light incidence is stored in the control electrode (for example, the base of a bipolar transistor, SIT (static induction transistor) or MOS transistor). It is based on the new idea of controlling the flowing current by the charge accumulated in the gate) and generated by light. That is, CCD type, MO
While the S-type reads out the stored charge itself to the outside, the method proposed here reads out the stored charge after amplifying the charge by the amplification function of each cell. In addition, if the viewpoint is changed, the low impedance output is read out by impedance conversion. Therefore, the method proposed here has high output, wide dynamic range, low noise, and since carriers (charges) excited by an optical signal are accumulated in the control electrode, nondestructive readout is possible. Has some benefits. Furthermore, it can be said that this method has potential for higher resolution in the future.

[0009]

However, this system is basically an XY address system, and the device structure described in the above publication has a bipolar transistor in each cell of a conventional MOS type image pickup device. The basic configuration is a composite of amplification elements such as SIT transistors.
Therefore, although it has a relatively complicated structure and has the possibility of high resolution, there is a limit to high resolution as it is.

There are also limitations in the points described below. JP-A-56-150878, JP-A-56-15
7073, JP-A-56-165473 and SIT (Stat
ic Injection Transistor) Application to image sensor, Technical Report of Television Society (hereinafter referred to as TV Society journal) "
FIG. 1 shows a representative example of a conventional technique involving one of the inventors of the present invention.

JP-A-56-150878, JP-A-56-15707
The 3 ^{JP, N +, P +, I} ( or ^P -, ^N -), ^N
The charge is accumulated in the P ⁺ region of the hook structure composed of the ⁺ region,
There is described a configuration of a system in which the potential of an N ⁺ region forming a capacitor with the ground potential is read by a switching transistor.

However, with this configuration, it is not possible to read the output signal at a high speed and with sufficient linearity. Also in the reset operation after reading, only the P ⁺ region is grounded, the output side is not reset, and a noticeable afterimage is often generated. Also, fixed pattern noise is large.

On the other hand, Japanese Unexamined Patent Publication No. 56-165473 discloses N ⁺
Region, a floating P ⁺ region, a high resistance region, and an N ⁺ region connected to a transparent electrode to which a pulse voltage is applied, N ⁺ , P ⁺ , I (or P ⁻ , N ⁻ ), The hook structure of the N ⁺ region is shown. The floating N ⁺ region is also one of the main electrode regions of the read transistor at the same time. During the read operation, the transistor is turned on and electrons flow into the positively charged N ⁺ region, and the voltage change is used as a signal. Read out. However, this also cannot read the output signal at high speed and with sufficient linearity. Also, in the reset operation after reading, the N ⁺ region on the transparent electrode side opposite to the output circuit is set to 0 or slightly negative potential, and there is no reset on the output side. Many occur. Furthermore, high speed refresh is not possible.

In addition, the TV conference journal shows a gate storage type photocell and a base storage type photocell. Among them, the gate storage type photocell has a configuration in which the gate region is set in a floating state and the gate region is reverse-biased in advance to a predetermined voltage via a refresh line via an insulating film and read to an output circuit of a source ground resistance load. However, with this configuration, sufficient linearity cannot be obtained when the output signal is read at high speed. This is because the output voltage does not reach the required value in a short time because a sufficient forward bias is not applied during reading. Further, since resetting is not performed on the output side, the resetting operation is insufficient and many afterimages occur.

On the other hand, the base storage type photocell has N ⁺ , P
^+, N ^-, N ⁺ has a phototransistor structure, a base in a floating state (P ^+), a collector (N ⁺⁾ of pulses to a voltage is applied, the capacitance and the switching MOS
An emitter follower output circuit including an FET and an emitter (N ⁺ ) to which the output circuit is connected. However, in this configuration, since reading is performed by applying a voltage to the collector, it is difficult to ensure linearity at high speed operation, as will be described later with reference to FIGS. 5, 6, and 7. Also, in refreshing, since the emitter and collector are simply grounded, fixed pattern noise is large and high-speed refreshing cannot be performed.

In addition to the above-mentioned prior art, US Pat. No. 3,624,428 and Japanese Patent Publication No. 50-38531 disclose an output circuit of a grounded-emitter resistance load for a transistor in which an electrode is provided on the base through an insulating layer. Is connected, the base is reversely biased to perform the accumulation operation, and the output circuit of the grounded-emitter resistor load reads the current. After all, however, the linearity and the afterimage characteristic are poor because of the destructive type current reading. [Object of the Invention] It is an object of the present invention to provide a new photoelectric conversion device and photoelectric conversion method which have an amplification function in each cell and have an extremely simple structure and which can sufficiently cope with future high resolution. is there.

Another object of the present invention is to provide a photoelectric conversion device and a photoelectric conversion method in which afterimages and fixed pattern noise hardly cause problems even when high-speed reading with good linearity is performed, and high-speed refreshing is possible. It is in.

[0018]

The object is to electrically control a control electrode region made of a semiconductor of a first conductivity type and an output circuit including a capacitive load made of a semiconductor of a second conductivity type different from the first conductivity type. A first main electrode region electrically connected, and a second main electrode region made of a second conductivity type semiconductor,
In a transistor capable of accumulating carriers generated by receiving light energy in the control electrode region, and in a refresh operation after reading a signal based on the accumulated carriers, the first main electrode region is set to a reference potential. Refreshing means for holding and removing carriers accumulated in the control electrode area, wherein the refreshing means is a reference to the control electrode area. An electric potential is independently applied to the first and second main electrode regions from a voltage source, and the junction between the first main electrode region and the control electrode region held at the reference potential is sequentially arranged. This is achieved by a photoelectric conversion device characterized in that it is means for biasing in the direction.

Further, such an object is electrically connected to a control electrode region made of a first conductivity type semiconductor and an output circuit made of a second conductivity type semiconductor different from the first conductivity type and including a capacitive load. A first main electrode region and a second main electrode region made of a second conductivity type semiconductor, and a carrier capable of storing carriers generated by receiving light energy in the control electrode region. A photoelectric conversion method using a photoelectric conversion device, comprising: a refresh unit for holding the first main electrode region at a reference potential and removing carriers accumulated in the control electrode region. A storage step of irradiating the transistor with light to store carriers therein, a reading step of reading out a signal based on the carriers stored in the control electrode region, and the refreshing step. A potential is independently applied to the control electrode region from the reference voltage source with respect to the first and second main electrode regions, and the first main electrode region in a state of being held at the reference potential is And a refresh step of removing carriers accumulated in the control electrode region by forward biasing the junction with the control electrode region.

[0020]

According to the present invention, the potential of the control electrode region can be controlled independently of the main electrode region during the refresh operation.

During reading, the junction between the control electrode region and the main electrode region connected to the output circuit is biased. In this way, since the electric charge is stored in the capacitive load of the output circuit, the output signal can be obtained in the nondestructive mode.

At the time of refreshing, the potential of the control electrode region is independently controlled to deeply bias the junction between the control electrode region and the main electrode region in the forward direction to pass through the main electrode region connected to the output circuit. It is possible to refresh and remove the accumulated charge by high-speed operation, so that refreshing for removing afterimages and noise can be performed at high speed.

[0023]

The outline of a preferred embodiment of the present invention will be described below.

First, referring to FIGS. 1 and 2, an output circuit is connected to a first main electrode region (emitter) of a photoelectric conversion cell including a transistor as shown by reference numeral 30 in FIG. This output circuit has vertical lines 38, 3
8 ', 38 ", horizontal shift register 39, MOS transistors 40, 40', 40", output line 41, MOS
Transistor 42, output transistor 44, load resistor 4
The vertical lines 38, 38 ', and 38 "each have a wiring capacitance such as Cs indicated by reference numeral 21 in FIG. 2 as a capacitive load.

A vertical shift register 32 and buffer MOS transistors 33, 3 serve as reading means for reading a signal photoelectrically converted based on the accumulated charges.
3 ', 33 ", terminals 34, horizontal lines 31, 31', 3
1 "is provided in the circuit configuration.

During the storage operation, the emitter is floating or grounded, and the second main electrode region (collector) is biased to a positive potential. The control electrode region (base) is reverse biased with respect to the emitter, and the saturation voltage can be determined by controlling the base potential at this time. Thus, by appropriately setting the bias voltage, the cell itself can have a switching action.

During the read operation, the emitter is in a floating state and the collector is biased to a positive potential. The potential of the control electrode region is controlled by the read means independently of the main electrode region. When the base is biased in the forward direction with respect to the emitter, high-speed reading can be performed while ensuring good linearity. The operation at this time will be described with reference to FIG. At the time of reading, the wiring 1 is independently provided to the floating emitter and the collector held at a positive potential.
By biasing the base potential in the forward direction with respect to the emitter potential by applying a positive voltage V _R from 0, the emitter-base junction is deeply forward biased. In this way, the current flows until the emitter potential becomes equal to the base potential, that is, the storage voltage generated by light irradiation. The time required at this time is further shortened by the action of the voltage V _R , and even in high-speed reading. Therefore, excellent linearity can be secured.

The refresh operation is as follows.

The emitter is connected to the first reference voltage source, which is indicated by a ground symbol, by MOS transistors 48, 48 ', 48 "as switching means and is grounded.
At this time, the collector is connected to the second reference voltage source, that is, the positive potential or the ground potential. Thus, the vertical lines 38, 38 ', 38 "including the capacitive load are reset. The case where the collector is grounded is shown in FIG. 3. In such a state, a voltage of positive potential V _RH is applied. By controlling the electric potential of the base as the control electrode region, at least the base-emitter is forward-biased and holes accumulated in the base region flow out or electrons are accumulated in the base region. The charge disappears.As refresh means for applying such a forward bias, MOS transistors 48, 48 ', 48 ", buffer MOS transistors 35, 35', 35", terminal 3 are provided.
6. It is configured by providing a terminal 37 or the like which serves as a reference voltage source for independently applying the potential V _RH to the base.

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 4 is a diagram for explaining the basic structure and operation of the photosensor cell that constitutes the photoelectric conversion device according to the embodiment of the present invention. 4 (a) is a plan view of the optical sensor cell, FIG. 4 (b) is a cross-sectional view of the AA ′ portion of the plan view of FIG. 4 (a), and FIG. 4 (c) is an equivalent circuit thereof. Show. 4 (a), (b), (c) in each part.
The same numbers are attached to common items.

Although FIG. 4 shows a plan view of the alignment arrangement method, it is needless to say that the arrangement can also be made in the pixel shift method (interpolation arrangement method) in order to increase the horizontal resolution.

This optical sensor cell is shown in FIGS. 4 (a) and 4 (b).
As shown in FIG. 3, a passivation film usually made of a PSG film or the like is formed on a silicon substrate 1 which is doped with impurities such as phosphorus (P), antimony (Sb) and arsenic (As) to be an n type or n ⁺ type. The film 2, the insulating oxide film 3 made of a silicon oxide film (SiO ₂ ), the insulating film made of SiO ₂ or Si ₃ N ₄ or the like or the polysilicon film for electrically insulating between the adjacent photosensor cells. The element isolation region 4 formed, the n ⁻ region 5 having a low impurity concentration formed by the epitaxial technique, and the bipolar transistor doped with impurities such as boron (B) using the impurity diffusion technique or the ion implantation technique thereon. p region 6 becomes the base, the impurity diffusion technology, n ⁺ region 7 serving as the emitter of the bipolar transistor formed by the ion implantation technique or the like, the signal for reading to the outside For example, aluminum (A
l), a wiring 8 made of a conductive material such as Al-Si, Al-Cu-Si, etc., an electrode 9 for applying a pulse to the p region 6 in a floating state through the insulating film 3, and its wiring 10. , N having a high impurity concentration formed by an impurity diffusion technique or the like for making ohmic contact with the back surface of the substrate 1.
^{A +} region 11 and an electrode 12 made of a conductive material such as aluminum for giving the potential of the substrate, that is, the collector potential of the bipolar transistor.

Reference numeral 19 in FIG. 4A is a contact portion for connecting the n ⁺ region 7 and the wiring 8. Further, the alternating portions of the wiring 8 and the wiring 10 are so-called two-layer wiring, which are insulated from each other in an insulating region formed of an insulating material such as SiO ₂ . That is, it has a two-layer wiring structure of metal.

The capacitor Cox of the equivalent circuit of FIG. 4 (c)
13 is composed of an electrode 9, an insulating film 3, and a p-region 6 MOS structure, and the bipolar transistor 14 is an n ⁺ region 7 as an emitter, a p region 6 as a base, an n ⁻ region 5 with a low impurity concentration, and a collector. Of n or n ⁺ region 1 of FIG. As is clear from these drawings, the p region 6 is a floating region.

In the second equivalent circuit of FIG. 4C, the bipolar transistor 14 is connected to the base-emitter junction capacitance Cb.
e15, pn junction diode Dbe of base / emitter
16, the junction capacitance Cbc17 of the base-collector, and the pn junction diode Dbc18 of the base-collector. Here, originally as an equivalent circuit diagram,
The symbols indicating the two differently oriented current sources to be written in parallel with the pn junction diode Dbe16 and the pn junction diode Dbc18 are omitted. The basic operation of the optical sensor cell will be described below with reference to FIG. The basic operation of this photosensor cell is composed of a charge accumulation operation by light incidence, a read operation and a refresh operation.

First, the charge accumulation operation will be described.

In the charge storage operation, for example, the emitter is grounded through the wiring 8 and the collector is biased to a positive potential through the wiring 12. In addition, the base is assumed to be in a reverse bias state with respect to the negative potential, that is, the emitter 7 by applying a positive pulse voltage to the capacitor Cox 13 through the wiring 10 in advance. The operation of applying a pulse to the Cox 13 to bias the base 6 to a negative potential will be described in detail later in the description of the refresh operation.

In this state, when the light 20 enters from the front side of the photosensor cell as shown in FIG. 4, electron-hole pairs are generated in the semiconductor. Of these, electrons flow out to the n region 1 side because the n region 1 is biased to a positive potential, but holes are gradually accumulated in the p region 6. By accumulating the holes in the p region, the potential of the p region 6 gradually changes toward the positive potential.

In FIGS. 4A and 4B, the lower surface of the light-receiving surface of each sensor cell is almost entirely occupied by the p region, and a part thereof is n.
⁺ Area 7 As a matter of course, the concentration of electron-hole pairs excited by light is larger as it is closer to the surface. Therefore, many electron-hole pairs are excited in the p region 6 by light. If the photoexcited electrons in the p region immediately flow out from the p region 6 without being recombined and are absorbed in the n region, the holes excited in the p region 6 are accumulated as they are, The p region 6 is changed in the positive potential direction. When the impurity concentration of the p region 6 is made uniform, the photoexcited electrons are diffused and the p region 6 and the n ⁻ region 5 are exposed to the p region.
It flows to the n ⁻ junction, and thereafter is absorbed by the n collector region 1 by the drift due to the strong electric field applied to the n ⁻ region. Of course, the electrons in the p region 6 may travel only by diffusion. However, if the impurity concentration of the p-base decreases from the surface to the inside, this difference in impurity concentration causes , An electric field Ed from the inside to the surface in the base,

[0040]

[Equation 1] Occurs. Here, W _B is the depth from the light incident side surface of the p region 6, k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, N _AS is the surface impurity concentration of the p base region 6, and N _Ai
Is the impurity concentration at the interface between the p region 6 and the n ⁻ high resistance region 5.

Here, if N _AS / N _Ai > 3, electrons in the p region 6 travel by drift rather than diffusion. That is, in order to effectively operate the carrier excited by light in the p region 6 as a signal,
It is desirable that the impurity concentration of the p-region 6 decreases inward from the surface on the light incident side. If the p-region 6 is formed by diffusion, the impurity concentration thereof decreases toward the inside as compared with the surface on the light incident side.

A part below the light receiving surface of the sensor cell is occupied by the n ⁺ region 7. The depth of the n ⁺ region 7 is normally 0.
Since it is designed to have a thickness of about 2 to 0.3 μm or less, the amount of light absorbed in the n ⁺ region 7 is not so large originally, so there is no problem so much. However, for light on the short wavelength side, particularly for blue light, the presence of the n ⁺ region 7 causes a decrease in sensitivity. The impurity concentration of the n ⁺ region 7 is usually 1 × 1
It is designed to be about 0 ²⁰ cm ^-3 or more. The diffusion distance of holes in the n ⁺ region 7 doped with such a high concentration of impurities is about 0.15 to 0.2 μm. Therefore, in order for the holes photo-excited in the n ⁺ region 7 to effectively flow into the p region 6, it is desirable that the n ⁺ region 7 also has a structure in which the impurity concentration decreases from the light incident surface toward the inside. If the impurity concentration distribution of the n ⁺ region 7 is as described above, a strong drift electric field is generated from the surface on the light incident side toward the inside, and the holes photoexcited in the n ⁺ region 7 are immediately drifted by the p region 6 due to the drift. Flow into. If the impurity concentrations of the n ⁺ region 7 and the p region 6 are both reduced from the light incident side surface toward the inside, the n ⁺ region 7 and the p region existing on the light incident side surface side of the sensor cell All the carriers optically excited in 6 work effectively as an optical signal. If this n ⁺ region 7 is formed by impurity diffusion from a silicon oxide film or a polysilicon film that is heavily doped with As or P, it is possible to obtain an n ⁺ region having the desired impurity gradient as described above. Is.

Eventually, due to the accumulation of holes, the base potential changes to the emitter potential, and in this case, it changes to the ground potential and is clipped there. More precisely, the base-emitter is deeply biased in the forward direction, and the holes accumulated in the base are clipped by the voltage at which they start flowing out to the emitter. That is, the saturation potential of the photosensor cell in this case is approximately given by the potential difference between the bias potential and the ground potential when the p region 6 is first biased to a negative potential. When the n ⁺ region 7 is not grounded and the charges generated by the light input are accumulated in the floating state, the p region 6 can accumulate the charges to substantially the same potential as the n region 1.

The above is a qualitative outline of the charge accumulation operation, but a little more concrete and quantitative explanation will be given below.

The spectral sensitivity distribution of this optical sensor cell is given by the following equation.

[0046]

[Equation 2] Where λ is the wavelength of light [μm], α is the attenuation coefficient of light [μm ⁻¹ ] in the silicon crystal, and x is the “delaylayer” which causes recombination loss on the semiconductor surface and does not contribute to sensitivity.
The thickness of r ″ (insensitive region) [μm], y is the thickness of the epitaxial layer [μm], T is the transmittance, that is, the incident light amount is effectively incident on the semiconductor in consideration of reflection and the like. The photocurrent Ip is calculated by the following equation using the spectral sensitivity S (λ) and the irradiance Ee (λ) of this photosensor cell.

[0047]

[Equation 3] However, the irradiance Ee (λ) [μW · cm ⁻² · nm ⁻¹ ] is given by the following equation.

[0048]

[Equation 4] However E _V illuminance of the light receiving surface of the sensor [Lux], P (lambda)
Is the spectral distribution of the light incident on the light receiving surface of the sensor, V
(Λ) is the relative luminous efficiency of the human eye. Using these formulas, an optical sensor cell having an epi-thickness layer of 4 μm is illuminated by the A light source (2854 ° K) and the sensor light receiving surface illuminance is 1
In the case of [Lux], a photocurrent of about 280 nA / cm ⁻² flows and the number of incident photons or the number of generated electron-hole pairs is 1.8 × 10 ¹² / cm ² · s.
It is about ec.

At this time, the potential Vp generated by the accumulation of holes excited by light in the base is Vp =
Given by Q / C. Q is the amount of charge of holes accumulated, and C is the junction capacitance obtained by adding Cbe15 and Cbc17.

Now, the impurity concentration of the n ⁺ region 7 is set to 10 ²⁰ cm.
^-3 , the p-region 6 has an impurity concentration of 5 × 10 ¹⁶ cm ^-3 , the n ^- region 5 has an impurity concentration of 10 ¹³ cm ^-3 , the n ⁺ region 7 has an area of 16 μm ² , and the p-region 6 has an area of 64 μm ^2. , N ⁻ region 5 having a thickness of 3 μm has a junction capacitance of about 0.014 p
On the other hand, the number of holes accumulated in the F region is 1/60 sec, and the effective light receiving area, that is, the area obtained by subtracting the areas of the electrodes 8 and 9 from the area of the p area 6 is about 56 μm ^2. Then, it becomes 1.7 × 10 ⁴ .
Therefore, the potential Vp generated by the incidence of light is about 190 mV.

It should be noted here that when the resolution is increased and the cell size is reduced, the amount of light incident on one photosensor cell decreases, and the accumulated charge amount Q
However, since the junction capacitance also decreases in proportion to the cell size as the cell size is reduced, the potential Vp generated by light incidence is kept almost constant. This is because the optical sensor cell in the present invention has an extremely simple structure as shown in FIG. 4 and has a possibility that the effective light receiving surface can be made extremely large.

This is one of the reasons why the photoelectric conversion device of the present invention is advantageous as compared with the case of the interline type CCD. With the increase in resolution, the photoelectric conversion device of the interline type CCD image pickup device transfers data. If an attempt is made to secure the charge amount, the area of the transfer portion becomes relatively large, and the effective light receiving surface is reduced, so that the sensitivity, that is, the voltage generated by light incidence is reduced. Also,
In the interline type CCD image pickup device, the saturation voltage is limited by the size of the transfer part and decreases more and more. On the other hand, in the photo sensor cell of the present invention, as described above, Since the saturation voltage is determined by the bias voltage when the p region 6 is biased to a negative potential, a large saturation voltage can be secured.

The operation of reading out the voltage generated by the charges accumulated in p region 6 as described above will be described below.

In the read operation state, the emitter and the wiring 8 are kept in a floating state, and the collector is kept at the positive potential Vcc.

FIG. 2 shows an equivalent circuit. Here again, the pn junction diodes Dbe16 and pn are originally equivalent circuits.
The symbols indicating the two differently directed current sources to be written in parallel with the junction diode Dbc18 have been omitted.

Now, assuming that the potential when the base 6 is biased to a negative potential before light irradiation is -V _B and the accumulated voltage generated by light irradiation is V _P , the base potential is -V _B.
+ Has become V _P become potential. When a positive voltage V _R for reading is applied to the electrode 9 through the wiring 10 in this state, this positive potential V _R becomes a capacitance due to the oxide film capacitance Cox13, the base-emitter junction capacitance Cbe15, and the base-collector junction capacitance Cbc7. Split and voltage on the base

[0057]

[Equation 5] Is added. Therefore, the base potential is

[0058]

[Equation 6] Becomes here,

[0059]

[Equation 7] If the condition is satisfied, the base potential becomes the accumulated voltage V _P itself generated by light irradiation. In this way, when the base potential is biased in the positive direction with respect to the emitter potential, electrons are injected from the emitter to the base, and the collector potential is positive, so that the electrons are accelerated by the drift electric field to the collector. To reach. The current flowing at this time is given by the following equation.

[0060]

[Equation 8] Where A _j is the junction area between the base and emitter, q is the unit charge (1.6 × 10 ⁻¹⁹ Coulomb), D _n is the diffusion constant of electrons in the base, and n _pe is the minority carrier at the emitter end of the p base. , W _B is the base width, N _Ae is the acceptor concentration in the base emitter alone, N _Ac is the acceptor concentration at the collector end of the base, k is the Boltzmann constant, T is the absolute temperature,
V _e is the emitter potential.

This current has the emitter potential V _e as the base potential, that is, the accumulated voltage V generated here by light irradiation.
It is clear from the above equation that the current flows until it becomes equal to _P. At this time, the time change of the emitter potential V _e is calculated by the following equation.

[0062]

[Equation 9] However, the wiring capacitance Cs is the capacitance 21 of the wiring 8 connected to the emitter.

FIG. 5 shows an example of the change over time in the emitter potential calculated using the above equation. According to FIG. 5, it takes about 1 second for the emitter potential to become equal to the base potential. This is because the current does not flow so much when the emitter potential V _e approaches V _P. Therefore, the means to solve this is to apply the positive voltage V _R to the electrode 9 first,

[0064]

[Equation 10] Was set, but instead of this condition

[0065]

[Equation 11] It is conceivable to add the following condition and bias the base potential by V _{Bias in} an extra forward direction. The current flowing at this time is given by the following equation.

[0066]

[Equation 12] In FIG. 6, when V _Bias = 0.6V, after a certain period of time, V _R applied to the electrode 9 is returned to zero volt,
For the accumulated voltage V _P when the flowing current is stopped,
The relationship between the read voltage, that is, the emitter potential is shown. However, in FIG. 6, the read voltage is always added with a constant potential that depends on the read time due to the bias voltage component, but the value obtained by subtracting the amount of the error is plotted. Electrode 9
When the positive voltage V _R applied to the

[0067]

[Equation 13] Is added to the base potential, the base potential is in the state before the positive voltage V _R is applied, that is, −V _B.
Then, the current is stopped because the emitter is reverse biased. According to FIG. 6, if a read time of about 100 ns or more (that is, a time during which V _R is applied to the electrode 9) is taken, the linearity is ensured for the accumulated voltage V _P and the read voltage over a range of about 4 digits, and the high speed It can be read. In FIG. 6, the 45 ° line is the result when sufficient time is taken for reading. In the above calculation example, the capacitance Cs of the wiring 8 is set to 4 pF, which is 0.014 pF of the junction capacitance of Cbe + Cbc. It is shown that the accumulated voltage V _P generated in the p region 6 is not attenuated at all and is read at extremely high speed due to the effect of the bias voltage, though it is about 300 times larger than 6 shows. This is because the amplifying function of the photosensor cell according to the above configuration, that is, the charge amplifying function is effectively operating.

On the other hand, in the conventional MOS type image pickup device, the accumulated voltage V _P is CjV _P / (Cj + Cs) (where Cj is the MOS type image pickup device) due to the influence of the wiring capacitance Cs in such a reading process. The pn junction capacitance of the light receiving portion) occurs, and there is a drawback in that the read voltage value of two digits decreases. Therefore, in the MOS type image pickup device, fixed pattern noise due to variations in the parasitic capacitance of the switching MOS transistor for reading to the outside or random noise generated due to large wiring capacitance, that is, output capacitance is large, and the S / N ratio is high. However, in the photosensor cell having the configuration shown in FIGS. 4A, 4B, and 4C, the accumulated voltage generated in the p region 6 is read out to the outside. Is relatively large, fixed pattern noise and random noise due to output capacitance are relatively small, and it is possible to obtain a signal with a very good S / N ratio.

It has been shown above that when the bias voltage V _Bias is set to 0.6 V, linearity of about 4 digits can be obtained in a high speed read time of about 100 nsec. This linearity, read time and bias voltage Further _details of the calculation result of the relationship of V _Bias are shown in FIG. 7.

In FIG. 7, the horizontal axis represents the bias voltage V _Bias.
And the vertical axis represents the read time. The parameters show the time dependence until the read voltage reaches 80%, 90%, 95%, 98% of 1 mV when the storage voltage is 1 mV. As shown in FIG. 6, at a storage voltage of 1 mV, 80%, 90%, 95%,
When it is 98%, it is clear that the storage voltage higher than that shows a better value.

According to FIG. 7, when the bias voltage V _Bias is 0.6 V, the read voltage becomes 80% of the accumulated voltage and the read time becomes 0.12 μs, and 90% becomes 0.2.
It can be seen that 7 μs and 95% are 0.54 μs and 98% are 1.4 μs. Further, it is shown that if the bias voltage V _Bias is made larger than 0.6 V, the reading can be performed at higher speed. Thus, once the read time and the required linearity are determined from the overall design of the imaging device, the required bias voltage V _Bias can be determined using the graph of FIG.

Another advantage of the photosensor cell having the above structure is that holes accumulated in the p region 6 can be read nondestructively because the recombination probability of electrons and holes in the p region 6 is extremely small. is there. That is, when the voltage V _R applied to the electrode 9 at the time of reading is returned to zero volts, the potential of the p region 6 is in the reverse bias state before the voltage V _R is applied, and the accumulated voltage V _P generated by light irradiation is , Unless it is newly irradiated with light, it is stored as it is. This means that when the optical sensor cell according to the above configuration is configured as a photoelectric conversion device, a new function can be provided in terms of system operation.

The time during which the storage voltage V _P can be held in the p region 6 is extremely long, and the maximum holding time is rather limited by the dark current thermally generated in the depletion layer of the junction. That is, the photosensor cell is saturated by the dark current generated thermally. However, in the optical sensor cell according to the above configuration, the region where the depletion layer spreads is the n ⁻ region 5 which is a low impurity concentration region, and this n ⁻ region 5 is about 10 ¹² cm ⁻³ to 10 ¹⁴ cm ^−3. Since the impurity concentration is extremely low, the crystallinity is good, and there are few electron-hole pairs that are thermally generated, as compared with the MOS type and CCD type image pickup devices. For this reason, the dark current is small compared to other conventional devices. That is, the photosensor cell according to the above-mentioned configuration has a structure in which dark current noise is essentially small.

Next, the operation of refreshing the charges accumulated in p region 6 will be described.

In the photosensor cell having the above structure, as already described, the charges accumulated in the p region 6 are not erased by the reading operation. Therefore, in order to input new optical information, a refresh operation for extinguishing the previously accumulated charges is necessary. At the same time, the potential of the p region 6 in the floating state needs to be charged to a predetermined negative voltage. In the optical sensor cell according to the above configuration,
Similar to the read operation, the refresh operation is performed by applying a positive voltage to the electrode 9 through the wiring 10. At this time, the emitter is grounded through the wiring 8. The collector is
It is grounded or made to have a positive potential through the electrode 12. FIG. 3 shows an equivalent circuit of the refresh operation. However, an example is shown in which the collector side is grounded.

When a voltage of positive voltage V _RH is applied to the electrode 9 in this state, the oxide film capacitance Cox1 is formed on the base 22.
3, base-emitter junction capacitance Cbe15, base
By dividing the junction capacitance Cbc17 between collectors,

[0077]

[Equation 14] Is applied instantaneously as in the previous read operation. Due to this voltage, the base-emitter junction diode Dbe16 and the base-collector junction diode Dbc18 are forward biased to be in a conductive state, current starts to flow, and the base potential gradually decreases.

At this time, the change in the potential V of the base in the floating state is approximately represented by the following equation.

[0079]

[Equation 15] However,

[0080]

[Equation 16] i ₁ is a current flowing through the diode Dbc, and i ₂ is a current flowing through the diode Dbe. A _b is the base area, Ae
Is the emitter area, Dp is the diffusion constant of holes in the collector, p _ne is the hole concentration in the collector in the thermal equilibrium state, Lp is the mean free path of the holes in the collector, and n _pe is the electron concentration in the base in the thermal equilibrium state. is there. At i ₂ , the current due to hole injection from the base side to the emitter can be ignored because the emitter impurity concentration is sufficiently higher than the base impurity concentration.

The above-mentioned formula is approximate to the stepwise junction, which is deviated from the stepwise junction in an actual device, and the base has a small thickness and has a complicated concentration distribution. However, the refresh operation can be explained with a good approximation.

Of the current i ₁ flowing between the base and collector in the above equation, q · Dp · p _ne / Lp is the current due to holes,
That is, it shows the component in which holes flow from the base to the collector side. In the photosensor cell according to the above configuration, the impurity concentration of the collector is designed to be slightly lower than that of a normal bipolar transistor so that the current due to the holes easily flows.

FIG. 8 shows an example of the time dependence of the base potential calculated using this equation. The horizontal axis represents the time elapsed from the moment when the refresh voltage V _RH was applied to the electrode 9, that is, the refresh time, and the vertical axis represents the base potential. Also, the initial potential of the base is used as a parameter. The initial potential of the base is a potential indicated by the base in a floating state at the moment when the refresh voltage V _RH is applied, and is determined by V _RH , Cox, Cbe, Cbc and the electric charge accumulated in the base.

Referring to FIG. 8, the potential of the base does not depend on the initial potential, but always drops according to one straight line on the semi-log graph after a certain period of time.

FIG. 9 shows experimental values of changes in base potential with respect to refresh time. Compared to the calculation example shown in FIG. 8, the test device used in this experiment has a considerably large dimension, so the absolute value does not match the calculation example, but the change in the base potential with respect to the refresh time is on a semi-logarithmic graph. It is proved that it is changing linearly. In this experimental example, values are shown when both the collector and the emitter are grounded.

Now, assuming that the maximum value of the accumulated voltage V _P due to light irradiation is 0.4 [V] and the voltage V applied to the base by the refresh voltage V _RH is 0.4 [V], as shown in FIG. The maximum value of the initial base potential is 0.8 [V], and after 10 ^-15 [sec] after the refresh voltage is applied, the base potential starts to drop in a straight line, and after 10 ^-5 [sec], light is emitted. When there is not, that is, when the initial base potential is 0.4 [V], it matches the potential change.

There are two ways in which the p region 6 is charged to a negative potential by applying a positive voltage through the MOS capacitor Cox for a certain time and removing the positive voltage. One is an operation in which negative charges are accumulated by the holes having a positive charge flowing out from the p region 6 to the n region 1 which is mainly in the grounded state. In order to prevent holes from unilaterally flowing from the p region 6 to the n region 1 and electrons in the n region 1 from flowing into the p region 6 too much, the impurity density of the p region 6 is set to the impurity density of the n region 1. It should be higher.
On the other hand, electrons from the n ⁺ region 7 and the n region 1 flow into the p region 6 and recombine with holes, so that the p region 6
The operation of accumulating negative charges can also be performed. In this case, the impurity density of n region 1 is higher than that of p region 6. p
The operation of accumulating negative charges due to the outflow of holes from the region 6 is much faster than the operation of accumulating negative charges due to electrons flowing into the base of the p region 6 and recombining with holes. However, according to the experiments performed so far, it has been confirmed that even the refresh operation of injecting electrons into the p region 6 exhibits a sufficiently fast time response to the operation of the photoelectric conversion device.

When a large number of optical sensor cells having the above-described structure are arranged in the XY direction to form a photoelectric conversion device, the accumulated voltage V _{P in} each sensor cell is 0 to 0 in the above example depending on the image.
Although it varies between 0.4 [V], a constant voltage of about 0.3 [V] remains at the bases of all the sensor cells at 10 ⁻⁵ [sec] after the refresh voltage V _{RH is} applied. It can be seen that all the changes in the accumulated voltage V _P due to the image disappear. That is, in the photoelectric conversion device using the optical sensor cell according to the above configuration, the complete refresh mode in which the base potentials of all the sensor cells are brought to zero volts by the refresh operation (at this time, 10 [sec] is required in the example of FIG. 8), There are two transient refresh modes in which a certain constant voltage remains in the base potential, but the fluctuation component due to the accumulated voltage V _P disappears (in this case, 10 [μsec] to 1 in the example of FIG. 8).
0 [sec] refresh pulse). In the above example,
The voltage V applied to the base by the refresh voltage V _{RH
Although A} was set to 0.4 [V], this voltage V _A was set to 0.6
[V], the transient refresh mode is
According to FIG. 8, it occurs in 1 [nsec], and refreshing can be performed at an extremely high speed. The selection of whether to operate in the complete refresh mode or the transient refresh mode is determined by the purpose of use of the photoelectric conversion device.

When the voltage remaining at the base in this transient refresh mode is V _K , the refresh voltage V _RH
In the transient state at the moment of returning V _RH to zero volt after applying

[0090]

[Equation 17] Since the negative voltage is added to the base, the base potential after the refresh operation by the refresh pulse is

[0091]

[Equation 18] And the base is reverse biased with respect to the emitter.

It was explained above that the base is reverse biased in the storage state during the storage operation for storing the carriers excited by light. However, the refresh operation brings the base and the base into the reverse bias state. The two operations of going forward are performed at the same time.

FIG. 10 shows the base potential after the refresh operation with respect to the refresh voltage V _RH .

[0094]

[Formula 19] The experimental value of change of is shown. The value of Cox is taken as a parameter from 5 pF to 100 pF. Circles are experimental values, solid lines are

[0095]

[Equation 20] The calculation value calculated by the above is shown. At this time V _K =
It is 0.52 V and Cbc + Cbe = 4 pF. However, the probe capacity of the observation oscilloscope is 13 pF
Are connected in parallel to Cbc + Cbe. Like this
The calculated value and the experimental value are completely in agreement, and the refresh operation has been confirmed experimentally.

In the above refresh operation, FIG.
As described above, an example in which the collector is grounded has been described, but it is also possible to perform it in a state where the collector is at a positive potential. At this time, even if the refresh pulse is applied to the base-collector junction diode Dbc18,
If the positive potential applied to the collector is higher than the potential applied to the base by this refresh pulse, the current remains in the non-conducting state, so that the current flows only through the base-emitter junction diode Dbe16. For this reason, the decrease in the base potential becomes relatively slower than when the collector is grounded, but basically, exactly the same fast refresh operation as described above is performed.

That is, the relationship of the base potential with respect to the refresh time in FIG. 8 is that the oblique straight line when the base potential in FIG. 8 decreases shifts toward the right side, that is, in the direction requiring more time. Therefore, if the same refresh voltage V _RH as when the collector is grounded is used, it takes time to refresh, but if the refresh voltage V _RH is raised slightly, a high-speed refresh operation can be performed similarly to when the collector is grounded. It is possible. The above is the description of the basic operation of the photosensor cell having the above-described configuration, which includes the charge accumulation operation, the read operation, and the refresh operation by light incidence.

As described above, the basic structure of the optical sensor cell having the above-mentioned structure is the same as that described in Japanese Patent Laid-Open No. 56-15.
It has a very simple structure as compared with JP 0878, JP 56-157073, and JP 56-165473, and can sufficiently cope with future high resolution, and has excellent features. The advantages such as low noise, high output, wide dynamic range, and nondestructive readout that come from a certain amplification function are preserved.

Next, one embodiment of the photoelectric conversion device of the present invention in which the photosensor cells having the above-described structure are arranged two-dimensionally will be described with reference to the drawings.

The basic optical sensor cell structure is two-dimensionally 3 × 3.
FIG. 1 shows a circuit configuration diagram of the photoelectric conversion device arranged in the above.

The basic photosensor cell 30 surrounded by the dotted line described above (the collector of the bipolar transistor is shown to be connected to the substrate and the substrate electrode at this time), the horizontal for applying the read pulse and the refresh pulse. Lines 31, 31 ', 31 ", vertical shift register 32 for generating read pulses, vertical shift register 32 and horizontal lines 31, 31', 31"
Between the buffer MOS transistors 33, 33 ', 3
A terminal 34 for applying a pulse to the gate of 3 ", buffer MOS transistors 35, 35 ', 35" for applying a refresh pulse, a terminal 36 for applying a pulse to its gate, and a refresh pulse 37, a vertical line 38, 38 ', 38 "for reading the accumulated voltage from the basic photosensor cell 30, a horizontal shift register 39 for generating a pulse for selecting each vertical line, and opening / closing each vertical line. Gate MOS transistors 40, 40 ', 40 "for output, an output line 41 for reading the accumulated voltage to the amplifier section,
M for refreshing the charge accumulated in the output line
OS transistor 42, terminal 43 for applying a refresh pulse to MOS transistor 42, bipolar for amplifying an output signal, MOS, FET, J-FE
A transistor 44 such as T, a load resistor 45, a terminal 46 for connecting the transistor and a power supply, an output terminal 47 of the transistor, and vertical lines 40 and 4 in the read operation.
MOS transistors 48, 48 ', 48 "for refreshing the charges accumulated in 0', 40", and M
This photoelectric conversion device is constituted by a terminal 49 for applying a pulse to the gates of the OS transistors 48, 48 ', 48 ".

The operation of this photoelectric conversion device will be described with reference to the pulse timing charts shown in FIGS.
In FIG. 11, section 61 is refresh operation, section 6
2 corresponds to the accumulation operation, and section 63 corresponds to the reading operation.

At time t ₁ , the substrate potential, that is, the collector potential 64 of the photosensor cell portion is kept at the ground potential or the positive potential, but in FIG. 11, it is shown that it is kept at the ground potential. Whether it is the ground potential or the positive potential, as described above, the time required for refreshing is different, and the basic operation does not change. The potential 65 at the terminal 49 is high, the MOS transistors 48, 48 ', 48 "are kept conductive, and each photosensor cell is grounded through the vertical line 38, 38', 38". Further, a voltage for conducting the buffer MOS transistor is applied to the terminal 36 as shown by a waveform 66, and the buffer MOS transistors 35, 35 ', 35 "for all-screen batch refresh are in a conductive state. When a pulse such as waveform 67 is applied to 37, a voltage is applied to the bases of the respective photosensor cells through the horizontal lines 31, 31 ', 31 ", and as described above, the refresh operation is started and the charge is accumulated before that. Charge is refreshed according to the complete refresh mode or the transient refresh mode. Whether to enter the complete refresh mode or the transient refresh mode is determined by the pulse width of the waveform 67.

At time t ₂ , as described above, the base of the transistor of each photosensor cell is reverse-biased with respect to the emitter, and the operation proceeds to the next accumulation section 62. In the refresh section 61, as shown in the figure, all the other applied pulses are kept in the low state.

In the accumulation operation section 62, the substrate voltage,
That is, the collector potential waveform 64 of the transistor is set to a positive potential. As a result, electrons of the electron-hole pairs generated by the light irradiation can quickly flow to the collector side. However, maintaining the collector potential at a positive potential is not an essential condition because the base is reverse-biased with respect to the emitter, that is, the image is taken as a negative potential. There is no change in the accumulation operation.

In the accumulation operation state, the potential 65 of the gate terminals 49 of the MOS transistors 48, 48 ', 48 "is 65.
Is kept high as in the refresh period, and each M
The OS transistor remains conductive. For this reason, the emitter of each photosensor cell has vertical lines 38, 38 ', 3
It is grounded through 8 ″. When strong light is irradiated and holes are accumulated in the base and become saturated, that is, when the base potential becomes a forward bias state with respect to the emitter potential (ground potential), The holes are vertical lines 38,
38 ', 38 ", where the base potential change ceases and is clipped. Therefore, the emitters of vertically adjacent photosensor cells are commonly connected by vertical lines 38, 38', 38". Even
When the vertical lines 38, 38 ', 38 "are grounded in this manner, the blooming phenomenon does not occur.

A method for avoiding this blooming phenomenon is M
Even when the OS transistors 48, 48 ', 48 "are in the non-conducting state and the vertical lines 38, 38', 38" are in the floating state, the substrate potential, that is, the collector potential 64 is set to a slightly negative potential and the hole This can also be achieved by allowing the base potential to flow toward the collector side before the emitter when the base potential changes in the positive potential direction due to the accumulation. After the accumulation section 62, the reading section 63 starts from time t ₃ . At this time t ₃ , the potential 65 of the gate terminal 49 of the MOS transistors 48, 48 ′, 48 ″ is set to low, and the horizontal lines 31, 31 ′, 3
1 ″ buffer MOS transistors 33, 33 ′, 3
The potential 68 of the gate terminal of 3 ″ is set high, and the respective MOS transistors are made conductive. However, the timing of setting the potential 68 of the gate terminal 34 high is not a prerequisite that it is time t ₃ , Any time earlier than that is fine.

At time t ₄ , of the outputs of the vertical shift register 32, the one connected to the horizontal line 31 has the waveform 6
As indicated by reference numeral 9, the MOS transistor 33 is conductive at this time, so that the reading of each of the three photosensor cells connected to the horizontal line 31 is performed. This read operation is as previously described,
The signal voltage generated by the signal charge accumulated in the base region of each photosensor cell is directly applied to the vertical lines 38, 3
8 ', 38 ". The pulse width of the pulse voltage from the vertical shift register 32 at this time is such that the read voltage with respect to the storage voltage maintains a sufficient linearity as shown in FIGS. The pulse voltage is set, and the pulse voltage is adjusted so that the emitter is forward biased by V _{Bias as} described above.

Next, at time t ₅ , of the outputs of the horizontal shift register 39, only the output to the gate of the MOS transistor 40 connected to the vertical line 38 has the waveform 7
It becomes high as 0, the MOS transistor 40 becomes conductive, and the output signal passes through the output line 41.
It enters the output transistor 44, is current-amplified, and is output from the output terminal 47. After the signal is read in this way, signal charges due to the wiring capacitance remain in the output line 41, so at time t ₆ , the MOS transistor 42 is discharged.
A pulse is applied to the gate terminal 43 as in the pulse waveform 71, the MOS transistor 42 is made conductive, the output line 41 is grounded, and the remaining signal charge is refreshed. In the same manner, the switching MOS transistors 40, 40 ', 40 "are sequentially turned on to read the signal output of the vertical lines 38, 38', 38". After reading the signals from the photosensor cells for one line arranged horizontally in this way, the vertical lines 38, 3 are read.
Similar to the output line 41, signal charges due to the wiring capacitance of the output line 41 remain in 8'and 38 ", so that the MOS transistors 48 and 48 'connected to the vertical lines 38, 38' and 38" are connected. , 48 ″ is made high to its gate terminal 49 as shown by the waveform 65 to make it conductive, and this residual signal charge is refreshed.

Next, at time t ₈ , of the outputs of the vertical shift register 32, the output connected to the horizontal line 31 'becomes high as shown by the waveform 69', and the accumulation of each photosensor cell connected to the horizontal line 31 '. The voltage is read out to each vertical line 38, 38 ', 38 ". Thereafter, the signal is read out from the output terminal 47 by the same operation as before.

In the above description, the application field in which the accumulation section 62 and the reading section 63 are clearly divided, for example, the operation state applied to the still video which has been actively researched and developed recently has been described. However, it can be applied to an application field in which the operation in the accumulation section 62 and the operation in the reading section 63 are simultaneously performed, such as a television camera, by changing the pulse timings in FIGS. 11 and 12. However, the refreshing at this time is not a full screen batch refresh, but a refresh function for each line is required. For example, after the signal of each photosensor cell connected to the horizontal line 31 is read, the time t
MOS transistors 48, 48 'for erasing charges remaining in the vertical line at _7, to conduct 48 ", applying a refresh pulse to the horizontal line 31 at this time. That is, even at the time t ₇ in the waveform 69 This can be achieved by using a vertical shift register configured to generate pulses having different pulse voltages and pulse widths as at time t _{4. Thus} , except for the double pulse operation, the right side of FIG. In place of the device for applying the batch refresh pulse installed on the right side, a second vertical shift register similar to that on the left side is provided on the right side, and the timing can be achieved by shifting the timing from the vertical register provided on the left side. It is possible.

At this time, the degree of freedom in the operation of suppressing the blooming by manipulating the potentials of the emitter and collector of each photosensor cell in the accumulation state as described above is reduced. However, as it has been explained in the basic operation, the read state, since the such a structure can high-speed reading at the time of applying a V _Bias becomes bias voltage to the base, as can be seen from the graph of FIG. 5, V _Bias Vertical line 2 due to saturation of each photosensor cell when no voltage is applied.
The amount of signal charges flowing out to 8, 28 ', 28 "is extremely small, and the blooming phenomenon does not pose any problem.

Also, with respect to the smear phenomenon, the photoelectric conversion device according to this embodiment can obtain extremely excellent characteristics. The smear phenomenon is a problem that occurs in operation and structure in which charge is transferred where light is irradiated in a CCD type image pickup device, particularly in a frame transfer type,
In the interline type, a problem particularly occurs because carriers generated in the deep portion of the semiconductor due to long wavelength light are accumulated in the charge transfer portion.

Further, in the MOS type image pickup device, there is a problem that carriers generated in the deep semiconductor region are accumulated by the light of the long wavelength on the drain side of the switching MOS transistor which is grounded to each photosensor cell.

On the other hand, in the photoelectric conversion device according to the present embodiment, there is no smear phenomenon that occurs due to operation and structure, and there is also a phenomenon that carriers generated in the semiconductor deep portion are accumulated due to long wavelength light. Absent. However, among the electrons and holes generated relatively near the surface of the emitter of the photosensor cell, there is concern about the development that electrons are accumulated. This is because the emitter is grounded in the accumulation operation state during the batch refresh operation. Therefore, the electrons are not accumulated,
Smear phenomenon does not occur. Further, in the line refresh operation applied to a normal TV camera, the vertical line is grounded and refreshed before reading the accumulated voltage in the vertical line during the horizontal blanking period.
At this time, at the same time, the electrons accumulated in the emitter during one horizontal scanning period flow out, so that the smear phenomenon hardly occurs. As described above, in the photoelectric conversion device according to the present embodiment, the smear development occurs only to an essentially negligible degree in terms of its structure and operation, which is one of the great advantages of the photoelectric conversion device according to the present embodiment. Is one.

Further, the operation of suppressing the blooming phenomenon by operating the respective potentials of the emitter and collector in the accumulation operation state has been described above, but it is also possible to control the γ characteristic by utilizing this.

That is, during the accumulation operation, the potential of the emitter or collector is temporarily set to a certain negative potential, and the number of holes accumulated in the base is larger than the number of carriers giving this negative potential. Is made to flow to the emitter or collector side. As a result, the relationship between the accumulated voltage and the incident light quantity is γ = 1 of the silicon crystal when the incident light quantity is small.
The characteristic is such that γ is smaller than 1 at a place where the amount of incident light is large. That is, it is possible to give the characteristic of γ = 0.45 which is usually required for a television camera in a polygonal line approximation. If the above operation is performed once in the middle of the accumulation operation, it becomes a one-line approximation, and if the negative potential applied to the emitter or the collector is appropriately changed twice, a two-line type γ characteristic can be provided.

In the above embodiments, the silicon substrate is used as a common collector, but it is also possible to provide a buried n ⁺ region like a bipolar transistor and divide the collector for each line.

In addition to the pulse timing shown in FIG. 11, a clock pulse for driving the vertical shift register 32 and the horizontal shift register 39 is necessary for the actual operation.

FIG. 13 shows an equivalent circuit related to the output signal. The capacitance C _V 80 is the wiring capacitance of the vertical lines 38, 38 ′, 38 ″, and the capacitance C _H 81 is the wiring capacitance of the output line 41. The equivalent circuit on the right side of FIG. And M for switching
OS transistor 40, 40 ', 40 "is conductive, indicating a resistance value in its conductive state by a resistor R _M 82. The resistance of the amplification transistor 44 r _e 83
And an equivalent circuit using the current source 84. The MOS transistor 42 for refreshing the charge accumulation due to the wiring capacitance of the output line 41 is in a non-conducting state in the read state and has a high impedance, so that it is omitted in the equivalent circuit on the right side.

Each parameter of the equivalent circuit is determined by the size of the photoelectric conversion device actually configured. For example, the capacitance C _V 80 is about 4 pF and the capacitance C _H 81
Is about 4 pF, and the resistance R of the conductive state of the MOS transistor
FIG. 14 shows an example in which the output signal waveform observed at the output terminal 47 is calculated assuming that _M 82 is about 3 KΩ and the current amplification factor β of the bipolar transistor 44 is about 100.

In FIG. 14, the horizontal axis represents the switching MOS.
The vertical axis represents the time [μs] from the moment when the transistors 40, 40 ', 40 "are turned on, and the vertical axis represents the vertical lines 38, 38', 3
The output voltage [V] that appears at the output terminal 47 when the signal charge is read from each photosensor cell and a voltage of 1 volt is applied to the wiring capacitance C _V 80 of 8 ″ is shown.

The output signal waveform 85 shows that the load resistance R _E 45 is 1
0KΩ, 86 is when the load resistance R _E 45 is 5KΩ, and 87 is when the load resistance R _E 45 is 2KΩ. In both cases, the peak value is about 0.5V due to the capacitance division of C _V 80 and C _H 81. It has become. As a matter of course, the larger the load resistance R _E 45 is, the smaller the attenuation amount is, and the desired output waveform is obtained. The rise time is as fast as about 20 nsec with the above parameter values. By reducing the resistance R _M of the switching MOS transistors 40, 40 ′ and 40 ″ in the conductive state and the wiring capacitances C _V and C _H , it is possible to read data at a higher speed.

In the photoelectric conversion device using the optical sensor cell having the above configuration, the voltage appearing at the output is large due to the amplification function of each optical sensor cell, and therefore the amplification amplifier at the final stage is considerably larger than that of the MOS type image pickup device. A simple one will do. In the above-mentioned example, the example of using the one-stage type of bipolar transistor has been described, but it goes without saying that other methods such as a two-stage type can be used. When a bipolar transistor is used as in this example, the problem of 1 / f noise, which is easily noticeable on the image and is generated from the MOS transistor of the amplifier at the final stage in the CCD image pickup device, does not occur in the photoelectric conversion device of this embodiment. It is possible to obtain an image quality with an extremely good S / N ratio.

Another embodiment of the photoelectric conversion device of the present invention will be described below. This embodiment is intended to solve the inconvenience in the transient refresh mode.

FIG. 12 shows the potential levels at the emitter, base and collector parts during the cyclic refresh operation, accumulation operation, read operation and transient refresh operation. The voltage level of each part is the potential seen from the outside, and there is a part that does not coincide with the internal potential level.

To simplify the explanation, the diffusion potential between the emitter and the base is omitted. Therefore, when the emitter and the base are represented at the same level in FIG.

[0128]

[Equation 21] There is a diffusion potential given by.

In FIG. 12, a state represents a refresh operation, a state represents a storage operation, a state represents a read operation, and a state represents an operation state when the emitter is grounded. Regarding the potential level, the upper side shows a negative potential and the lower side shows a positive potential with 0 V as a boundary. It is assumed that the base potential before the state is zero volt and that the collector potential is biased to the positive potential from the state.

The above series of operations will be described with reference to the timing chart of FIG.

As shown by the waveform 67 in FIG. 11, at time t ₁ , a positive potential, that is, the refresh voltage V _RH is applied to the terminal 37.
Is applied to the base as in the state of FIG.

[0132]

[Equation 22] Partial pressure is applied. This potential gradually decreases toward the zero potential from time t ₁ to t ₂ , and becomes the potential 201 shown by the dotted line in FIG. 12 at time t ₂ . This potential is the potential V _K remaining at the base in the transient refresh mode, as described above. At time t ₂ , as shown in the waveform 67, the base voltage is applied to the base at the moment when the refresh voltage V _RH returns to zero voltage.

[0133]

[Equation 23] Since the generated voltage is generated by the capacitance division as before, the base becomes the potential obtained by adding the remaining voltage V _K and the newly generated voltage. That is, the base potential 202 shown in the state, which is

[0134]

[Equation 24] Given in.

When light enters the emitter in the reverse bias state, holes generated by the light are accumulated in the base region.
The base potential 202 gradually changes to a positive potential like the base potentials 203, 203 ', and 203 "according to the intensity of the incident light. The voltage generated by this light is V _P
And

Next, as shown by the waveform 69, a voltage is applied to the horizontal line from the vertical shift register, that is, the read voltage V _R.
Is applied to the base

[0137]

[Equation 25] Is added, the base potential 204 when no light is emitted is

[0138]

[Equation 26] Becomes The potential 204 at this time is, as described above,
It is set so as to be biased in the forward direction by about 0.5 to 0.6 V with respect to the emitter. Also, the base potential 20
5, 205 ', 205 "are each

[0139]

[Equation 27] Given in.

The base potential is thus relative to the emitter
When forward biased, electrons are injected from the emitter side, and the emitter potential gradually moves in the positive potential direction. The emitter potential 206 with respect to the base potential 204 when light is not irradiated is about 50 to 100 mV when the read pulse width is about 1 to 2 μs when the forward bias is set to 0.5 to 0.6 V. , If this voltage is V _B , the emitter potentials 207, 2
07 'and 207 "have sufficient linearity as long as the pulse width is 0.1 μs or more as in the previous example.
_P + V _B , V _P ′ + V _B , and V _P ″ + V _B.

After a certain read time, when the read voltage V _R becomes zero potential as shown by the waveform 69, the base has

[0142]

[Equation 28] Therefore, the base potential becomes the state before the read pulse is applied, that is, the reverse bias state as in the state, and the potential change of the emitter is stopped. That is, the base potential 208 at this time is

[0143]

[Equation 29] The base potentials 209, 209 'and 209 "are respectively

[0144]

[Equation 30] Given in. This is exactly the same as before reading was started.

In this state, the optical information signal on the emitter side is read out to the outside. After this reading is completed, each switching MOS transistor 48, 4
8 ′ and 48 ″ are in a conductive state, and the emitter is grounded, so that the emitter has a zero potential.
The refresh operation, the accumulation operation, and the read operation make a round, and then the state returns to the next state. At this time, before the first refresh operation, the base potential started from zero potential, but it made one round. After that the base potential

[0146]

[Equation 31] And the respective potentials have changed to V _P , V _P ′, and V _P ″. Therefore, in this state, even if the refresh voltage V _RH is applied, the base potential is V _K. , V _K + V _P , V _K + V _P ′,
V _K + V _P ″, which does not apply a sufficient forward bias to the base, and the amount of forward bias is large where the light hits strongly, but the optical information disappears.
It is obvious from the calculation example of the refresh operation shown in FIG. 8 that the information of the weak light portion remains without disappearing.

Such a phenomenon is peculiar to the transient refresh mode, and in the complete refresh mode, such a problem does not occur because it takes a long refresh time until the base potential always becomes zero potential.

A method of using the transient refresh mode capable of high-speed refresh and avoiding such inconvenience will be described below.

One way to solve this is that the base potential 210 is in the negative potential direction in the state, that is, in the reverse bias direction with respect to the emitter.
In the next state, it suffices to bring the base potential 210 to the zero potential or a slightly positive potential by some method before the refresh pulse is applied.

FIG. 24 (a) is a cross-sectional view of an optical sensor cell for achieving this, and FIG. 24 (b) is an equivalent circuit diagram thereof.
The internal potential diagrams are shown in (c). Figure 24
(A) differs from the sensor cell shown in FIG. 4 only in that it has a buried p ⁺ region 220. In the equivalent circuit diagram of FIG. 24B, the base region 6 of the sensor cell is the collector, the buried p ⁺ region 220 is the emitter, and a part of the high resistance n ⁻ region 5 between the base region 6 and the collector region 1 is the base. The pnp transistor 221 is added. The base region of the pnp transistor is loosely coupled with the collector region 1 of the sensor cell, and is shown by a dotted line in the equivalent circuit. Also, this buried p ⁺ region 2
20 is connected inside the crystal like a wiring 222,
It has a structure that voltage can be applied from outside the sensor area.

As is apparent from FIG. 24B, the p ⁺ buried region 220 forms one line in the horizontal line direction as indicated by 222, so in practice,
In FIG. 24 (a), it should be shown as a p ⁺ buried region continuously connected to the left and right. In FIG. 24A, a p ⁺ region is schematically shown in a part for the sake of clarity.

The potential for the internal electrons is as shown in FIG. 24C, and the buried p ⁺ region 22 is used.
The potential distribution in the vertical cross section that does not include 0 is no different from that shown in FIG. 12, but the potential distribution in the vertical cross section that includes the embedded p ⁺ region 220 has the potential distribution as indicated by the dotted line 223. ing. However, in this figure, the potential distribution is shown when the buried p ⁺ region 220 is biased to a slightly positive potential. In this state, the embedded p
^{When the +} region 220 is further biased in the positive potential direction, the n ⁻ region existing between them is completely punched through,
Holes flow into the base region 6 of the sensor cell from the p ⁺ region, and the potential of the base region 6 moves in the positive potential direction due to the holes.

Punch through the n ^- region and p ⁺
To pour holes from region 220 into the p base region,
When the thickness d of the n ⁻ region, the impurity density N, and the voltage applied to the p ⁺ region 220 are V _P ⁺

[0154]

[Equation 32] Design like. V _bi is the diffusion potential of the p ⁺ n ⁻ junction.

Therefore, in the state of FIG. 12, a positive voltage is applied to the buried p ⁺ region 220 through the wiring 222 to inject holes into the p base region, so that the base potential 210 is zero as described above. By bringing the potential or a slightly positive potential, it is possible to solve the disadvantageous phenomenon in the transient refresh mode. At this time, the voltage applied to the embedded p ⁺ region 220 is slightly smaller than the voltage applied to the sensor cell collector 1, that is, the embedded p ⁺ region 220 and the collector n.
It is possible to sufficiently pass holes into the base region 6 in a state where the region 1 is not forward biased.

Impurities forming the p ⁺ region (usually boron)
Generally has a large diffusion constant, and problems of autodoping and diffusion occur when the high resistance n ⁻ region 5 is formed by using the epitaxial technique. However, due to the low temperature of the epitaxial technique, the autodoping from the buried p ⁺ region is caused. And a device is made to suppress diffusion as much as possible.

The above one embodiment is different only in that the buried p ⁺ region is added to the basic photosensor cell by diffusion or ion implantation as described above, and the method of forming the latter part may be exactly the same.

FIG. 25 shows a sectional view of an optical sensor cell for explaining another embodiment. In the sectional view shown in FIG. 25, when the base region 6 is formed instead of the buried p ⁺ region 220 shown in FIG.
It has a structure to make 24. This P region 224 serves as an emitter, the low impurity n ⁻ region 5 serves as a base, and the base 6 of the photosensor cell serves as a collector to form a pnp transistor. This is because the pnp transistor having the vertical structure is formed as shown in FIG. 24, whereas the pnp transistor having the horizontal structure is formed. Therefore, in the embodiment of FIG. 25, the voltage is supplied to P region 224 through wiring 225 on the front surface side.

The equivalent circuit of the embodiment shown in FIG. 25 is
Although the pnp transistor has a vertical structure and a horizontal structure, it is exactly the same as the equivalent circuit shown in FIG. 24B, and its operation is also exactly the same as that already described.

In the cross-sectional view shown in FIG. 25, p ⁺ region 22
4. The wiring 225 thereof is shown in the same cross section as the MOS capacitor electrode 9, the emitter region 7 and the wiring 8 for the sake of explanation, but they can be arranged in other parts of the same photosensor cell. This is determined by design factors such as the shape of the window on which light is incident and the wiring.

As described above, in the photoelectric conversion device using the optical sensor cell having the above-described structure, the final stage amplification amplifier may be extremely simple. Therefore, only one final stage amplification amplifier is provided. Instead of the type as in the embodiment shown in FIG. 1, it is also possible to install a plurality of amplification amplifiers and divide one screen into a plurality of pieces for reading.

FIG. 15 shows an example of the division read method.
The embodiment shown in FIG. 15 is an example in which the horizontal direction is divided into three and three final stage amplifiers are installed. The basic operation is almost the same as that described with reference to the embodiment of FIG. 1 and the timing diagrams of FIGS. 11 and 12, but in the embodiment of FIG. 15, three equivalent horizontal shift registers 100, 10 are provided.
1, 102 are provided, and when a starting pulse is applied to the terminal 103 for applying these starting pulses, the first column, (n +
The outputs of the respective sensor cells connected to the 1) th column and the (2n + 1) th column (n is an integer, and the number of horizontal picture elements is 3n in this embodiment) are read simultaneously.
At the next time point, the second row, the (n + 2) th row, the (2n + 2) th row
The column will be read. According to this embodiment, when the time for reading one horizontal line is fixed,
The scanning frequency in the horizontal direction may be 1/3 of the frequency compared to the system with one final stage amplifier, which simplifies the horizontal shift ranger and converts the output signal from the photoelectric conversion device into an analog-digital signal. Then, a high-speed analog-to-digital converter is not required for applications such as signal processing, which is a great advantage of the divided read method.

In the embodiment shown in FIG. 15, three equivalent horizontal shift registers are provided, but a similar function can be provided by only one horizontal shift register. An example of this case is shown in FIG.

The embodiment of FIG. 16 shows only the intermediate portion of the horizontal switching MOS transistor and the final stage amplifier of the embodiment shown in FIG. 15, and the other portions are the same as those of FIG. It is omitted because it is the same as the example.

In this embodiment, the output from one horizontal shift register 104 is output to the first column, (n + 1) th column, (2n)
The gates of the switching MOS transistors in the (+1) th column are connected to read those lines at the same time. At the next time point, the second row, the (n + 2) th row, the (2n +
2) The column number is read.

According to this embodiment, each switching MO
Although the number of wirings to the gate of the S transistor is increased, only one horizontal shift register can operate.

In the examples of FIGS. 15 and 16, three output amplifiers are provided, but it goes without saying that the number may be increased depending on the purpose.

In each of the embodiments shown in FIGS. 15 and 16, the starting pulse and the clock pulse of the horizontal shift register and the vertical shift register are omitted, but these are provided in the same chip as other refresh pulses. Or a clock pulse generator provided on another chip.

In this divided reading method, when horizontal line batch or full screen batch refresh is performed, the nth column and (n
The accumulation time is slightly different between the photosensor cells in the (+1) th column, which may cause a slight discontinuity in the dark current component and the signal component, which may be noticeable on the image. Is small and practically no problem. Even if it exceeds the allowable limit, it is necessary to correct it using an external circuit to generate a poppy-like wave, and subtract it from the dark current component and multiply and divide it with the signal component. This is easily possible by using conventional correction techniques performed by.

When a color image is picked up by using such a photoelectric conversion device, a stripe filter, a mosaic filter, or the like is integrated on the photoelectric conversion device, or a separately prepared color filter is attached. A color signal can be obtained by combining them.

As an example, when the R, G, and B stripe filters are used, in the photoelectric conversion device using the photosensor cell according to the above configuration, the R signal, the G signal, and the B signal are respectively output from different final stage amplifiers. It is possible to obtain.
An example of this is shown in FIG. Similar to FIG. 16, this FIG. 17 also shows only around the horizontal shift register.
Others are the same as in FIGS. 1 and 15, except that the first column is an R color filter, the second column is a G color filter, the third column is a B color filter, and the fourth column is an R color filter. The color filter is attached to. Figure 1
As shown in FIG. 7, the vertical lines of the first column, the fourth column, the seventh column, ... Are connected to the output line 110, which takes out the R signal. The vertical lines in the second, fifth, eighth, ... Columns are connected to the output line 111, which takes out the G signal. Similarly, the vertical lines of the third column, the sixth column, the ninth column, ... Take out the B signal connected to the output line 112. The output lines 110, 111 and 112 are respectively connected to on-chip refresh MOS transistors and final stage amplifiers, for example, emitter follower type bipolar transistors, and each color signal is output separately.

FIG. 18 is a diagram for explaining the basic structure and operation of another example of the photosensor cell constituting the photoelectric conversion device according to another embodiment of the present invention. Further, FIG. 19 shows an equivalent circuit thereof and an overall circuit configuration diagram.

The photosensor cell shown in FIG. 18 is a photosensor cell capable of simultaneously performing a read operation and a line refresh by the same horizontal scan pulse. 18 is different from the configuration already shown in FIG. 4 in that in FIG. 4, M connected to the horizontal line wiring 10 is used.
The MOS capacitor electrode 1 having only one OS capacitor electrode 9 is also provided on the side of vertically adjacent photosensor cells.
20 is connected and is of a double capacitor type when viewed from one photosensor cell, and the emitters 7 and 7 ′ of the photosensor cells that are vertically adjacent to each other in the figure are the wiring 8 and the wiring 121 which are two-layer wiring. , (In FIG. 18, one vertical line is seen, but two lines are arranged through an insulating layer), that is, the emitter 7 is connected to the wiring 8 through the contact hole 19 and the emitter 7 ′. Are connected to the wiring 121 through the contact holes 19 ', respectively.

This becomes more apparent when the equivalent circuit of FIG. 19 is viewed. That is, the MOS capacitor 150 connected to the base of the photosensor cell 152 is connected to the horizontal line 31, and the MOS capacitor 151 is connected to the horizontal line 31 '. Further, the MOS capacitor 150 'of the photosensor cell 152' adjacent to the bottom of the photosensor cell 152 in the drawing is connected to the common horizontal line 31 '.

The emitters of the photosensor cells 152 are alternately connected to the vertical lines 38, the emitters of the photosensor cells 152 'are connected to the vertical lines 138, the emitters of the photosensor cells 152 "are connected to the vertical lines 38, and so on.

The equivalent circuit of FIG. 19 differs from the image pickup apparatus of FIG. 1 except for the basic photosensor cell section described above.
In addition to the switching MOS transistor 48 for refreshing the vertical line 38, a switching MOS transistor 148 for refreshing the vertical line 138, and a switching MOS transistor 40 for selecting the vertical line 38 and a switching for selecting the vertical line 138. A MOS transistor 140 is added and one output amplifier system is added. This output system has a configuration in which switching MOS transistors 48 and 148 for refreshing each line are connected, and a switching MOS transistor for horizontal scanning is used as shown in FIG. A configuration with only one is also possible. FIG. 20 shows only the vertical line selection and output amplifier system of FIG.

According to the photosensor cell of FIG. 18 and the embodiment shown in FIG. 19, the following operation is possible. That is, when the reading operation of each photosensor cell connected to the horizontal line 31 is completed and the horizontal blanking period in the television operation is completed, the output pulse from the vertical shift register 32 is output to the horizontal line 31 '. Through 151, the optical sensor cell 15 whose reading has been completed
Refresh 2. At this time, switching MOS
Transistor 48 is conductive and vertical line 38 is grounded.

The MO connected to the horizontal line 31 '
The output of the photosensor cell 152 'is read out on the vertical line 138 through the S capacitor 150'. At this time, as a matter of course, the switching MOS transistor 148 is turned off and the vertical line 138 is in a floating state. In this way, with one vertical scan pulse, it is possible to simultaneously refresh the photosensor cells that have already been read and read the photosensor cells of the next line with the same pulse. At this time, as already described, the voltage for refreshing and the voltage for reading are different because a bias voltage is applied during reading because of the necessity of high-speed reading.
As shown in FIG. 5, it is achieved by changing the areas of the MOS capacitor electrode 9 and the MOS capacitor electrode 120 so that different voltages are applied to the bases of the respective photosensor cells even if the same voltage is applied to each electrode. ing.

That is, the area of the refresh MOS capacitor is smaller than that of the read MOS capacitor. As shown in FIG. 4B, when the sensor cells are not refreshed all at once but refreshed line by line as in this example, the collector is made of an n type or an n substrate. However, it may be desirable to have separate collectors for each horizontal line. When the collector is the substrate, the collectors of all the photosensor cells are in the common region, so that a constant bias voltage is applied to the collector in the accumulation and light reception read states. Of course, as described above, the floating base can be refreshed between the emitters even when the bias voltage is applied to the collector. However, in this case, at the same time as the refreshing of the base region is performed, a wasteful current flows between the emitter and collector of the cell to which the refresh pulse is applied, resulting in a large power consumption. In order to overcome these drawbacks, the collectors of all the sensor cells are not common to each other, and the collectors of the sensor cells arranged in each horizontal line are common, but the collectors of each horizontal line are separated from each other. That is, in connection with the structure of FIG. 4, the substrate is of p-type, and n ⁺ collectors separated from each other by horizontal lines in the p-type substrate.
The structure has an embedded region. N of adjacent horizontal lines
^{The +} buried region may be separated by a structure having a p region interposed therebetween. Insulator isolation is better for reducing the collector capacitor buried along the horizontal line.
In FIG. 4, since the collector is composed of the substrate, the isolation regions surrounding the sensor cell are all provided to almost the same depth. On the other hand, in order to separate the collectors for each horizontal line from each other, the separation region in the horizontal line direction is set to be deeper than the separation region in the vertical line direction by a necessary value.

If the collector is separated for each horizontal line, when the voltage of the collector of the horizontal line is grounded when the reading operation is finished and the refresh operation is started, the emitter-collector current as described above does not flow. , Does not increase power consumption. When the refresh operation ends and the charge accumulation operation by the optical signal is started, a predetermined bias voltage is applied to the collector region again.

According to the equivalent circuit of FIG. 19, the output is alternately output to the output terminals 47 and 147 for each horizontal line. This is, as I already explained,
With the configuration shown in FIG. 20, it is possible to take out the output from one amplifier.

As described above, according to the present embodiment, the line refresh can be performed with a relatively simple structure, and the present invention can be applied to the application fields such as ordinary television cameras.

Another embodiment of the present invention is a type in which a plurality of emitters are provided in a photosensor cell or a plurality of contacts are provided in one emitter, and a plurality of outputs are taken out from one photosensor cell. Conceivable.

Since each photosensor cell of the photoelectric conversion device according to the present invention has an amplification function, even if a plurality of wiring capacitors are connected to each photosensor cell in order to take out a plurality of outputs from one photosensor cell, This is because the accumulated voltage Vp generated inside the photo sensor cell can be read out to each output without any attenuation.

As described above, with the structure in which a plurality of outputs can be taken out from each optical sensor cell, many advantages are provided for the signal processing or noise countermeasures for the photoelectric conversion device in which a large number of each optical sensor cell is arranged. It is possible to add.

Next, an example of a method of manufacturing the photoelectric conversion device according to the present invention will be described. 21 and 22 show selective epitaxial growth (N. Endo et al, “New device isolation
technology with selected epitaxial growth "Tech.
Dig. Of 1982 IEDM, pp. 241-244), an example of the manufacturing method is shown.

An n ⁺ region 11 for contact is provided by diffusion of As or P on the back surface side of the n-type Si substrate 1 having an impurity concentration of about 1 to 10 × 10 ¹⁶ cm ^-3 . Although not shown, an oxide film and a nitride film are usually provided on the back surface in order to prevent autodoping from the n ⁺ region.

As the substrate 1, a substrate whose impurity concentration and oxygen concentration are uniformly controlled is used. That is, a crystal wafer having a carrier line time that is sufficiently long and uniform is used. As such a material, for example, a crystal by the MCZ method is suitable. An oxide film of about 1 μm is formed on the surface of the substrate 1 by wet oxidation. That is, it is oxidized in a H ₂ O atmosphere or a (H ₂ + O ₂ ) atmosphere. To obtain a good oxide film without causing stacking faults, 900 ° C
High pressure oxidation at moderate temperatures is suitable.

A SiO ₂ film having a thickness of, for example, about _{2 to 4} μm is deposited thereon by CVD. (N ₂ + SiH ₄ + O
₂ ) Deposit a SiO ₂ film of desired thickness at a temperature of about 300 to 500 ° C. in a gas system. The O ₂ / SiH ₄ molar ratio is set to about 4 to 40 depending on the temperature. By the photolithography process, the oxide film in the part which becomes the isolation region between the cells is left and the oxide films in the other regions are (CF ₄ + H ₂ ), C ₂
Removal by reactive ion etching using a gas such as F ₄ , CH ₂ F ₂ (step (a) in FIG. 21), for example,
10 μm when one pixel is provided for 10 × 10 μm ^2.
The SiO ₂ film is left in the form of pitch mesh. The width of the SiO ₂ film is selected to be, for example, about 2 μm. The damage layer and the contamination layer on the surface due to the reactive ion etching are
After removing by r / Cl ₂ gas-based plasma etching or wet etching, vapor deposition in ultra-high vacuum, or sputtering in which the atmosphere is sufficiently cleaned by a load lock method, or a CO ₂ laser beam is applied to SiH ₄ gas. Amorphous silicon 301 is deposited by irradiation with low pressure photo CVD (step (b) in FIG. 21), CBrF
_{3, CCl 2 F 2, Cl} SiO 2 by anisotropic etching using reactive ion etching using a ₂ or the like of the gas
Amorphous silicon other than those deposited on the side surface of the layer is removed (step (c) in FIG. 21). As before, the damage layer and the contaminated layer are sufficiently removed, and then the surface of the silicon substrate is sufficiently cleaned. Selective growth of a silicon layer is carried out by a (H ₂ + SiH ₂ , Cl ₂ + HCl) gas system. Number 10 Tor
The growth is performed under a reduced pressure of r, and the substrate temperature is 900 to 10
The molar ratio of 00 ° C. and HCl is set to a value higher than a certain level. If the amount of HCl is too small, selective growth does not occur.
Although a silicon crystal layer grows on the silicon substrate,
Since silicon on the O ₂ layer is etched by HCl, silicon is not deposited on the SiO ₂ layer ((d) of FIG. 21). The thickness of the n ⁻ layer 5 is, for example, 3 to 5 μm.
It is about m. The impurity concentration is preferably 10 ¹² to 10 ¹⁶
Set it to about cm ^-3 . Of course, this range may be deviated, but the impurity concentration and the impurity concentration such that at least the n ⁻ region is completely depleted in the state of being completely depleted at the diffusion potential of the pn ⁻ junction or when the operating voltage is applied to the collector. It is desirable to select the thickness.

Since HCl gas that is usually available contains a large amount of water, an oxide film is always formed on the surface of a silicon substrate, so that high quality epitaxial growth cannot be expected. HCl containing a large amount of water reacts with the material of the cylinder in a state where it is contained in the cylinder, and contains a large amount of heavy metals centering on iron, which easily forms an epitaxial layer with a large amount of heavy metal contamination. Since it is more desirable for the epitaxial layer used for the optical sensor cell to have a smaller dark current component, it is necessary to suppress contamination by heavy metals to the utmost limit. It is needless to say that ultra-high-purity materials are used for SiH ₂ Cl ₂ , but HCl has particularly low water content, preferably at least 0.5 ppm water content.
Use the following: Of course, the lower the water content, the better. In order to further improve the quality of the epitaxial growth layer, the substrate is first subjected to a high temperature treatment of about 1150 to 1250 ° C. to remove oxygen from the vicinity of the surface, and then subjected to a long-term heat treatment of about 800 ° C. to generate many microdefects inside the substrate. It is also extremely effective to use a substrate having a denuded zone and capable of intrithic gettering. Since the epitaxial growth is performed in the state where the SiO ₂ layer 4 as the isolation region exists,
A lower growth temperature is desirable to reduce the uptake of oxygen from SiO ₂ . In the high-frequency heating method that is often used, it is difficult to further lower the temperature because there is much contamination from the carbon susceptor. The wafer direct heating method by lamp heating without bringing in a carbon susceptor into the reaction chamber can make the growth atmosphere the cleanest and can grow a high-quality epitaxial layer at a low temperature.

Ultrahigh-purity molten sapphire having a lower vapor pressure is suitable for the wafer support in the reaction chamber. The raw material gas can be preheated easily, and even if a large flow of gas is flowing, it is easy to make the wafer in-plane temperature uniform, that is, the wafer direct heating method by lamp heating that generates almost no thermal stress produces high-quality epitaxial layers. Suitable to get. UV irradiation on the wafer surface during growth
Further improve the quality of the epitaxial layer.

Amorphous silicon is deposited on the side wall of the SiO ₂ layer to be the isolation region 4 (step (c) in FIG. 21). Since amorphous silicon is likely to be single-crystallized by solid phase growth, the crystal near the interface with the SiO ₂ separation region 4 becomes very excellent. After forming the high resistance n ⁻ layer 5 by selective epitaxial growth (step (d) in FIG. 21), the P region 6 having a surface concentration of about 1 to 20 × 10 ¹⁶ cm ⁻³ is diffused from the doped oxide, or A low-dose ion implantation layer is used as a source to form a predetermined depth by diffusion. The depth of the p region 6 is, for example, 0.6 to
It is about 1 μm.

The thickness of the p region 6 and the impurity concentration are determined in the following way. To increase the sensitivity, p region 6
It is desirable to reduce the impurity concentration of and reduce Cbe. Cbe is approximately given as follows.

[0194]

[Expression 33] However, Vbi is the diffusion potential between the emitter and the base,

[0195]

[Equation 34] Given in. Where ε is the dielectric constant of the silicon crystal, N
_D is the impurity concentration of the emitter, N _A is the impurity concentration of the portion adjacent to the emitter of the base, and n _i is the true carrier concentration. Cbe becomes smaller as N _A becomes smaller and the sensitivity increases, but if N _A is made too small, the base region will be completely depleted in the operating state and become a punching through state, so it cannot be made too low. Absent. It is set to such an extent that the base region is not completely depleted and a punching through state does not occur.

Then, (H ₂ + O
₂ ) From several 10Å to several 100Å due to gas-based steam oxidation
A thermal oxide film 3 having a thickness of about 800 is formed at a temperature of about 800 to 900.degree. Then, a nitride film (Si ₃ N ₄ ) 302 of 500 to 15 is formed by CVD of (SiH ₄ + NH ₃ ) based gas.
It is formed with a thickness of about 00Å. Formation temperature is 700-90
It is about 0 ° C. NH ₃ gas and the normally available products along with HCl gas also contain a large amount of water. If NH ₃ gas with a large amount of water is used as a raw material, a nitride film with a high oxygen concentration will be formed, resulting in poor reproducibility.
The selective etching with the O ₂ film causes a result that a selective ratio cannot be obtained. The NH ₃ gas also has a water content of at least 0.
It should be 5 ppm or less. It goes without saying that the smaller the water content, the more desirable. A PSG film 300 is further deposited on the nitride film 302 by CVD. The gas system is, for example, (N ₂ + SiH ₄ + O ₂ + PH ₃ ),
A PSG film having a thickness of about 2000 to 3000 Å is deposited by CVD at a temperature of about 300 to 450 ° C. (step (e) in FIG. 21). An As-doped polysilicon film 304 is deposited on the n ⁺ region 7 and the refresh and read pulse application electrodes by a photolithography process including two mask alignment processes. In this case, a p-doped polysilicon film may be used. For example, a PSG film and Si are formed on the emitter by two photolithography processes.
_The 3N ₄ film and the SiO ₂ film are all removed, and the underlying Si
Only the PSG film and the Si ₃ N ₄ film are etched, leaving the O ₂ film. Then, the As-doped polysilicon is replaced with (N ₂
+ SiH ₄ + AsH ₃ ) or (H ₂ + SiH ₄ + A
sH ₃ ) gas is deposited by the CVD method. Deposition temperature is 5
The film thickness is about 50 ° C to 700 ° C and the film thickness is 1000 to 2000Å. Of course, non-doped polysilicon may be deposited by the CVD method and then As or P may be diffused.
The polysilicon film except for the emitter and the refresh and read pulse application electrodes is masked, and is removed by etching after the photolithography process. Further, when the PSG film is etched, P is caused by lift-off.
The polysilicon deposited on the SG film is removed in a self-aligned manner (step (f) in FIG. 21). The etching of the polysilicon film is performed using C ₂ Cl ₂ F ₄ , (CBrF ₃ +
Cl ₂ ), etc. is used for etching, and the Si ₃ N ₄ film is C
Etching is performed with a gas such as H ₂ F ₂ .

Next, after depositing the PSG film 305 by the gas-based CVD method as described above, contact holes are formed on the polysilicon film for the refresh pulse and read pulse electrodes by a mask aligning process and an etching process. Open. In such a state, Al, Al-Si, Al-
Metals such as Cu-Si or deposited by vacuum deposition or sputtering, or (CH _{3) 3} Al or AlCl ₃
Al is deposited by a plasma CVD method using as a raw material gas or a light irradiation CVD method of cutting the Al—C bond or Al—Cl bond of the above raw material gas by direct light irradiation. When performing the above-described CVD method using (CH ₃ ) ₃ Al or AlCl ₃ as a raw material gas, hydrogen is allowed to flow in a large excess. For depositing Al in a thin and steep contact hole, the CVD method in which the substrate temperature is raised to 300 to 400 ° C. in a clean atmosphere containing no moisture or oxygen is excellent. After the patterning of the metal wiring 10 shown in FIG. 4 is completed, the interlayer insulating film 306 is deposited by the CVD method. 306 is the above-mentioned PSG film, the CVD method SiO ₂ film, or the Si ₃ N ₄ film formed by the (SiH ₄ + NH ₃ ) gas-based plasma CVD method when it is necessary to consider the water resistance. Is. In order to keep the hydrogen content in the Si ₃ N ₄ film low, a plasma CVD method using a (SiH ₄ + N ₂ ) gas system is used.

In order to increase the electrical breakdown voltage of the Si ₃ N ₄ film formed by causing the phenomenon of damage by the plasma CVD method and reduce the leak current, Si ₃ by the photo CVD method is used.
N ₄ film is excellent. There are two types of photo CVD methods. A method of irradiating 2537Å ultraviolet rays of a mercury lamp from the outside with a (SiH ₄ + NH ₃ + Hg) gas system, and (S
This is a method of irradiating the iH ₄ + NH) ₃ gas system with 1849 Å ultraviolet rays from a mercury lamp. In both cases, the substrate temperature is 150-
It is about 350 ° C.

By the mask aligning process and the etching process, the insulating films 305 and 3 are formed on the polysilicon on the emitter 7.
After the contact hole penetrating 06 is opened by reactive ion etching, Al, Al-Si,
A metal such as Al-Cu-Si is deposited. In this case,
Since the aspect ratio of the contact hole is large, CVD
The deposition by the method is superior. After patterning the metal wiring 8 in FIG. 1, a Si ₃ N ₄ film or a PSG film 2 as a final passivation film is deposited by the CVD method (FIG. 22).

Also in this case, the film formed by the photo-CVD method is excellent. Reference numeral 12 is a metal electrode on the back surface made of Al, Al-Si, or the like.

The method for manufacturing the photoelectric conversion device of the present invention has various steps, and FIGS. 21 and 22 are merely examples.

An important point of the photoelectric conversion device of the present invention is how to reduce the leak current between the p region 6 and the n ⁻ region 5 and between the p region 6 and the n ⁺ region 7. n ^- region 5
Of course, to reduce the dark current by improving the quality of the isolation region 4 and the n ⁻ region 5 made of an oxide film or the like.
The interface is the problem. 21 and 22, for this purpose, amorphous Si is previously formed on the side wall of the isolation region 4.
A method of depositing and performing epitaxial growth has been described. In this case, the substrate S during epitaxial growth
Amorphous Si is single-crystallized by solid phase growth from i. Epitaxial growth is 850 ° C to 100
It is carried out at a relatively high temperature of about 0 ° C. Therefore, fine crystals often start to grow in the amorphous Si before the amorphous Si is single-crystallized by solid phase growth from the substrate Si, which causes deterioration of crystallinity.
The lower the temperature, the faster the solid-phase growth rate is in amorphous Si.
Before the selective epitaxial growth, 5
Amorphous Si is obtained by low-temperature treatment of about 50 ° C to 700 ° C.
If a single crystal is used, the interface characteristics are improved. At this time, if there is a layer such as an oxide film between the substrate Si and the amorphous Si, the start of solid phase growth is delayed, and therefore an ultra-high cleaning process that does not include such a layer at the boundary between the two is required.

For solid phase growth of amorphous Si, in addition to the above-described furnace growth, a rapid anneal technique of heating the substrate at a certain temperature and heating with a fish lamp or an infrared lamp for, for example, several seconds to several tens seconds is also available. It is valid. When using these technologies, Si
The Si deposited on the side wall of the O ₂ layer may be polycrystalline. However, it is necessary to deposit it by a very clean process to make polycrystalline Si that does not contain oxygen, carbon, etc. at the crystal grain boundaries of the polycrystalline body.

After the Si on the side surface of SiO ₂ is single-crystallized, the Si is selectively grown.

When the leakage current at the interface between the SiO ₂ isolation region 4 and the high resistance n ⁻ region 5 is inevitable, the high resistance n −
^- only the portion adjacent to the SiO ₂ isolation region 4 in the region 5, n
If the impurity concentration of the shape is increased, the problem of the leak current can be avoided. For example, only the n ⁻ region 5 in contact with the isolation SiO ₂ region 4 and having a thickness of about 0.3 to 1 μm,
For example, the n-type impurity concentration is increased to about 1 to 10 × 10 ¹⁶ cm ⁻³ . This structure can be formed relatively easily. After forming a thermal oxide film of about 1 μm on the substrate 1, it is deposited by the CVD method. Only first required thickness of the SiO ₂ film, keep the SiO ₂ film containing P of a predetermined amount. Further, SiO ₂ is deposited thereon by the CVD method to form the isolation region 4. In the subsequent high-temperature process, phosphorus is diffused from the SiO ₂ film containing phosphorus existing in the isolation region 4 in a sandwich shape into the high resistance n ⁻ region 5, and the interface has the highest impurity concentration. make.

That is, the structure is as shown in FIG. The isolation region 4 has a three-layer structure, 308 is a thermal oxide film SiO ₂ , and 309 is C containing phosphorus.
The VD method SiO ₂ film and 301 are CVD method SiO ₂ films. N adjacent to the isolation region 4 and between the n ⁻ region 5 and n
The region 307 is formed by diffusion from the SiO ₂ film 309 containing phosphorus. 307 is formed all around the cell. With this structure, the base-collector capacitance Cbc
Is large, but the base-collector leakage current is drastically reduced.

In FIG. 21 and FIG. 22, an example in which the isolation insulating region 4 is formed in advance and selective epitaxial growth is performed has been described, but a high resistance n ⁻ required on the substrate is described.
U-group isolation technology (A.Hayasaka et al, “U-groove isolation, in which a layer to be an isolation region is cut in a mesh shape by reactive ion etching after the layer is epitaxially grown to form the isolation region.
technique for highspeed bipolar VLSI'S ″, Tech.
Dig. Of IEDM. P.62, 1982, see also).

The photoelectric conversion device according to the present invention is a bipolar transistor in which a base region, most of which is adjacent to the surface of a semiconductor wafer, is in a floating state in a region surrounded by an isolation region made of an insulator. This is a device for photoelectrically converting optical information by controlling the potential of a base region which has been formed and brought into a floating state by an electrode provided in a part of the base region through a thin insulating layer. An emitter region composed of a high impurity concentration region is provided in a part of the base region, and this emitter is connected to a MOS transistor operated by a horizontal scan pulse. The above-mentioned electrodes provided on a part of the floating base region via a thin insulating layer are connected to the horizontal line. The collector provided inside the wafer may be composed of a substrate, or may be composed of a high-concentration impurity-embedded region separated for each horizontal line on a high resistance substrate of opposite conductivity type depending on the purpose. . The applied pulse voltage at the time of reading a signal is substantially higher than the pulse voltage at the time of refreshing the floating base region in the electrode provided via the insulating layer. In practice, a pulse train that waits for two kinds of voltage may be used, or, as described in the double capacitor structure, the capacitance C _ox of the refresh MOS capacitor electrode.
The capacitance C _ox of the read MOS capacitor electrode may be made larger than that. By applying a refresh pulse, the photo-excited carriers are accumulated in the floating base region in the reverse bias state to store a signal based on the optical signal, and at the time of reading the signal, the base and emitter are deeply biased in the forward direction. As described above, the read pulse voltage is applied so that the signal can be read at a high speed. It is needless to say that the photoelectric conversion device of the present invention may be realized by any structure as long as it has such characteristics, and is not limited to the structure described in the above embodiment. For example, the same applies to the structure described in the above embodiment and the structure in which the conductivity type is completely inverted. However, at this time, it is necessary to completely reverse the polarity of the applied voltage. In a structure in which the conductivity type is completely inverted, the region becomes n-type. That is, the impurities constituting the base are As and P.
become. When the surface of the area containing As and P is oxidized, As
And P pile up on the Si side of the Si / SiO ₂ interface. That is, a strong drift electric field from the surface to the inside is generated inside the base, the photoexcited holes immediately escape from the base to the collector side, and electrons are efficiently accumulated in the base.

When the base is p-type, the commonly used impurity is boron. When the surface of the p region containing boron is thermally oxidized, boron is incorporated into the oxide film, so that Si /
The boron concentration in Si near the SiO ₂ interface is slightly lower than the boron concentration inside. This depth is usually several 100 Å, although it depends on the oxide film thickness. Near this interface,
An anti-drift field for the electrons occurs, and the electrons photoexcited in this region tend to collect at the surface. Under this condition, the region in which the reverse drift electric field is generated becomes a dead region, but since the n ⁺ region exists in a part along the surface in the photoelectric conversion device of the present invention, p
The electrons collected at the Si / SiO ₂ interface of the region are
It flows into this n ⁺ region before it is recombined. Therefore, even if there is a region where, for example, boron is reduced in the vicinity of the Si / SiO ₂ interface and an inverse drift electric field is generated, it hardly becomes a dead region. Rather, When such regions are present at the Si / SiO ₂ interface, in order to be present within the accumulated holes pulled away from the Si / SiO ₂ interface, there is no effect of hole disappears at the interface of the p-layer The hole accumulation effect in the base is good, which is extremely desirable.

In addition to the solid-state image pickup device described above, the photoelectric conversion device according to the present invention includes, for example, an image input device, a facsimile, a workstation, a digital copying machine, an image input device such as a word processor, an OCR, a bar code reader. The present invention can also be applied to a photoelectric conversion subject detection device for autofocus such as a device, a camera, a video camera, and an 8 mm camera.

As described above, the photoelectric conversion device of the present invention accumulates carriers excited by light in the base region, which is the control electrode region in the floating state. That is, Base Store Image S
It is a device that should be called an "enor" and is abbreviated as "BASIS".

Since the photoelectric conversion device of the present invention can form one pixel with one transistor, it is extremely easy to increase the density, and at the same time, due to its structure, there is little blooming and smear and high sensitivity, and its dynamic range is high. Since it has a wide range and has an internal amplification function, a large signal voltage is generated irrespective of the wiring capacity, so that the recording is low and the peripheral circuit is easy. For example, as a high-quality solid-state imaging device of the future, its industrial value is extremely high.

[0213]

According to the present invention, the potential of the main electrode region is fixed and the potential of the control electrode region is independently controlled, and the junction between the control electrode region and the main electrode region is forward biased and accumulated. Since the charges are eliminated, afterimages and fixed pattern noise can be extremely reduced at high speed operation. Similarly, since the potential of the control electrode area is controlled independently of the main electrode area,
High-speed reading is possible while ensuring good linearity of the output voltage signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an exemplary embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram during a read operation of the photosensor cell according to the embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of a photosensor cell according to an embodiment of the present invention during a refresh operation.

4A is a plan view of an optical sensor cell according to an embodiment of the present invention, FIG. 4B is a sectional view, and FIG. 4C is an equivalent circuit diagram.

FIG. 5 is a graph showing the relationship between the read time and the read voltage of the photosensor cell according to the embodiment of the present invention.

FIG. 6 is a graph showing the relationship between the accumulated voltage and the read time of the photo sensor cell according to the embodiment of the present invention.

FIG. 7 is a graph showing the relationship between the bias voltage and the read time of the photo sensor cell according to the embodiment of the present invention.

FIG. 8 is a graph showing a relationship between a refresh time and a base potential of an optical sensor cell according to an example of the present invention.

FIG. 9 is a graph showing the relationship between the refresh time and the base potential of the photo sensor cell according to the embodiment of the present invention.

FIG. 10 is a graph showing the relationship between the refresh time and the base potential of the photo sensor cell according to the embodiment of the present invention.

11 is a pulse timing diagram of the photoelectric conversion device of FIG.

12 is a graph showing a potential distribution during each operation of the photoelectric conversion device of FIG.

13 is an equivalent circuit diagram related to an output signal of the photoelectric conversion device of FIG.

FIG. 14 is a graph showing the output voltage from the moment when the photoelectric conversion device of FIG. 1 becomes conductive in relation to time.

FIG. 15 is a circuit diagram showing another photoelectric conversion device.

FIG. 16 is a circuit diagram showing another photoelectric conversion device.

FIG. 17 is a circuit diagram showing another photoelectric conversion device.

FIG. 18 is a plan view for explaining a main structure of a modified example of the present invention.

19 is a circuit configuration diagram of a photoelectric conversion device configured by the optical sensor cell shown in FIG.

20 is a circuit configuration diagram of a photoelectric conversion device configured by the optical sensor cell shown in FIG.

FIG. 21 is a cross-sectional view showing an example of a method for manufacturing the photoelectric conversion device of the present invention.

FIG. 22 is a cross-sectional view showing an example of a method for manufacturing the photoelectric conversion device of the present invention.

FIG. 23 is a cross-sectional view showing an example of a method for manufacturing the photoelectric conversion device of the present invention.

FIG. 24 shows an optical sensor cell according to an embodiment of the present invention,
(A) is a sectional view, (b) is an equivalent circuit diagram thereof, and (c) is a potential distribution diagram.

FIG. 25 is a sectional view showing the main structure of another modification of the optical sensor cell.

[Explanation of symbols]

1 Silicon substrate 2 PSG film 3 Insulating oxide film 4 Element isolation region 5 n ^- region (collector region) 6 p region (base region) 7, 7'n ⁺ region (emitter region) 8 wiring 9 electrode 10 wiring 11 n ⁺ region 12 electrodes 13 capacitors 14 bipolar transistors 15 and 17 junction capacitances 16 and 18 diodes 19 and 19 'contact parts 20 light 28 vertical lines 30 photosensor cells 31 horizontal lines 32 vertical shift registers 33 and 35 MOS transistors 36 and 37 terminals 38 vertical lines 39 Horizontal shift register 40 MOS transistor 41 output line 42 MOS transistor 43 terminal 44 transistor 45 load resistor 46 terminal 47 terminal 48 MOS transistor 49 terminal 61, 62, 63 section 64 collector potential 67 waveform 80, 81 Capacitance 82,83 Resistance 84 Current source 100,101,102 Horizontal shift register 111,112 Output line 138 Vertical line 140 MOS transistor 148 MOS transistor 150,150 'MOS capacitor 152,152' Photosensor cell 202,203,205 Base potential 220 Buried p ⁺ region 222, 225 wiring 251 p ⁺ region 252 n ⁺ region 253 wiring 300 amorphous silicon 302 nitride film 303 PSG film 304 polysilicon 305 PSG film 306 interlayer insulating film

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] July 15, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title: Signal processing device

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device,
Especially from multiple photosensor arrays on the same substrate
The present invention relates to a signal processing device that processes the output signal of the.

[0002]

2. Description of the Related Art In recent years, research on photoelectric conversion devices, particularly solid-state image pickup devices, has been actively conducted with the progress of semiconductor technology, and some have begun to be put to practical use.

These solid-state image pickup devices are roughly classified into two types, CCD type and MOS type. The CCD type image pickup device forms potential wells under the MOS capacitor electrodes, accumulates electric charges generated by the incidence of light in the wells, and at the time of reading, these potential wells are
The principle is that the accumulated charges are transferred to the output amplifier section and read out by sequentially moving them by the pulse applied to the electrodes. Further, in the CCD type image pickup device, the light receiving part is a pn
There is also a type in which a junction diode structure is used and the transfer unit is a CCD structure. On the other hand, the MOS-type image pickup device accumulates charges generated by the incidence of light in each of the photodiodes having a pn junction that constitutes a light receiving portion, and sequentially reads out the MOS switching transistors connected to the photodiodes at the time of reading. It is based on the principle that the charges accumulated by turning on are read out to the output amplifier section.

The CCD type image pickup device has a relatively simple structure, and in view of the noise that can be generated, only the capacitance value of the charge detector consisting of the floating diffusion in the final stage contributes to random noise. It is an imaging device with relatively low noise and is capable of low-illumination imaging. However, due to the process limitation of making a CCD type image pickup device, a MOS type amplifier is on-chip as an output amplifier, so 1 / f noise, which is easily noticeable on the image, is generated from the interface between silicon and the SiO ₂ film. To do. Therefore, although it is called low noise, there is a limit to its performance. Also,
If the number of cells is increased and the density is increased for higher resolution, the maximum amount of charge that can be stored in one potential well decreases, and the dynamic range cannot be obtained.
In the future, there will be a big problem in increasing the resolution of the solid-state imaging device. Further, since the CCD type image pickup device transfers the accumulated charges by sequentially moving the potential wells, even if there is a defect in one of the cells, the charge transfer is stopped there, or an extreme charge is generated. It also has a drawback that the production yield does not increase.

On the other hand, the MOS type image pickup device is a little complicated in structure as compared with the CCD type image pickup device, especially the frame transfer type device, but it can be constructed so as to increase the storage capacity and is dynamic. It has the advantage that it can take a wide range. Further, even if one of the cells has a defect, the defect does not affect other cells due to the XY address system, which is advantageous in terms of manufacturing yield. However, in this MOS type image pickup device, since wiring capacitance is connected to each photodiode at the time of signal reading, an extremely large signal voltage drop occurs, the output voltage drops, and wiring capacitance is large, which causes random noise. Is generated, fixed pattern noise is mixed due to variations in parasitic capacitance of each photodiode and MOS switching transistor for horizontal scanning, and low-illuminance shooting is more difficult than a CCD image pickup device. have.

Further, in the future high resolution of the image pickup apparatus, the size of each cell is reduced and the accumulated charge is reduced. On the other hand, the wiring capacity determined by the chip size does not decrease much even if the line width is reduced. Therefore, the MOS type image pickup device becomes more and more disadvantageous in terms of S / N.

Although the CCD type and MOS type image pickup devices have advantages and disadvantages as described above, they are gradually approaching the level of practical use. However, it can be said that there are inherently large problems in advancing the higher resolution required in the future.

On the other hand, regarding the solid-state image pickup device, JP-A-56-150878, "Semiconductor imager", JP-A-56-157073, "Semiconductor imager", and JP-A-56-165473, " A new method has been proposed for the “semiconductor image pickup device”. An image pickup device of CCD type or MOS type uses a charge generated by light incidence as a main electrode (for example, MO.
In contrast to the accumulation in the source of the S-transistor, the method proposed here is such that the electric charge generated by light incidence is stored in the control electrode (for example, the base of a bipolar transistor, SIT (static induction transistor) or MOS transistor). It is based on the new idea of controlling the flowing current by the charge accumulated in the gate) and generated by light. That is, CCD type, MO
While the S-type reads out the stored charge itself to the outside, the method proposed here reads out the stored charge after amplifying the charge by the amplification function of each cell. In addition, if the viewpoint is changed, the low impedance output is read out by impedance conversion. Therefore, the method proposed here has high output, wide dynamic range, low noise, and since carriers (charges) excited by an optical signal are accumulated in the control electrode, nondestructive readout is possible. Has some benefits. Furthermore, it can be said that this method has potential for higher resolution in the future.

However, this method is basically X-
The Y-address method is the Y-address method, and the element structure described in the above publication has a basic configuration in which each cell of a conventional MOS type image pickup device is combined with an amplification element such as a bipolar transistor or an SIT transistor. Therefore, although it has a relatively complicated structure and has the possibility of high resolution, there is a limit to high resolution as it is.

There are also limitations in the points described below. JP-A-56-150878, JP-A-56-15
7073, JP-A-56-165473 and SIT (Stat
ic Injection Transistor) Application to image sensor, Technical Report of Television Society (hereinafter referred to as TV Society journal) "
FIG. 1 shows a representative example of a conventional technique involving one of the inventors of the present invention.

JP-A-56-150878, JP-A-56-15707
The 3 ^{JP, N +, P +, I} ( or ^P -, ^N -), ^N
The charge is accumulated in the P ⁺ region of the hook structure composed of the ⁺ region,
There is described a configuration of a system in which the potential of an N ⁺ region forming a capacitor with the ground potential is read by a switching transistor.

However, with this configuration, it is not possible to read the output signal at a high speed and with sufficient linearity. Also in the reset operation after reading, only the P ⁺ region is grounded, the output side is not reset, and a noticeable afterimage is often generated. Also, fixed pattern noise is large.

On the other hand, Japanese Unexamined Patent Publication No. 56-165473 discloses N ⁺
Region, a floating P ⁺ region, a high resistance region, and an N ⁺ region connected to a transparent electrode to which a pulse voltage is applied, N ⁺ , P ⁺ , I (or P ⁻ , N ⁻ ), The hook structure of the N ⁺ region is shown. The floating N ⁺ region is also one of the main electrode regions of the read transistor at the same time. During the read operation, the transistor is turned on and electrons flow into the positively charged N ⁺ region, and the voltage change is used as a signal. Read out. However, this also cannot read the output signal at high speed and with sufficient linearity. Also, in the reset operation after reading, the N ⁺ region on the transparent electrode side opposite to the output circuit is set to 0 or slightly negative potential, and there is no reset on the output side. Many occur. Furthermore, high speed refresh is not possible.

In addition, the TV conference journal shows a gate storage type photocell and a base storage type photocell. Among them, the gate storage type photocell has a configuration in which the gate region is set in a floating state and the gate region is reverse-biased in advance to a predetermined voltage via a refresh line via an insulating film and read to an output circuit of a source ground resistance load. However, with this configuration, sufficient linearity cannot be obtained when the output signal is read at high speed. This is because the output voltage does not reach the required value in a short time because a sufficient forward bias is not applied during reading. Further, since resetting is not performed on the output side, the resetting operation is insufficient and many afterimages occur.

On the other hand, the base storage type photocell has N ⁺ , P
^+, N ^-, N ⁺ has a phototransistor structure, a base in a floating state (P ^+), a collector (N ⁺⁾ of pulses to a voltage is applied, the capacitance and the switching MOS
An emitter follower output circuit including an FET and an emitter (N ⁺ ) to which the output circuit is connected. However, in this configuration, since reading is performed by applying a voltage to the collector, it is difficult to ensure linearity at high speed operation, as will be described later with reference to FIGS. 5, 6, and 7. Also, in refreshing, since the emitter and collector are simply grounded, fixed pattern noise is large and high-speed refreshing cannot be performed.

In addition to the above-mentioned prior art, US Pat. No. 3,624,428 and Japanese Patent Publication No. 50-38531 disclose an output circuit of a grounded-emitter resistance load for a transistor in which an electrode is provided on the base through an insulating layer. Is connected, the base is reversely biased to perform the accumulation operation, and the output circuit of the grounded-emitter resistor load reads the current. After all, however, the linearity and the afterimage characteristic are poor because of the destructive type current reading.

[0017]

As described above, the conventional solid-state imaging
The configuration of the device and its problems were described.
The signal from the source is sequentially turned on by the shift register.
A signal readout circuit that reads out to the amplifier via the transistor
The solid-state imaging device that has a signal for one horizontal line
If the read time is fixed, the number of pixels may increase.
The higher the number, the faster it becomes necessary to read the data.
Analog-to-digital conversion of signals for signal processing
Applications require high-speed analog-to-digital converters
There was a problem . [Object of the Invention] The object of the present invention is to achieve high speed with a simple circuit configuration.
To provide a signal processing device capable of performing signal processing.
And in.

[0018]

[Means for Solving the Problems] The same object
Output signals from the multiple optical sensor arrays provided above
In the signal processing device for processing, the plurality of optical sensor
Transfer means for transferring the output signal from the ray,
A shift register connected to the sending means, and the shift register
A plurality of signal processing means provided corresponding to the
The plurality of signal processing means are respectively provided in the plurality of optical sensors.
It is provided for each array and each optical sensor array
The signals transferred from the above are processed in parallel by the signal processing means.
Is achieved by a signal processing device characterized by
It

[0019]

The present invention is based on the output signals from a plurality of photosensor arrays.
Signal processing, each signal is processed by a plurality of signal processing means.
It processes the signals transferred from the sensor array in parallel.
Compared to the case where signal processing is performed by one signal processing means,
Therefore, even at low frequencies,
It is possible to process signals at the same speed.

[0020]

EXAMPLES Examples of preferred embodiments according to the present invention will be described below.
Will be explained in comparison with the case where there is only one signal processing means.
It

FIG . 1 shows a preferred embodiment of the present invention.
FIG. 3 is a circuit configuration diagram of a photoelectric conversion device using a signal processing device.
It The signal processing means is an output transistor 44, a load resistor 4
Includes 5 amplifiers, 3 here
ing. In FIG. 1, each horizontal shift register
MOS transistor controlled by 100, 101, 102
Each row of optical sensors connected to the sensor is an optical sensor array.
Is. FIG. 15 shows a photoelectric converter showing a case where there is one signal processing means.
It is a circuit block diagram of a converter.

In the example embodiment of FIG . 1, three equivalent horizontal
The shift registers 100, 101, 102 are provided and these
Starting pulse to the terminal 103 for applying the starting pulse of
When entering, the 1st column, (n + 1) th column, (2n + 1) th column
(N is an integer, and the number of horizontal picture elements is 3 in this embodiment.
It is n. Output of each sensor cell connected to
Will be read. At the next time, the second column, (n
The +2) th column and the (2n + 2) th column are to be read.
It According to the present invention, the time to read one horizontal line
Is fixed, the horizontal scanning frequency
The number is compared with the method of Fig. 15 with one final stage amplifier.
The frequency can be reduced to 1/3 and the horizontal shift range
From the photoelectric conversion device by means of signal processing means
Analog-to-digital conversion of the output signal of
High-speed analog-to-digital converter is not necessary
It is important that the signal processing apparatus of the present invention uses a divided read method.
Is a great advantage.

In the example embodiment shown in FIG . 1, the equivalent horizontal
It was a system with three shift registers, but a similar machine
Noh can have only one horizontal shift register.
It is possible. An example of an embodiment in this case is shown in FIG.

The embodiment shown in FIG . 2 is the embodiment shown in FIG .
A horizontal switching MOS transistor of the examples,
Only the middle part of the final stage amplifier is written,
1 is the same as the embodiment shown in FIG.
There is.

In this example embodiment, one horizontal shift
The output from the register 104 is the first column, the (n + 1) th column,
Of the switching MOS transistors in the (2n + 1) th column
Connect to the gate and read those lines simultaneously
is doing. At the next time, the second row, the (n + 2) th row,
That is, the (2n + 2) th column is read.

Next, the operation of the photoelectric conversion device shown in FIG.
I will briefly explain about it. Light of photoelectric conversion device shown in FIG.
The electrical conversion operations are accumulation operation, read operation, and refresh operation.
It consists of works. In the following description, for simplification of description, FIG.
Will be explained.

First, referring to FIG . 15 and FIG .
An output circuit is connected to the first main electrode region (emitter) of the photoelectric conversion cell including a transistor as indicated by reference numeral 30 of 15 . This output circuit has a vertical line 38,
38 ', 38 ", horizontal shift register 39, MOS transistors 40, 40', 40", output line 41, MO
S transistor 42, the output transistor 44 is constituted by a load resistor 45 or the like, the vertical lines 38, 38 ', 38 "has a wiring capacitance as Cs, each indicated by reference numeral 21 in FIG. 16 as a capacitive load.

A vertical shift register 32 and buffer MOS transistors 33 and 3 are provided as reading means for reading out a signal photoelectrically converted based on the accumulated charges.
3 ', 33 ", terminals 34, horizontal lines 31, 31', 3
1 "is provided in the circuit configuration.

During the accumulation operation, the emitter is floating or grounded, and the second main electrode region (collector) is biased to a positive potential. The control electrode region (base) is reverse biased with respect to the emitter, and the saturation voltage can be determined by controlling the base potential at this time. Thus, by appropriately setting the bias voltage, the cell itself can have a switching action.

During the read operation, the emitter is brought into a floating state and the collector is biased to a positive potential. The potential of the control electrode region is controlled by the read means independently of the main electrode region. When the base is biased in the forward direction with respect to the emitter, high-speed reading can be performed while ensuring good linearity. The operation at this time will be described with reference to FIG . At the time of reading, a positive voltage V _R is independently applied from the wiring 10 to the floating emitter and the collector held at a positive potential, whereby the base potential is forward biased with respect to the emitter potential. By
The emitter-base junction is deeply biased in the forward direction. In this way, the current flows until the emitter potential becomes equal to the base potential, that is, the storage voltage generated by light irradiation. The time required at this time is further shortened by the action of the voltage V _R , and even in high-speed reading. Therefore, excellent linearity can be secured.

The refresh operation is as follows.

The emitter is connected to the first reference voltage source indicated by the earth symbol by the MOS transistors 48, 48 ', 48 "as switching means and is grounded.
At this time, the collector is connected to the second reference voltage source, that is, the positive potential or the ground potential. Thus, the vertical lines 38, 38 ', 38 "including the capacitive load are reset. The case where the collector is grounded is shown in FIG. 3. In such a state, a voltage of positive potential V _RH is applied. By controlling the electric potential of the base as the control electrode region, at least the base-emitter is forward-biased and holes accumulated in the base region flow out or electrons are accumulated in the base region. The charge disappears.As refresh means for applying such a forward bias, MOS transistors 48, 48 ', 48 ", buffer MOS transistors 35, 35', 35", terminal 3 are provided.
6. It is configured by providing a terminal 37 or the like which serves as a reference voltage source for independently applying the potential V _RH to the base.

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 4 is a diagram for explaining the basic structure and operation of the photosensor cell that constitutes the photoelectric conversion device according to the embodiment of the present invention. 4 (a) is a plan view of the optical sensor cell, FIG. 4 (b) is a cross-sectional view of the AA ′ portion of the plan view of FIG. 4 (a), and FIG. 4 (c) is an equivalent circuit thereof. Show. 4 (a), (b), (c) in each part.
The same numbers are attached to common items.

In FIG. 4, a plan view of the alignment arrangement method is shown, but it is needless to say that the arrangement can also be performed in the pixel shift method (interpolation arrangement method) in order to increase the horizontal resolution.

This optical sensor cell is shown in FIGS. 4 (a) and 4 (b).
As shown in FIG. 3, a passivation film usually made of a PSG film or the like is formed on a silicon substrate 1 which is doped with impurities such as phosphorus (P), antimony (Sb) and arsenic (As) to be an n type or n ⁺ type. The film 2, the insulating oxide film 3 made of a silicon oxide film (SiO ₂ ), the insulating film made of SiO ₂ or Si ₃ N ₄ or the like or the polysilicon film for electrically insulating between the adjacent photosensor cells. The element isolation region 4 formed, the n ⁻ region 5 having a low impurity concentration formed by the epitaxial technique, and the bipolar transistor doped with impurities such as boron (B) using the impurity diffusion technique or the ion implantation technique thereon. p region 6 becomes the base, the impurity diffusion technology, n ⁺ region 7 serving as the emitter of the bipolar transistor formed by the ion implantation technique or the like, the signal for reading to the outside For example, aluminum (A
l), a wiring 8 made of a conductive material such as Al-Si, Al-Cu-Si, etc., an electrode 9 for applying a pulse to the p region 6 in a floating state through the insulating film 3, and its wiring 10. , N having a high impurity concentration formed by an impurity diffusion technique or the like for making ohmic contact with the back surface of the substrate 1.
^{A +} region 11 and an electrode 12 made of a conductive material such as aluminum for giving the potential of the substrate, that is, the collector potential of the bipolar transistor.

Reference numeral 19 in FIG. 4A is a contact portion for connecting the n ⁺ region 7 and the wiring 8. Further, the alternating portions of the wiring 8 and the wiring 10 are so-called two-layer wiring, which are insulated from each other in an insulating region formed of an insulating material such as SiO ₂ . That is, it has a two-layer wiring structure of metal.

Capacitor Cox of the equivalent circuit of FIG. 4 (c)
13 is composed of an electrode 9, an insulating film 3, and a p-region 6 MOS structure, and the bipolar transistor 14 is an n ⁺ region 7 as an emitter, a p region 6 as a base, an n ⁻ region 5 with a low impurity concentration, and a collector. Of n or n ⁺ region 1 of FIG. As is clear from these drawings, the p region 6 is a floating region.

In the second equivalent circuit of FIG. 4C, the bipolar transistor 14 is connected to the base-emitter junction capacitance Cb.
e15, pn junction diode Dbe of base / emitter
16, the junction capacitance Cbc17 of the base-collector, and the pn junction diode Dbc18 of the base-collector. Here, originally as an equivalent circuit diagram,
The symbols indicating the two differently oriented current sources to be written in parallel with the pn junction diode Dbe16 and the pn junction diode Dbc18 are omitted. The basic operation of the optical sensor cell will be described below with reference to FIG. The basic operation of this photosensor cell is composed of a charge accumulation operation by light incidence, a read operation and a refresh operation.

First, the charge accumulation operation will be described.

In the charge storage operation, for example, the emitter is grounded through the wiring 8 and the collector is biased to a positive potential through the wiring 12. In addition, the base is assumed to be in a reverse bias state with respect to the negative potential, that is, the emitter 7 by applying a positive pulse voltage to the capacitor Cox 13 through the wiring 10 in advance. The operation of applying a pulse to the Cox 13 to bias the base 6 to a negative potential will be described in detail later in the description of the refresh operation.

In this state, when light 20 enters from the front side of the photosensor cell as shown in FIG. 4, electron-hole pairs are generated in the semiconductor. Of these, electrons flow out to the n region 1 side because the n region 1 is biased to a positive potential, but holes are gradually accumulated in the p region 6. By accumulating the holes in the p region, the potential of the p region 6 gradually changes toward the positive potential.

In FIGS. 4A and 4B, the lower surface of the light receiving surface of each sensor cell is almost entirely occupied by the p region, and a part of it is n.
⁺ Area 7 As a matter of course, the concentration of electron-hole pairs excited by light is larger as it is closer to the surface. Therefore, many electron-hole pairs are excited in the p region 6 by light. If the photoexcited electrons in the p region immediately flow out from the p region 6 without being recombined and are absorbed in the n region, the holes excited in the p region 6 are accumulated as they are, The p region 6 is changed in the positive potential direction. When the impurity concentration of the p region 6 is made uniform, the photoexcited electrons are diffused and the p region 6 and the n ⁻ region 5 are exposed to the p region.
It flows to the n ⁻ junction, and thereafter is absorbed by the n collector region 1 by the drift due to the strong electric field applied to the n ⁻ region. Of course, the electrons in the p region 6 may travel only by diffusion. However, if the impurity concentration of the p-base decreases from the surface to the inside, this difference in impurity concentration causes , An electric field Ed from the inside to the surface in the base,

[0043]

[Equation 1] Occurs. Here, W _B is the depth from the light incident side surface of the p region 6, k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, N _AS is the surface impurity concentration of the p base region 6, and N _Ai
Is the impurity concentration at the interface between the p region 6 and the n ⁻ high resistance region 5.

Here, if N _AS / N _Ai > 3, the electrons in the p region 6 travel by drift rather than diffusion. That is, in order to effectively operate the carrier excited by light in the p region 6 as a signal,
It is desirable that the impurity concentration of the p-region 6 decreases inward from the surface on the light incident side. If the p-region 6 is formed by diffusion, the impurity concentration thereof decreases toward the inside as compared with the surface on the light incident side.

A part below the light receiving surface of the sensor cell is occupied by the n ⁺ region 7. The depth of the n ⁺ region 7 is normally 0.
Since it is designed to have a thickness of about 2 to 0.3 μm or less, the amount of light absorbed in the n ⁺ region 7 is not so large originally, so there is no problem so much. However, for light on the short wavelength side, particularly for blue light, the presence of the n ⁺ region 7 causes a decrease in sensitivity. The impurity concentration of the n ⁺ region 7 is usually 1 × 1
It is designed to be about 0 ²⁰ cm ^-3 or more. The diffusion distance of holes in the n ⁺ region 7 doped with such a high concentration of impurities is about 0.15 to 0.2 μm. Therefore, in order for the holes photo-excited in the n ⁺ region 7 to effectively flow into the p region 6, it is desirable that the n ⁺ region 7 also has a structure in which the impurity concentration decreases from the light incident surface toward the inside. If the impurity concentration distribution of the n ⁺ region 7 is as described above, a strong drift electric field is generated from the surface on the light incident side toward the inside, and the holes photoexcited in the n ⁺ region 7 are immediately drifted by the p region 6 due to the drift. Flow into. If the impurity concentrations of the n ⁺ region 7 and the p region 6 are both reduced from the light incident side surface toward the inside, the n ⁺ region 7 and the p region existing on the light incident side surface side of the sensor cell All the carriers optically excited in 6 work effectively as an optical signal. If this n ⁺ region 7 is formed by impurity diffusion from a silicon oxide film or a polysilicon film that is heavily doped with As or P, it is possible to obtain an n ⁺ region having the desired impurity gradient as described above. Is.

Finally, the accumulation of holes causes the base potential to change to the emitter potential, and in this case to the ground potential, where it is clipped. More precisely, the base-emitter is deeply biased in the forward direction, and the holes accumulated in the base are clipped by the voltage at which they start flowing out to the emitter. That is, the saturation potential of the photosensor cell in this case is approximately given by the potential difference between the bias potential and the ground potential when the p region 6 is first biased to a negative potential. When the n ⁺ region 7 is not grounded and the charges generated by the light input are accumulated in the floating state, the p region 6 can accumulate the charges to substantially the same potential as the n region 1.

The above is a qualitative outline of the charge accumulation operation, but a little more concrete and quantitative explanation will be given below.

The spectral sensitivity distribution of this optical sensor cell is given by the following equation.

[0049]

[Equation 2] Where λ is the wavelength of light [μm], α is the attenuation coefficient of light [μm ⁻¹ ] in the silicon crystal, and x is the “delaylayer” which causes recombination loss on the semiconductor surface and does not contribute to sensitivity.
The thickness of r ″ (insensitive region) [μm], y is the thickness of the epitaxial layer [μm], T is the transmittance, that is, the incident light amount is effectively incident on the semiconductor in consideration of reflection and the like. The photocurrent Ip is calculated by the following equation using the spectral sensitivity S (λ) and the irradiance Ee (λ) of this photosensor cell.

[0050]

[Equation 3] However, the irradiance Ee (λ) [μW · cm ⁻² · nm ⁻¹ ] is given by the following equation.

[0051]

[Equation 4] However E _V illuminance of the light receiving surface of the sensor [Lux], P (lambda)
Is the spectral distribution of the light incident on the light receiving surface of the sensor, V
(Λ) is the relative luminous efficiency of the human eye. Using these formulas, an optical sensor cell having an epi-thickness layer of 4 μm is illuminated by the A light source (2854 ° K) and the sensor light receiving surface illuminance is 1
In the case of [Lux], a photocurrent of about 280 nA / cm ⁻² flows and the number of incident photons or the number of generated electron-hole pairs is 1.8 × 10 ¹² / cm ² · s.
It is about ec.

At this time, the potential Vp generated by the accumulation of holes excited by light in the base is Vp =
Given by Q / C. Q is the amount of charge of holes accumulated, and C is the junction capacitance obtained by adding Cbe15 and Cbc17.

Now, the impurity concentration of the n ⁺ region 7 is set to 10 ²⁰ cm
^-3 , the p-region 6 has an impurity concentration of 5 × 10 ¹⁶ cm ^-3 , the n ^- region 5 has an impurity concentration of 10 ¹³ cm ^-3 , the n ⁺ region 7 has an area of 16 μm ² , and the p-region 6 has an area of 64 μm ^2. , N ⁻ region 5 having a thickness of 3 μm has a junction capacitance of about 0.014 p
On the other hand, the number of holes accumulated in the F region is 1/60 sec, and the effective light receiving area, that is, the area obtained by subtracting the areas of the electrodes 8 and 9 from the area of the p area 6 is about 56 μm ^2. Then, it becomes 1.7 × 10 ⁴ .
Therefore, the potential Vp generated by the incidence of light is about 190 mV.

It should be noted here that when the resolution is increased and the cell size is reduced, the amount of light incident on one photosensor cell is reduced, and the accumulated charge amount Q
However, since the junction capacitance also decreases in proportion to the cell size as the cell size is reduced, the potential Vp generated by light incidence is kept almost constant. This is because the optical sensor cell in the present invention has an extremely simple structure as shown in FIG. 4 and has a possibility that the effective light receiving surface can be made extremely large.

This is one of the reasons why the photoelectric conversion device of the present invention is advantageous as compared with the case of the interline type CCD. With the increase in resolution, the transfer is performed in the interline type CCD image pickup device. If an attempt is made to secure the charge amount, the area of the transfer portion becomes relatively large, and the effective light-receiving surface is reduced. Also,
In the interline type CCD image pickup device, the saturation voltage is limited by the size of the transfer part and decreases more and more. On the other hand, in the photo sensor cell of the present invention, as described above, Since the saturation voltage is determined by the bias voltage when the p region 6 is biased to a negative potential, a large saturation voltage can be secured.

The operation of reading out the voltage generated by the charges accumulated in p region 6 as described above will be described below.

In the read operation state, the emitter and the wiring 8 are kept in a floating state, and the collector is kept at the positive potential Vcc.

FIG . 16 shows an equivalent circuit. Here again, the pn junction diodes Dbe16 and p are originally equivalent circuits.
The symbols indicating two differently directed current sources to be written in parallel with the n-junction diode Dbc18 are omitted.

Now, assuming that the potential when the base 6 is biased to a negative potential before light irradiation is -V _B and the accumulated voltage generated by light irradiation is V _P , the base potential is -V _B.
+ Has become V _P become potential. When a positive voltage V _R for reading is applied to the electrode 9 through the wiring 10 in this state, this positive potential V _R becomes a capacitance due to the oxide film capacitance Cox13, the base-emitter junction capacitance Cbe15, and the base-collector junction capacitance Cbc7. Split and voltage on the base

[0060]

[Equation 5] Is added. Therefore, the base potential is

[0061]

[Equation 6] Becomes here,

[0062]

[Equation 7] If the condition is satisfied, the base potential becomes the accumulated voltage V _P itself generated by light irradiation. In this way, when the base potential is biased in the positive direction with respect to the emitter potential, electrons are injected from the emitter to the base, and the collector potential is positive, so that the electrons are accelerated by the drift electric field to the collector. To reach. The current flowing at this time is given by the following equation.

[0063]

[Equation 8] Where A _j is the junction area between the base and emitter, q is the unit charge (1.6 × 10 ⁻¹⁹ Coulomb), D _n is the diffusion constant of electrons in the base, and n _pe is the minority carrier at the emitter end of the p base. , W _B is the base width, N _Ae is the acceptor concentration in the base emitter alone, N _Ac is the acceptor concentration at the collector end of the base, k is the Boltzmann constant, T is the absolute temperature,
V _e is the emitter potential.

This current is based on the fact that the emitter potential V _e is the base potential, that is, the accumulated voltage V generated by light irradiation here.
It is clear from the above equation that the current flows until it becomes equal to _P. At this time, the time change of the emitter potential V _e is calculated by the following equation.

[0065]

[Equation 9] However, the wiring capacitance Cs is the capacitance 21 of the wiring 8 connected to the emitter.

FIG. 5 shows an example of the change over time in the emitter potential calculated using the above equation. According to FIG. 5, it takes about 1 second for the emitter potential to become equal to the base potential. This is because the current does not flow so much when the emitter potential V _e approaches V _P. Therefore, the means to solve this is to apply the positive voltage V _R to the electrode 9 first,

[0067]

[Equation 10] Was set, but instead of this condition

[0068]

[Equation 11] It is conceivable to add the following condition and bias the base potential by V _{Bias in} an extra forward direction. The current flowing at this time is given by the following equation.

[0069]

[Equation 12] In FIG. 6, when V _Bias = 0.6V, after a certain period of time, V _R applied to the electrode 9 is returned to zero volt,
For the accumulated voltage V _P when the flowing current is stopped,
The relationship between the read voltage, that is, the emitter potential is shown. However, in FIG. 6, the read voltage is always added with a constant potential that depends on the read time due to the bias voltage component, but the value obtained by subtracting the amount of the error is plotted. Electrode 9
When the positive voltage V _R applied to the

[0070]

[Equation 13] Is added to the base potential, the base potential is in the state before the positive voltage V _R is applied, that is, −V _B.
Then, the current is stopped because the emitter is reverse biased. According to FIG. 6, if a read time of about 100 ns or more (that is, a time during which V _R is applied to the electrode 9) is taken, the linearity is ensured for the accumulated voltage V _P and the read voltage over a range of about 4 digits, and the high speed It can be read. In FIG. 6, the 45 ° line is the result when sufficient time is taken for reading. In the above calculation example, the capacitance Cs of the wiring 8 is set to 4 pF, which is 0.014 pF of the junction capacitance of Cbe + Cbc. It is shown that the accumulated voltage V _P generated in the p region 6 is not attenuated at all and is read at extremely high speed due to the effect of the bias voltage, though it is about 300 times larger than 6 shows. This is because the amplifying function of the photosensor cell according to the above configuration, that is, the charge amplifying function is effectively operating.

On the other hand, in the conventional MOS type image pickup device, the accumulated voltage V _P is Cj · V _P / (Cj + Cs) (where Cj is the MOS type image pickup device due to the influence of the wiring capacitance Cs in such a reading process). The pn junction capacitance of the light receiving portion) occurs, and there is a drawback in that the read voltage value of two digits decreases. Therefore, in the MOS type image pickup device, fixed pattern noise due to variations in the parasitic capacitance of the switching MOS transistor for reading to the outside or random noise generated due to large wiring capacitance, that is, output capacitance is large, and the S / N ratio is high. However, in the photosensor cell having the configuration shown in FIGS. 4A, 4B, and 4C, the accumulated voltage generated in the p region 6 is read out to the outside. Is relatively large, fixed pattern noise and random noise due to output capacitance are relatively small, and it is possible to obtain a signal with a very good S / N ratio.

It has been shown above that when the bias voltage V _Bias is set to 0.6 V, linearity of about 4 digits can be obtained in a high-speed read time of about 100 nsec. This linearity, read time and bias voltage Further _details of the calculation result of the relationship of V _Bias are shown in FIG. 7.

In FIG. 7, the horizontal axis represents the bias voltage V _Bias.
And the vertical axis represents the read time. The parameters show the time dependence until the read voltage reaches 80%, 90%, 95%, 98% of 1 mV when the storage voltage is 1 mV. As shown in FIG. 6, at a storage voltage of 1 mV, 80%, 90%, 95%,
When it is 98%, it is clear that the storage voltage higher than that shows a better value.

According to FIG. 7, when the bias voltage V _Bias is 0.6 V, the read voltage becomes 80% of the accumulated voltage and the read time becomes 0.12 μs, and 90% becomes 0.2.
It can be seen that 7 μs and 95% are 0.54 μs and 98% are 1.4 μs. Further, it is shown that if the bias voltage V _Bias is made larger than 0.6 V, the reading can be performed at higher speed. Thus, once the read time and the required linearity are determined from the overall design of the imaging device, the required bias voltage V _Bias can be determined using the graph of FIG.

Another advantage of the optical sensor cell having the above structure is that holes accumulated in the p region 6 can be read nondestructively because the recombination probability of electrons and holes in the p region 6 is extremely small. is there. That is, when the voltage V _R applied to the electrode 9 at the time of reading is returned to zero volts, the potential of the p region 6 is in the reverse bias state before the voltage V _R is applied, and the accumulated voltage V _P generated by light irradiation is , Unless it is newly irradiated with light, it is stored as it is. This means that when the optical sensor cell according to the above configuration is configured as a photoelectric conversion device, a new function can be provided in terms of system operation.

The time during which the storage voltage V _P can be held in the p region 6 is extremely long, and the maximum holding time is rather limited by the dark current thermally generated in the depletion layer of the junction. That is, the photosensor cell is saturated by the dark current generated thermally. However, in the optical sensor cell according to the above configuration, the region where the depletion layer spreads is the n ⁻ region 5 which is a low impurity concentration region, and this n ⁻ region 5 is about 10 ¹² cm ⁻³ to 10 ¹⁴ cm ^−3. Since the impurity concentration is extremely low, the crystallinity is good, and there are few electron-hole pairs that are thermally generated, as compared with the MOS type and CCD type image pickup devices. For this reason, the dark current is small compared to other conventional devices. That is, the photosensor cell according to the above-mentioned configuration has a structure in which dark current noise is essentially small.

Next, the operation of refreshing the charges accumulated in p region 6 will be described.

In the photosensor cell having the above structure, as already described, the charge accumulated in the p region 6 does not disappear in the reading operation. Therefore, in order to input new optical information, a refresh operation for extinguishing the previously accumulated charges is necessary. At the same time, the potential of the p region 6 in the floating state needs to be charged to a predetermined negative voltage. In the optical sensor cell according to the above configuration,
Similar to the read operation, the refresh operation is performed by applying a positive voltage to the electrode 9 through the wiring 10. At this time, the emitter is grounded through the wiring 8. The collector is
It is grounded or made to have a positive potential through the electrode 12. FIG. 3 shows an equivalent circuit of the refresh operation. However, an example is shown in which the collector side is grounded.

When a voltage of positive voltage V _RH is applied to the electrode 9 in this state, the base film 22 has an oxide film capacitance Cox1.
3, base-emitter junction capacitance Cbe15, base
By dividing the junction capacitance Cbc17 between collectors,

[0080]

[Equation 14] Is applied instantaneously as in the previous read operation. Due to this voltage, the base-emitter junction diode Dbe16 and the base-collector junction diode Dbc18 are forward biased to be in a conductive state, current starts to flow, and the base potential gradually decreases.

At this time, the change in the potential V of the base in the floating state is approximately represented by the following equation.

[0082]

[Equation 15] However,

[0083]

[Equation 16] i ₁ is a current flowing through the diode Dbc, and i ₂ is a current flowing through the diode Dbe. A _b is the base area, Ae
Is the emitter area, Dp is the diffusion constant of holes in the collector, p _ne is the hole concentration in the collector in the thermal equilibrium state, Lp is the mean free path of the holes in the collector, and n _pe is the electron concentration in the base in the thermal equilibrium state. is there. At i ₂ , the current due to hole injection from the base side to the emitter can be ignored because the emitter impurity concentration is sufficiently higher than the base impurity concentration.

The above equation is a gradual-junction approximation, which is deviated from the gradual-junction in an actual device, and the base has a small thickness and has a complicated concentration distribution. However, the refresh operation can be explained with a good approximation.

Of the current i ₁ flowing between the base and collector in the above equation, q · Dp · p _ne / Lp is the current due to holes,
That is, it shows the component in which holes flow from the base to the collector side. In the photosensor cell according to the above configuration, the impurity concentration of the collector is designed to be slightly lower than that of a normal bipolar transistor so that the current due to the holes easily flows.

FIG. 8 shows an example of the time dependence of the base potential calculated using this equation. The horizontal axis represents the time elapsed from the moment when the refresh voltage V _RH was applied to the electrode 9, that is, the refresh time, and the vertical axis represents the base potential. Also, the initial potential of the base is used as a parameter. The initial potential of the base is a potential indicated by the base in a floating state at the moment when the refresh voltage V _RH is applied, and is determined by V _RH , Cox, Cbe, Cbc and the electric charge accumulated in the base.

Referring to FIG. 8, the potential of the base does not depend on the initial potential, but always drops according to one straight line on the semi-logarithmic graph after a certain period of time.

FIG. 9 shows experimental values of changes in base potential with respect to refresh time. Compared to the calculation example shown in FIG. 8, the test device used in this experiment has a considerably large dimension, so the absolute value does not match the calculation example, but the change in the base potential with respect to the refresh time is on a semi-logarithmic graph. It is proved that it is changing linearly. In this experimental example, values are shown when both the collector and the emitter are grounded.

Now, assuming that the maximum value of the accumulated voltage V _P due to light irradiation is 0.4 [V] and the voltage V applied to the base by the refresh voltage V _RH is 0.4 [V], as shown in FIG. The maximum value of the initial base potential is 0.8 [V], and after 10 ^-15 [sec] after the refresh voltage is applied, the base potential starts to drop in a straight line, and after 10 ^-5 [sec], light is emitted. When there is not, that is, when the initial base potential is 0.4 [V], it matches the potential change.

There are two ways in which the p region 6 is applied with a positive voltage through the MOS capacitor Cox for a certain period of time and is charged to a negative potential when the positive voltage is removed. One is an operation in which negative charges are accumulated by the holes having a positive charge flowing out from the p region 6 to the n region 1 which is mainly in the grounded state. In order to prevent holes from unilaterally flowing from the p region 6 to the n region 1 and electrons in the n region 1 from flowing into the p region 6 too much, the impurity density of the p region 6 is set to the impurity density of the n region 1. It should be higher.
On the other hand, electrons from the n ⁺ region 7 and the n region 1 flow into the p region 6 and recombine with holes, so that the p region 6
The operation of accumulating negative charges can also be performed. In this case, the impurity density of n region 1 is higher than that of p region 6. p
The operation of accumulating negative charges due to the outflow of holes from the region 6 is much faster than the operation of accumulating negative charges due to electrons flowing into the base of the p region 6 and recombining with holes. However, according to the experiments performed so far, it has been confirmed that even the refresh operation of injecting electrons into the p region 6 exhibits a sufficiently fast time response to the operation of the photoelectric conversion device.

When a large number of optical sensor cells having the above structure are arranged in the XY directions to form a photoelectric conversion device, the accumulated voltage V _{P in} each sensor cell is 0 to 0 in the above example.
Although it varies between 0.4 [V], a constant voltage of about 0.3 [V] remains at the bases of all the sensor cells at 10 ⁻⁵ [sec] after the refresh voltage V _{RH is} applied. It can be seen that all the changes in the accumulated voltage V _P due to the image disappear. That is, in the photoelectric conversion device using the optical sensor cell according to the above configuration, the complete refresh mode in which the base potentials of all the sensor cells are brought to zero volts by the refresh operation (at this time, 10 [sec] is required in the example of FIG. 8), There are two transient refresh modes in which a certain constant voltage remains in the base potential, but the fluctuation component due to the accumulated voltage V _P disappears (in this case, 10 [μsec] to 1 in the example of FIG. 8).
0 [sec] refresh pulse). In the above example,
The voltage V applied to the base by the refresh voltage V _{RH
Although A} was set to 0.4 [V], this voltage V _A was set to 0.6
[V], the transient refresh mode is
According to FIG. 8, it occurs in 1 [nsec], and refreshing can be performed at an extremely high speed. The selection of whether to operate in the complete refresh mode or the transient refresh mode is determined by the purpose of use of the photoelectric conversion device.

When the voltage remaining in the base in this transient refresh mode is V _K , the refresh voltage V _RH
In the transient state at the moment of returning V _RH to zero volt after applying

[0093]

[Equation 17] Since the negative voltage is added to the base, the base potential after the refresh operation by the refresh pulse is

[0094]

[Equation 18] And the base is reverse biased with respect to the emitter.

It has been explained above that the base is reverse biased in the storage state during the storage operation for storing the carriers excited by light. By this refresh operation, the refresh and the base are held in the reverse bias state. The two operations of going forward are performed at the same time.

FIG. 10 shows the base potential after the refresh operation with respect to the refresh voltage V _RH .

[0097]

[Formula 19] The experimental value of change of is shown. The value of Cox is taken as a parameter from 5 pF to 100 pF. Circles are experimental values, solid lines are

[0098]

[Equation 20] The calculation value calculated by the above is shown. At this time V _K =
It is 0.52 V and Cbc + Cbe = 4 pF. However, the probe capacity of the observation oscilloscope is 13 pF
Are connected in parallel to Cbc + Cbe. Like this
The calculated value and the experimental value are completely in agreement, and the refresh operation has been confirmed experimentally.

In the above refresh operation, FIG.
As described above, an example in which the collector is grounded has been described, but it is also possible to perform it in a state where the collector is at a positive potential. At this time, even if the refresh pulse is applied to the base-collector junction diode Dbc18,
If the positive potential applied to the collector is higher than the potential applied to the base by this refresh pulse, the current remains in the non-conducting state, so that the current flows only through the base-emitter junction diode Dbe16. For this reason, the decrease in the base potential becomes relatively slower than when the collector is grounded, but basically, exactly the same fast refresh operation as described above is performed.

That is, the relationship of the base potential with respect to the refresh time in FIG. 8 is that the oblique straight line when the base potential in FIG. 8 decreases shifts toward the right side, that is, in the direction requiring more time. Therefore, if the same refresh voltage V _RH as when the collector is grounded is used, it takes time to refresh, but if the refresh voltage V _RH is raised slightly, a high-speed refresh operation can be performed similarly to when the collector is grounded. It is possible. The above is the description of the basic operation of the photosensor cell having the above-described configuration, which includes the charge accumulation operation, the read operation, and the refresh operation by light incidence.

As described above, the basic structure of the optical sensor cell having the above-mentioned structure is the same as that of the above-mentioned JP-A-56-15.
It has a very simple structure as compared with JP 0878, JP 56-157073, and JP 56-165473, and can sufficiently cope with future high resolution, and has excellent features. The advantages such as low noise, high output, wide dynamic range, and nondestructive readout that come from a certain amplification function are preserved.

[0102] will be described with reference to the accompanying drawings, an embodiment of a photoelectric conversion device according to the present invention constructed by arranging the photosensor cell in two dimensions according to the configuration described above. First, the book
Prior to the description of the embodiments of the invention, one signal processing means is described.
Taking the case as an example, the configuration of the photoelectric conversion device according to the present invention and
And operation will be described.

The basic optical sensor cell structure is two-dimensionally 3 × 3.
FIG . 15 shows a circuit configuration diagram of the photoelectric conversion device arranged in the above.

The basic photosensor cell 30 (the collector of the bipolar transistor is shown to be connected to the substrate and the substrate electrode at this time) surrounded by the dotted line, which has already been described, and the horizontal for applying the read pulse and the refresh pulse. Lines 31, 31 ', 31 ", vertical shift register 32 for generating read pulses, vertical shift register 32 and horizontal lines 31, 31', 31"
Between the buffer MOS transistors 33, 33 ', 3
A terminal 34 for applying a pulse to the gate of 3 ", buffer MOS transistors 35, 35 ', 35" for applying a refresh pulse, a terminal 36 for applying a pulse to its gate, and a refresh pulse 37, a vertical line 38, 38 ', 38 "for reading the accumulated voltage from the basic photosensor cell 30, a horizontal shift register 39 for generating a pulse for selecting each vertical line, and opening / closing each vertical line. Gate MOS transistors 40, 40 ', 40 "for output, an output line 41 for reading the accumulated voltage to the amplifier section,
M for refreshing the charge accumulated in the output line
OS transistor 42, terminal 43 for applying a refresh pulse to MOS transistor 42, bipolar for amplifying an output signal, MOS, FET, J-FE
A transistor 44 such as T, a load resistor 45, a terminal 46 for connecting the transistor and a power supply, an output terminal 47 of the transistor, and vertical lines 40 and 4 in the read operation.
MOS transistors 48, 48 ', 48 "for refreshing the charges accumulated in 0', 40", and M
This photoelectric conversion device is constituted by a terminal 49 for applying a pulse to the gates of the OS transistors 48, 48 ', 48 ".

[0105] will be described with reference to the pulse timing diagram illustrating the operation of the photoelectric conversion device in Figs. 15 and 11. In FIG. 11, section 61 corresponds to the refresh operation, section 62 corresponds to the accumulation operation, and section 63 corresponds to the read operation.

At time t ₁ , the substrate potential, that is, the collector potential 64 of the photosensor cell portion is kept at the ground potential or the positive potential, but FIG. 11 shows that it is kept at the ground potential. Whether it is the ground potential or the positive potential, as described above, the time required for refreshing is different, and the basic operation does not change. The potential 65 at the terminal 49 is high, the MOS transistors 48, 48 ', 48 "are kept conductive, and each photosensor cell is grounded through the vertical line 38, 38', 38". Further, a voltage for conducting the buffer MOS transistor is applied to the terminal 36 as shown by a waveform 66, and the buffer MOS transistors 35, 35 ', 35 "for all-screen batch refresh are in a conductive state. When a pulse such as waveform 67 is applied to 37, a voltage is applied to the bases of the respective photosensor cells through the horizontal lines 31, 31 ', 31 ", and as described above, the refresh operation is started and the charge is accumulated before that. Charge is refreshed according to the complete refresh mode or the transient refresh mode. Whether to enter the complete refresh mode or the transient refresh mode is determined by the pulse width of the waveform 67.

At time t ₂ , as already described, the base of the transistor of each photosensor cell is reverse biased with respect to the emitter, and the operation proceeds to the next accumulation section 62. In the refresh section 61, as shown in the figure, all the other applied pulses are kept in the low state.

In the accumulation operation section 62, the substrate voltage,
That is, the collector potential waveform 64 of the transistor is set to a positive potential. As a result, electrons of the electron-hole pairs generated by the light irradiation can quickly flow to the collector side. However, maintaining the collector potential at a positive potential is not an essential condition because the base is reverse-biased with respect to the emitter, that is, the image is taken as a negative potential. There is no change in the accumulation operation.

In the accumulation operation state, the potential 65 of the gate terminals 49 of the MOS transistors 48, 48 ', 48 "is 65.
Is kept high as in the refresh period, and each M
The OS transistor remains conductive. For this reason, the emitter of each photosensor cell has vertical lines 38, 38 ', 3
It is grounded through 8 ″. When strong light is irradiated and holes are accumulated in the base and become saturated, that is, when the base potential becomes a forward bias state with respect to the emitter potential (ground potential), The holes are vertical lines 38,
38 ', 38 ", where the base potential change ceases and is clipped. Therefore, the emitters of vertically adjacent photosensor cells are commonly connected by vertical lines 38, 38', 38". Even
When the vertical lines 38, 38 ', 38 "are grounded in this manner, the blooming phenomenon does not occur.

A method for avoiding this blooming phenomenon is M
Even when the OS transistors 48, 48 ', 48 "are in the non-conducting state and the vertical lines 38, 38', 38" are in the floating state, the substrate potential, that is, the collector potential 64 is set to a slightly negative potential and the hole This can also be achieved by allowing the base potential to flow toward the collector side before the emitter when the base potential changes in the positive potential direction due to the accumulation. After the accumulation section 62, the reading section 63 starts from time t ₃ . At this time t ₃ , the potential 65 of the gate terminal 49 of the MOS transistors 48, 48 ′, 48 ″ is set to low, and the horizontal lines 31, 31 ′, 3
1 ″ buffer MOS transistors 33, 33 ′, 3
The potential 68 of the gate terminal of 3 ″ is set high, and the respective MOS transistors are made conductive. However, the timing of setting the potential 68 of the gate terminal 34 high is not a prerequisite that it is time t ₃ , Any time earlier than that is fine.

At time t ₄ , of the outputs of the vertical shift register 32, the one connected to the horizontal line 31 has the waveform 6
As indicated by reference numeral 9, the MOS transistor 33 is conductive at this time, so that the reading of each of the three photosensor cells connected to the horizontal line 31 is performed. This read operation is as previously described,
The signal voltage generated by the signal charge accumulated in the base region of each photosensor cell is directly applied to the vertical lines 38, 3
8 ', 38 ". The pulse width of the pulse voltage from the vertical shift register 32 at this time is such that the read voltage with respect to the storage voltage maintains a sufficient linearity as shown in FIGS. The pulse voltage is set, and the pulse voltage is adjusted so that the emitter is forward biased by V _{Bias as} described above.

Next, at time t ₅ , of the outputs of the horizontal shift register 39, only the output to the gate of the MOS transistor 40 connected to the vertical line 38 has the waveform 7
It becomes high as 0, the MOS transistor 40 becomes conductive, and the output signal passes through the output line 41.
It enters the output transistor 44, is current-amplified, and is output from the output terminal 47. After the signal is read in this way, signal charges due to the wiring capacitance remain in the output line 41, so at time t ₆ , the MOS transistor 42 is discharged.
A pulse is applied to the gate terminal 43 as in the pulse waveform 71, the MOS transistor 42 is made conductive, the output line 41 is grounded, and the remaining signal charge is refreshed. In the same manner, the switching MOS transistors 40, 40 ', 40 "are sequentially turned on to read the signal output of the vertical lines 38, 38', 38". After reading the signals from the photosensor cells for one line arranged horizontally in this way, the vertical lines 38, 3 are read.
Similar to the output line 41, signal charges due to the wiring capacitance of the output line 41 remain in 8'and 38 ", so that the MOS transistors 48 and 48 'connected to the vertical lines 38, 38' and 38" are connected. , 48 ″ is made high to its gate terminal 49 as shown by the waveform 65 to make it conductive, and this residual signal charge is refreshed.

Next, at time t ₈ , of the outputs of the vertical shift register 32, the output connected to the horizontal line 31 ′ becomes high as shown by the waveform 69 ′, and the accumulation of each photosensor cell connected to the horizontal line 31 ′. The voltage is read out to each vertical line 38, 38 ', 38 ". Thereafter, the signal is read out from the output terminal 47 by the same operation as before.

In the above description, the application field in which the accumulation section 62 and the reading section 63 are clearly divided, for example, the operation state applied to the still video which has been actively researched and developed recently has been described. However, it can be applied to an application field in which the operation in the accumulation section 62 and the operation in the reading section 63 are simultaneously performed, such as a television camera, by changing the pulse timings in FIGS. 11 and 12. However, the refreshing at this time is not a full screen batch refresh, but a refresh function for each line is required. For example, after the signal of each photosensor cell connected to the horizontal line 31 is read, the time t
MOS transistors 48, 48 'for erasing charges remaining in the vertical line at _7, to conduct 48 ", applying a refresh pulse to the horizontal line 31 at this time. That is, even at the time t ₇ in the waveform 69 This can be achieved by using a vertical shift register configured to generate pulses having different pulse voltages and pulse widths as at time t _{4. Thus} , except for the double pulse operation, the right side of FIG. Instead of the device for applying the batch refresh pulse installed in the above, a second vertical shift register similar to the one on the left side may be provided on the right side, and the timing may be achieved by shifting the timing from the vertical register provided on the left side. It is possible.

At this time, the degree of freedom in the operation of suppressing the blooming by operating the respective potentials of the emitter and collector of each photosensor cell in the accumulation state as described above is reduced. However, as it has been explained in the basic operation, the read state, since the such a structure can high-speed reading at the time of applying a V _Bias becomes bias voltage to the base, as can be seen from the graph of FIG. 5, V _Bias Vertical line 2 due to saturation of each photosensor cell when no voltage is applied.
The amount of signal charges flowing out to 8, 28 ', 28 "is extremely small, and the blooming phenomenon does not pose any problem.

Also, with respect to the smear phenomenon, the photoelectric conversion device according to the present embodiment can obtain extremely excellent characteristics. The smear phenomenon is a problem that occurs in operation and structure in which charge is transferred where light is irradiated in a CCD type image pickup device, particularly in a frame transfer type,
In the interline type, a problem particularly occurs because carriers generated in the deep portion of the semiconductor due to long wavelength light are accumulated in the charge transfer portion.

Further, in the MOS type image pickup device, there is a problem that carriers generated in the semiconductor deep portion are accumulated by the light of the long wavelength on the drain side of the switching MOS transistor which is grounded to each photosensor cell.

On the other hand, in the photoelectric conversion device according to the present configuration example, there is no smear phenomenon that occurs due to operation and structure, and there is also a phenomenon that carriers generated in the semiconductor deep portion are accumulated due to long wavelength light. Absent. However, among the electrons and holes generated relatively near the surface of the emitter of the photosensor cell, there is concern about the development that electrons are accumulated. This is because the emitter is grounded in the accumulation operation state during the batch refresh operation. Therefore, the electrons are not accumulated,
Smear phenomenon does not occur. Further, in the line refresh operation applied to a normal TV camera, the vertical line is grounded and refreshed before reading the accumulated voltage in the vertical line during the horizontal blanking period.
At this time, at the same time, the electrons accumulated in the emitter during one horizontal scanning period flow out, so that the smear phenomenon hardly occurs. As described above, in the photoelectric conversion device according to the present embodiment, the smear development occurs only to an essentially negligible degree in terms of its structure and operation, which is one of the great advantages of the photoelectric conversion device according to the present embodiment. Is one.

Further, the operation of suppressing the blooming phenomenon by operating the respective potentials of the emitter and the collector in the accumulation operation state has been described above, but it is also possible to control the γ characteristic by utilizing this.

That is, during the accumulation operation, the potential of the emitter or collector is temporarily set to a certain negative potential, and the number of holes accumulated in the base is larger than the number of carriers giving this negative potential. Is made to flow to the emitter or collector side. As a result, the relationship between the accumulated voltage and the incident light quantity is γ = 1 of the silicon crystal when the incident light quantity is small.
The characteristic is such that γ is smaller than 1 at a place where the amount of incident light is large. That is, it is possible to give the characteristic of γ = 0.45 which is usually required for a television camera in a polygonal line approximation. If the above operation is performed once in the middle of the accumulation operation, it becomes a one-line approximation, and if the negative potential applied to the emitter or the collector is appropriately changed twice, a two-line type γ characteristic can be provided.

Further, in the above configuration example , the silicon substrate is used as a common collector, but it is also possible to provide a buried n ⁺ region like a bipolar transistor and divide the collector for each line.

In addition to the pulse timing shown in FIG. 11, a clock pulse for driving the vertical shift register 32 and the horizontal shift register 39 is necessary for the actual operation.

FIG. 13 shows an equivalent circuit related to the output signal. The capacitance C _V 80 is the wiring capacitance of the vertical lines 38, 38 ′, 38 ″, and the capacitance C _H 81 is the wiring capacitance of the output line 41. The equivalent circuit on the right side of FIG. And M for switching
OS transistor 40, 40 ', 40 "is conductive, indicating a resistance value in its conductive state by a resistor R _M 82. The resistance of the amplification transistor 44 r _e 83
And an equivalent circuit using the current source 84. The MOS transistor 42 for refreshing the charge accumulation due to the wiring capacitance of the output line 41 is in a non-conducting state in the read state and has a high impedance, so that it is omitted in the equivalent circuit on the right side.

Each parameter of the equivalent circuit is determined by the size of the photoelectric conversion device actually configured. For example, the capacitance C _V 80 is about 4 pF, and the capacitance C _H 81
Is about 4 pF, and the resistance R of the conductive state of the MOS transistor
FIG. 14 shows an example in which the output signal waveform observed at the output terminal 47 is calculated assuming that _M 82 is about 3 KΩ and the current amplification factor β of the bipolar transistor 44 is about 100.

In FIG. 14, the horizontal axis represents the switching MOS.
The vertical axis represents the time [μs] from the moment when the transistors 40, 40 ', 40 "are turned on, and the vertical axis represents the vertical lines 38, 38', 3
The output voltage [V] that appears at the output terminal 47 when the signal charge is read from each photosensor cell and a voltage of 1 volt is applied to the wiring capacitance C _V 80 of 8 ″ is shown.

The output signal waveform 85 shows that the load resistance R _E 45 is 1
0KΩ, 86 is when the load resistance R _E 45 is 5KΩ, and 87 is when the load resistance R _E 45 is 2KΩ. In both cases, the peak value is about 0.5V due to the capacitance division of C _V 80 and C _H 81. It has become. As a matter of course, the larger the load resistance R _E 45 is, the smaller the attenuation amount is, and the desired output waveform is obtained. The rise time is as fast as about 20 nsec with the above parameter values. By reducing the resistance R _M of the switching MOS transistors 40, 40 ′ and 40 ″ in the conductive state and the wiring capacitances C _V and C _H , it is possible to read data at a higher speed.

In the photoelectric conversion device using the optical sensor cell having the above structure, since the voltage appearing at the output is large due to the amplification function of each optical sensor cell, the amplification amplifier at the final stage is considerably larger than that of the MOS type image pickup device. A simple one will do. In the above-mentioned example, the example of using the one-stage type of bipolar transistor has been described, but it goes without saying that other methods such as a two-stage type can be used. When a bipolar transistor is used as in this example, the problem of 1 / f noise, which is easily noticeable on the image and is generated from the MOS transistor of the amplifier at the final stage in the CCD image pickup device, does not occur in the photoelectric conversion device of this embodiment. It is possible to obtain an image quality with an extremely good S / N ratio.

Another example of the configuration of the photoelectric conversion device of the present invention will be described below. This configuration example is intended to solve the inconvenience in the transient refresh mode.

FIG. 12 shows potential levels in the emitter, base, and collector sections during the cyclic refresh operation, accumulation operation, read operation, and transient refresh operation. The voltage level of each part is the potential seen from the outside, and there is a part that does not coincide with the internal potential level.

To simplify the explanation, the diffusion potential between the emitter and the base is omitted. Therefore, when the emitter and the base are represented at the same level in FIG.

[0131]

[Equation 21] There is a diffusion potential given by.

In FIG. 12, state represents a refresh operation, state represents a storage operation, state represents a read operation, and state represents an operating state when the emitter is grounded. Regarding the potential level, the upper side shows a negative potential and the lower side shows a positive potential with 0 V as a boundary. It is assumed that the base potential before the state is zero volt and that the collector potential is biased to the positive potential from the state.

The above series of operations will be described with reference to the timing chart of FIG.

As shown by the waveform 67 in FIG. 11, at time t ₁ , a positive potential, that is, the refresh voltage V _RH is applied to the terminal 37.
Is applied to the base as in the state of FIG.

[0135]

[Equation 22] Partial pressure is applied. This potential gradually decreases toward the zero potential from time t ₁ to t ₂ , and becomes the potential 201 shown by the dotted line in FIG. 12 at time t ₂ . This potential is the potential V _K remaining at the base in the transient refresh mode, as described above. At time t ₂ , as shown in the waveform 67, the base voltage is applied to the base at the moment when the refresh voltage V _RH returns to zero voltage.

[0136]

[Equation 23] Since the generated voltage is generated by the capacitance division as before, the base becomes the potential obtained by adding the remaining voltage V _K and the newly generated voltage. That is, the base potential 202 shown in the state, which is

[0137]

[Equation 24] Given in.

When light enters the emitter in the reverse bias state, holes generated by the light are accumulated in the base region.
The base potential 202 gradually changes to a positive potential like the base potentials 203, 203 ', and 203 "according to the intensity of the incident light. The voltage generated by this light is V _P
And

Next, as shown by the waveform 69, a voltage is applied to the horizontal line from the vertical shift register, that is, the read voltage V _R.
Is applied to the base

[0140]

[Equation 25] Is added, the base potential 204 when no light is emitted is

[0141]

[Equation 26] Becomes The potential 204 at this time is, as described above,
It is set so as to be biased in the forward direction by about 0.5 to 0.6 V with respect to the emitter. Also, the base potential 20
5, 205 ', 205 "are each

[0142]

[Equation 27] Given in.

The base potential is thus relative to the emitter
When forward biased, electrons are injected from the emitter side, and the emitter potential gradually moves in the positive potential direction. The emitter potential 206 with respect to the base potential 204 when light is not irradiated is about 50 to 100 mV when the read pulse width is about 1 to 2 μs when the forward bias is set to 0.5 to 0.6 V. , If this voltage is V _B , the emitter potentials 207, 2
07 'and 207 "have sufficient linearity as long as the pulse width is 0.1 μs or more as in the previous example.
_P + V _B , V _P ′ + V _B , and V _P ″ + V _B.

After a certain read time, when the read voltage V _R becomes zero potential as shown by the waveform 69, the base has no potential.

[0145]

[Equation 28] Therefore, the base potential becomes the state before the read pulse is applied, that is, the reverse bias state as in the state, and the potential change of the emitter is stopped. That is, the base potential 208 at this time is

[0146]

[Equation 29] The base potentials 209, 209 'and 209 "are respectively

[0147]

[Equation 30] Given in. This is exactly the same as before reading was started.

In this state, the optical information signal on the emitter side is read out to the outside. After this reading is completed, each switching MOS transistor 48, 4
8 ′ and 48 ″ are in a conductive state, and the emitter is grounded, so that the emitter has a zero potential.
The refresh operation, the accumulation operation, and the read operation make a round, and then the state returns to the next state. At this time, before the first refresh operation, the base potential started from zero potential, but it made one round. After that the base potential

[0149]

[Equation 31] And the respective potentials have changed to V _P , V _P ′, and V _P ″. Therefore, in this state, even if the refresh voltage V _RH is applied, the base potential is V _K. , V _K + V _P , V _K + V _P ′,
V _K + V _P ″, which does not apply a sufficient forward bias to the base, and the amount of forward bias is large where the light hits strongly, but the optical information disappears.
It is obvious from the calculation example of the refresh operation shown in FIG. 8 that the information of the weak light portion remains without disappearing.

Such a phenomenon is peculiar to the transient refresh mode, and in the complete refresh mode, such a problem does not occur because it takes a long refresh time until the base potential always becomes zero potential.

A method of using the transient refresh mode capable of high-speed refresh and avoiding such inconvenience will be described below.

One way to solve this is that the base potential 210 is in the negative potential direction in the state, that is, in the reverse bias direction with respect to the emitter.
In the next state, it suffices to bring the base potential 210 to the zero potential or a slightly positive potential by some method before the refresh pulse is applied.

FIG. 24 (a) is a sectional view of an optical sensor cell for achieving this, and FIG. 24 (b) is an equivalent circuit diagram thereof.
The internal potential diagrams are shown in (c). Figure 24
(A) differs from the sensor cell shown in FIG. 4 only in that it has a buried p ⁺ region 220. In the equivalent circuit diagram of FIG. 24B, the base region 6 of the sensor cell is the collector, the buried p ⁺ region 220 is the emitter, and a part of the high resistance n ⁻ region 5 between the base region 6 and the collector region 1 is the base. The pnp transistor 221 is added. The base region of the pnp transistor is loosely coupled with the collector region 1 of the sensor cell, and is shown by a dotted line in the equivalent circuit. Also, this buried p ⁺ region 2
20 is connected inside the crystal like a wiring 222,
It has a structure that voltage can be applied from outside the sensor area.

As is apparent from FIG. 24B, the p ⁺ buried region 220 forms one line in the horizontal line direction as indicated by 222, so in reality,
In FIG. 24 (a), it should be shown as a p ⁺ buried region continuously connected to the left and right. In FIG. 24A, a p ⁺ region is schematically shown in a part for the sake of clarity.

The potential for the internal electrons is as shown in FIG. 24C, and the buried p ⁺ region 22 is used.
The potential distribution in the vertical cross section that does not include 0 is no different from that shown in FIG. 12, but the potential distribution in the vertical cross section that includes the embedded p ⁺ region 220 has the potential distribution as indicated by the dotted line 223. ing. However, in this figure, the potential distribution is shown when the buried p ⁺ region 220 is biased to a slightly positive potential. In this state, the embedded p
^{When the +} region 220 is further biased in the positive potential direction, the n ⁻ region existing between them is completely punched through,
Holes flow into the base region 6 of the sensor cell from the p ⁺ region, and the potential of the base region 6 moves in the positive potential direction due to the holes.

Punch through the n ^- region and p ⁺
To pour holes from region 220 into the p base region,
When the thickness d of the n ⁻ region, the impurity density N, and the voltage applied to the p ⁺ region 220 are V _P ⁺

[0157]

[Equation 32] Design like. V _bi is the diffusion potential of the p ⁺ n ⁻ junction.

Therefore, in the state of FIG. 12, a positive voltage is applied to the embedded p ⁺ region 220 through the wiring 222 to inject holes into the p base region, so that the base potential 210 is zero as described above. By bringing the potential or a slightly positive potential, it is possible to solve the disadvantageous phenomenon in the transient refresh mode. At this time, the voltage applied to the embedded p ⁺ region 220 is slightly smaller than the voltage applied to the sensor cell collector 1, that is, the embedded p ⁺ region 220 and the collector n.
It is possible to sufficiently pass holes into the base region 6 in a state where the region 1 is not forward biased.

Impurities forming the p ⁺ region (usually boron)
Generally has a large diffusion constant, and problems of autodoping and diffusion occur when the high resistance n ⁻ region 5 is formed by using the epitaxial technique. However, due to the low temperature of the epitaxial technique, the autodoping from the buried p ⁺ region is caused. And a device is made to suppress diffusion as much as possible.

The above-mentioned one configuration example is different only in that the buried p ⁺ region is added to the basic photosensor cell by diffusion or ion implantation as described above, and the method of forming the subsequent portion may be exactly the same.

FIG. 25 shows a sectional view of an optical sensor cell for explaining another configuration example. In the sectional view shown in FIG. 25, when the base region 6 is formed instead of the buried p ⁺ region 220 shown in FIG.
It has a structure to make 24. This P region 224 serves as an emitter, the low impurity n ⁻ region 5 serves as a base, and the base 6 of the photosensor cell serves as a collector to form a pnp transistor. This is because the pnp transistor having the vertical structure is formed as shown in FIG. 24, whereas the pnp transistor having the horizontal structure is formed. Therefore, in the configuration example of FIG. 25, the voltage is supplied to P region 224 through wiring 225 on the front surface side.

The equivalent circuit of the configuration example shown in FIG.
Although the pnp transistor has a vertical structure and a horizontal structure, it is exactly the same as the equivalent circuit shown in FIG. 24B, and its operation is also exactly the same as that already described.

In the cross-sectional view shown in FIG. 25, p ⁺ region 22
4. The wiring 225 thereof is shown in the same cross section as the MOS capacitor electrode 9, the emitter region 7 and the wiring 8 for the sake of explanation, but they can be arranged in other parts of the same photosensor cell. This is determined by design factors such as the shape of the window on which light is incident and the wiring.

As described above, in the photoelectric conversion device using the optical sensor cell according to the above-mentioned configuration, the final stage amplification amplifier may be extremely simple. Therefore, only one final stage amplification amplifier is provided . Instead of the type as shown in 15, it is preferable to employ a configuration in which a plurality of amplification amplifiers are installed and one screen is divided into a plurality of pieces and read out as in the present invention.
Can be used for.

FIG . 1 shows an example of a division read method by the signal processing device of the present invention . The embodiment shown in FIG. 1 is an example in which the horizontal direction is divided into three and three final stage amplifiers are installed.
The basic operation is almost the same as that described using the configuration example of FIG . 15 and the timing diagrams of FIGS. 11 and 12, but in the embodiment of FIG. 1 , three equivalent horizontal shift registers 100 and 101 are provided. , 102, and when the start pulse is applied to the terminal 103 for applying these start pulses, the first column, the (n + 1) th column, and the (2n + 1) th column (n is an integer, and in this embodiment, the horizontal The output of each sensor cell connected to the direction picture element number is 3n). At the next time, the second row, (n + 2)
The second and (2n + 2) th columns will be read. According to this embodiment, when the time for reading one horizontal line is fixed, the scanning frequency in the horizontal direction is 1/3 as compared with the system with one final stage amplifier.
, The horizontal shift ranger becomes simpler,
In addition, a high-speed analog-to-digital converter is not necessary for applications such as analog-to-digital conversion of output signals from the photoelectric conversion device and signal processing, which is a great advantage of the divided read method.

In the embodiment shown in FIG . 1 , three equivalent horizontal shift registers are provided, but a similar function can be provided by only one horizontal shift register. An example of this case is shown in FIG .

[0167] embodiment of FIG. 2, which has written the horizontal switching MOS transistor of the embodiment shown in FIG. 1, only the middle portion of the final stage amplifier, the other part, the implementation of FIG. 1 It is omitted because it is the same as the example.

In this embodiment, the output from one horizontal shift register 104 is output to the first column, (n + 1) th column, (2n
The gates of the switching MOS transistors in the (+1) th column are connected to read those lines at the same time. At the next time point, the second row, the (n + 2) th row, the (2n +
2) The column number is read.

According to this embodiment, each switching MO
Although the number of wirings to the gate of the S transistor is increased, only one horizontal shift register can operate.

In the examples of FIGS. 1 and 2 , three output amplifiers are provided, but it goes without saying that the number may be increased depending on the purpose.

In both the embodiments of FIGS. 1 and 2 , the start pulse and the clock pulse of the horizontal shift register and the vertical shift register are omitted, but these are provided in the same chip as other refresh pulses. Or a clock pulse generator provided on another chip.

In this divided reading method, when horizontal line batch or full screen batch refresh is performed, the nth column and (n
The accumulation time is slightly different between the photosensor cells in the (+1) th column, which may cause a slight discontinuity in the dark current component and the signal component, which may be noticeable on the image. Is small and practically no problem. Even if it exceeds the allowable limit, it is necessary to correct it using an external circuit to generate a poppy-like wave, and subtract it from the dark current component and multiply and divide it with the signal component. This is easily possible by using conventional correction techniques performed by.

When a color image is picked up by using such a photoelectric conversion device, a stripe filter, a mosaic filter, or the like is integrated on the photoelectric conversion device, or a separately prepared color filter is attached. A color signal can be obtained by combining them.

As an example, when the R, G, and B stripe filters are used, in the photoelectric conversion device using the photosensor cell according to the above configuration, the R signal, the G signal, and the B signal are respectively output from different final stage amplifiers. It is possible to obtain.
An example of this is shown in FIG. Similar to FIG. 2, this FIG. 17 also shows only around the horizontal shift register. Others are the same as in FIGS. 1 and 15, except that the first column is an R color filter, the second column is a G color filter, the third column is a B color filter, and the fourth column is an R color filter. The color filter is attached to. FIG. 17
, Each vertical line of the 1st, 4th, 7th, ... Is connected to the output line 110, which takes out the R signal. The vertical lines in the second, fifth, eighth, ... Columns are connected to the output line 111, which takes out the G signal.
Similarly, the vertical lines of the third column, the sixth column, the ninth column, ... Take out the B signal connected to the output line 112.
The output lines 110, 111 and 112 are respectively connected to on-chip refresh MOS transistors and final stage amplifiers, for example, emitter follower type bipolar transistors, and each color signal is output separately.

[0175] The diagram for explaining the basic structure and operation of another example of the photosensor cell of the photoelectric conversion device according to the present invention shown in FIG. 18. Further, FIG. 19 shows an equivalent circuit thereof and an overall circuit configuration diagram.

The photosensor cell shown in FIG. 18 is a photosensor cell capable of simultaneously performing a read operation and a line refresh by the same horizontal scan pulse. 18 is different from the configuration already shown in FIG. 4 in that in FIG. 4, M connected to the horizontal line wiring 10 is used.
The MOS capacitor electrode 1 having only one OS capacitor electrode 9 is also provided on the side of vertically adjacent photosensor cells.
20 is connected and is of a double capacitor type when viewed from one photosensor cell, and the emitters 7 and 7 ′ of the photosensor cells that are vertically adjacent to each other in the figure are the wiring 8 and the wiring 121 which are two-layer wiring. , (In FIG. 18, one vertical line is seen, but two lines are arranged through an insulating layer), that is, the emitter 7 is connected to the wiring 8 through the contact hole 19 and the emitter 7 ′. Are connected to the wiring 121 through the contact holes 19 ', respectively.

This becomes more apparent when the equivalent circuit of FIG. 19 is viewed. That is, the MOS capacitor 150 connected to the base of the photosensor cell 152 is connected to the horizontal line 31, and the MOS capacitor 151 is connected to the horizontal line 31 '. Further, the MOS capacitor 150 'of the photosensor cell 152' adjacent to the bottom of the photosensor cell 152 in the drawing is connected to the common horizontal line 31 '.

The emitter of the photosensor cell 152 is connected to the vertical line 38, the emitter of the photosensor cell 152 'is connected to the vertical line 138, the emitter of the photosensor cell 152 "is connected to the vertical line 38, and so on.

In the equivalent circuit of FIG. 19, except for the basic photosensor cell section described above, the difference from the image pickup device of FIG. 15 is that in addition to the switching MOS transistor 48 for refreshing the vertical line 38, the vertical line 138.
, And a switching MOS transistor 40 for selecting the vertical line 138 and a switching MOS transistor 140 for selecting the vertical line 138.
Has been added, and one output amplifier system has been added.
This output system has a switching MOS transistor 48 and 148 for refreshing each line.
It is also possible to adopt a configuration in which the output amplifiers are connected to each other, and use only a switching MOS transistor for horizontal scanning as shown in FIG. FIG. 20 shows only the vertical line selection and output amplifier system of FIG.

According to the photosensor cell of FIG. 18 and the embodiment shown in FIG. 19, the following operation is possible. That is, when the reading operation of each photosensor cell connected to the horizontal line 31 is completed and the horizontal blanking period in the television operation is completed, the output pulse from the vertical shift register 32 is output to the horizontal line 31 '. Through 151, the optical sensor cell 15 whose reading has been completed
Refresh 2. At this time, switching MOS
Transistor 48 is conductive and vertical line 38 is grounded.

Further, the MO connected to the horizontal line 31 '
The output of the photosensor cell 152 'is read out on the vertical line 138 through the S capacitor 150'. At this time, as a matter of course, the switching MOS transistor 148 is turned off and the vertical line 138 is in a floating state. In this way, with one vertical scan pulse, it is possible to simultaneously refresh the photosensor cells that have already been read and read the photosensor cells of the next line with the same pulse. At this time, as already described, the voltage for refreshing and the voltage for reading are different because a bias voltage is applied during reading because of the necessity of high-speed reading.
As shown in FIG. 5, it is achieved by changing the areas of the MOS capacitor electrode 9 and the MOS capacitor electrode 120 so that different voltages are applied to the bases of the respective photosensor cells even if the same voltage is applied to each electrode. ing.

That is, the area of the refresh MOS capacitor is smaller than that of the read MOS capacitor. As shown in FIG. 4B, when the sensor cells are not refreshed all at once but refreshed line by line as in this example, the collector is made of an n type or an n substrate. However, it may be desirable to have separate collectors for each horizontal line. When the collector is the substrate, the collectors of all the photosensor cells are in the common region, so that a constant bias voltage is applied to the collector in the accumulation and light reception read states. Of course, as described above, the floating base can be refreshed between the emitters even when the bias voltage is applied to the collector. However, in this case, at the same time as the refreshing of the base region is performed, a wasteful current flows between the emitter and collector of the cell to which the refresh pulse is applied, resulting in a large power consumption. In order to overcome these drawbacks, the collectors of all the sensor cells are not common to each other, and the collectors of the sensor cells arranged in each horizontal line are common, but the collectors of each horizontal line are separated from each other. That is, in connection with the structure of FIG. 4, the substrate is of p-type, and n ⁺ collectors separated from each other by horizontal lines in the p-type substrate.
The structure has an embedded region. N of adjacent horizontal lines
^{The +} buried region may be separated by a structure having a p region interposed therebetween. Insulator isolation is better for reducing the collector capacitor buried along the horizontal line.
In FIG. 4, since the collector is composed of the substrate, the isolation regions surrounding the sensor cell are all provided to almost the same depth. On the other hand, in order to separate the collectors for each horizontal line from each other, the separation region in the horizontal line direction is set to be deeper than the separation region in the vertical line direction by a necessary value.

If the collector is separated for each horizontal line, if the collector voltage of the horizontal line is grounded when the read operation is finished and the refresh operation is started, the above-described emitter-collector current does not flow. , Does not increase power consumption. When the refresh operation ends and the charge accumulation operation by the optical signal is started, a predetermined bias voltage is applied to the collector region again.

According to the equivalent circuit of FIG. 19, the output is alternately output to the output terminals 47 and 147 for each horizontal line. This is, as I already explained,
With the configuration shown in FIG. 20, it is possible to take out the output from one amplifier.

As described above, the photoelectric conversion device according to the present invention
According to location, a relatively simple configuration, the line refreshing is possible, can be applied to applications such as ordinary television camera.

As another configuration example of the present invention, a type in which a plurality of outputs are taken out from one photosensor cell by a configuration in which a plurality of emitters are provided in a photosensor cell or a configuration in which a plurality of contacts are provided in one emitter Conceivable.

Since each photosensor cell of the photoelectric conversion device according to the present invention has an amplification function, even if a plurality of wiring capacitors are connected to each photosensor cell in order to obtain a plurality of outputs from one photosensor cell, This is because the accumulated voltage Vp generated inside the photo sensor cell can be read out to each output without any attenuation.

As described above, with the configuration in which a plurality of outputs can be taken out from each optical sensor cell, many advantages are obtained for a signal processing or noise countermeasure for a photoelectric conversion device in which a large number of optical sensor cells are arranged. It is possible to add.

Next, an example of a method of manufacturing the photoelectric conversion device according to the present invention will be described. 21 and 22 show selective epitaxial growth (N. Endo et al, “New device isolation
technology with selected epitaxial growth "Tech.
Dig. Of 1982 IEDM, pp. 241-244), an example of the manufacturing method is shown.

An n ⁺ region 11 for contact is provided by diffusion of As or P on the back surface side of the n-type Si substrate 1 having an impurity concentration of about 1 to 10 × 10 ¹⁶ cm ^-3 . Although not shown, an oxide film and a nitride film are usually provided on the back surface in order to prevent autodoping from the n ⁺ region.

As the substrate 1, a substrate whose impurity concentration and oxygen concentration are uniformly controlled is used. That is, a crystal wafer having a carrier line time that is sufficiently long and uniform is used. As such a material, for example, a crystal by the MCZ method is suitable. An oxide film of about 1 μm is formed on the surface of the substrate 1 by wet oxidation. That is, it is oxidized in a H ₂ O atmosphere or a (H ₂ + O ₂ ) atmosphere. To obtain a good oxide film without causing stacking faults, 900 ° C
High pressure oxidation at moderate temperatures is suitable.

A SiO ₂ film having a thickness of, for example, about _{2 to 4} μm is deposited thereon by CVD. (N ₂ + SiH ₄ + O
₂ ) Deposit a SiO ₂ film of desired thickness at a temperature of about 300 to 500 ° C. in a gas system. The O ₂ / SiH ₄ molar ratio is set to about 4 to 40 depending on the temperature. By the photolithography process, the oxide film in the part which becomes the isolation region between the cells is left and the oxide films in the other regions are (CF ₄ + H ₂ ), C ₂
Removal by reactive ion etching using a gas such as F ₄ , CH ₂ F ₂ (step (a) in FIG. 21), for example,
10 μm when one pixel is provided for 10 × 10 μm ^2.
The SiO ₂ film is left in the form of pitch mesh. The width of the SiO ₂ film is selected to be, for example, about 2 μm. The damage layer and the contamination layer on the surface due to the reactive ion etching are
After removing by r / Cl ₂ gas-based plasma etching or wet etching, vapor deposition in ultra-high vacuum, or sputtering in which the atmosphere is sufficiently cleaned by a load lock method, or a CO ₂ laser beam is applied to SiH ₄ gas. Amorphous silicon 301 is deposited by irradiation with low pressure photo CVD (step (b) in FIG. 21), CBrF
_{3, CCl 2 F 2, Cl} SiO 2 by anisotropic etching using reactive ion etching using a ₂ or the like of the gas
Amorphous silicon other than those deposited on the side surface of the layer is removed (step (c) in FIG. 21). As before, the damage layer and the contaminated layer are sufficiently removed, and then the surface of the silicon substrate is sufficiently cleaned. Selective growth of a silicon layer is carried out by a (H ₂ + SiH ₂ , Cl ₂ + HCl) gas system. Number 10 Tor
The growth is performed under a reduced pressure of r, and the substrate temperature is 900 to 10
The molar ratio of 00 ° C. and HCl is set to a value higher than a certain level. If the amount of HCl is too small, selective growth does not occur.
Although a silicon crystal layer grows on the silicon substrate,
Since silicon on the O ₂ layer is etched by HCl, silicon is not deposited on the SiO ₂ layer ((d) of FIG. 21). The thickness of the n ⁻ layer 5 is, for example, 3 to 5 μm.
It is about m. The impurity concentration is preferably 10 ¹² to 10 ¹⁶
Set it to about cm ^-3 . Of course, this range may be deviated, but the impurity concentration and the impurity concentration such that at least the n ⁻ region is completely depleted in the state of being completely depleted at the diffusion potential of the pn ⁻ junction or when the operating voltage is applied to the collector. It is desirable to select the thickness.

Since HCl gas that can be usually obtained contains a large amount of water, an oxide film is always formed on the surface of a silicon substrate, and high-quality epitaxial growth cannot be expected. HCl containing a large amount of water reacts with the material of the cylinder in a state where it is contained in the cylinder, and contains a large amount of heavy metals centering on iron, which easily forms an epitaxial layer with a large amount of heavy metal contamination. Since it is more desirable for the epitaxial layer used for the optical sensor cell to have a smaller dark current component, it is necessary to suppress contamination by heavy metals to the utmost limit. It is needless to say that ultra-high-purity materials are used for SiH ₂ Cl ₂ , but HCl has particularly low water content, preferably at least 0.5 ppm water content.
Use the following: Of course, the lower the water content, the better. In order to further improve the quality of the epitaxial growth layer, the substrate is first subjected to a high temperature treatment of about 1150 to 1250 ° C. to remove oxygen from the vicinity of the surface, and then subjected to a long-term heat treatment of about 800 ° C. to generate many microdefects inside the substrate. It is also extremely effective to use a substrate having a denuded zone and capable of intrithic gettering. Since the epitaxial growth is performed in the state where the SiO ₂ layer 4 as the isolation region exists,
A lower growth temperature is desirable to reduce the uptake of oxygen from SiO ₂ . In the high-frequency heating method that is often used, it is difficult to further lower the temperature because there is much contamination from the carbon susceptor. The wafer direct heating method by lamp heating without bringing in a carbon susceptor into the reaction chamber can make the growth atmosphere the cleanest and can grow a high-quality epitaxial layer at a low temperature.

Ultrahigh-purity molten sapphire having a lower vapor pressure is suitable for the wafer support in the reaction chamber. The raw material gas can be preheated easily, and even if a large flow of gas is flowing, it is easy to make the wafer in-plane temperature uniform, that is, the wafer direct heating method by lamp heating that generates almost no thermal stress produces high-quality epitaxial layers. Suitable to get. UV irradiation on the wafer surface during growth
Further improve the quality of the epitaxial layer.

Amorphous silicon is deposited on the side wall of the SiO ₂ layer to be the isolation region 4 (step (c) in FIG. 21). Since amorphous silicon is likely to be single-crystallized by solid phase growth, the crystal near the interface with the SiO ₂ separation region 4 becomes very excellent. After forming the high resistance n ⁻ layer 5 by selective epitaxial growth (step (d) in FIG. 21), the P region 6 having a surface concentration of about 1 to 20 × 10 ¹⁶ cm ⁻³ is diffused from the doped oxide, or A low-dose ion implantation layer is used as a source to form a predetermined depth by diffusion. The depth of the p region 6 is, for example, 0.6 to
It is about 1 μm.

The thickness of the p region 6 and the impurity concentration are determined based on the following ideas. To increase the sensitivity, p region 6
It is desirable to reduce the impurity concentration of and reduce Cbe. Cbe is approximately given as follows.

[0197]

[Expression 33] However, Vbi is the diffusion potential between the emitter and the base,

[0198]

[Equation 34] Given in. Where ε is the dielectric constant of the silicon crystal, N
_D is the impurity concentration of the emitter, N _A is the impurity concentration of the portion adjacent to the emitter of the base, and n _i is the true carrier concentration. Cbe becomes smaller as N _A becomes smaller and the sensitivity increases, but if N _A is made too small, the base region will be completely depleted in the operating state and become a punching through state, so it cannot be made too low. Absent. It is set to such an extent that the base region is not completely depleted and a punching through state does not occur.

Then, (H ₂ + O
₂ ) From several 10Å to several 100Å due to gas-based steam oxidation
A thermal oxide film 3 having a thickness of about 800 is formed at a temperature of about 800 to 900.degree. Then, a nitride film (Si ₃ N ₄ ) 302 of 500 to 15 is formed by CVD of (SiH ₄ + NH ₃ ) based gas.
It is formed with a thickness of about 00Å. Formation temperature is 700-90
It is about 0 ° C. NH ₃ gas and the normally available products along with HCl gas also contain a large amount of water. If NH ₃ gas with a large amount of water is used as a raw material, a nitride film with a high oxygen concentration will be formed, resulting in poor reproducibility.
The selective etching with the O ₂ film causes a result that a selective ratio cannot be obtained. The NH ₃ gas also has a water content of at least 0.
It should be 5 ppm or less. It goes without saying that the smaller the water content, the more desirable. A PSG film 300 is further deposited on the nitride film 302 by CVD. The gas system is, for example, (N ₂ + SiH ₄ + O ₂ + PH ₃ ),
A PSG film having a thickness of about 2000 to 3000 Å is deposited by CVD at a temperature of about 300 to 450 ° C. (step (e) in FIG. 21). An As-doped polysilicon film 304 is deposited on the n ⁺ region 7 and the refresh and read pulse application electrodes by a photolithography process including two mask alignment processes. In this case, a p-doped polysilicon film may be used. For example, a PSG film and Si are formed on the emitter by two photolithography processes.
_The 3N ₄ film and the SiO ₂ film are all removed, and the underlying Si
Only the PSG film and the Si ₃ N ₄ film are etched, leaving the O ₂ film. Then, the As-doped polysilicon is replaced with (N ₂
+ SiH ₄ + AsH ₃ ) or (H ₂ + SiH ₄ + A
sH ₃ ) gas is deposited by the CVD method. Deposition temperature is 5
The film thickness is about 50 ° C to 700 ° C and the film thickness is 1000 to 2000Å. Of course, non-doped polysilicon may be deposited by the CVD method and then As or P may be diffused.
The polysilicon film except for the emitter and the refresh and read pulse application electrodes is masked, and is removed by etching after the photolithography process. Further, when the PSG film is etched, P is caused by lift-off.
The polysilicon deposited on the SG film is removed in a self-aligned manner (step (f) in FIG. 21). The etching of the polysilicon film is performed using C ₂ Cl ₂ F ₄ , (CBrF ₃ +
Cl ₂ ), etc. is used for etching, and the Si ₃ N ₄ film is C
Etching is performed with a gas such as H ₂ F ₂ .

Next, after depositing the PSG film 305 by the gas-based CVD method as described above, contact holes are formed on the polysilicon film for the refresh pulse and read pulse electrodes by a mask aligning process and an etching process. Open. In such a state, Al, Al-Si, Al-
Metals such as Cu-Si or deposited by vacuum deposition or sputtering, or (CH _{3) 3} Al or AlCl ₃
Al is deposited by a plasma CVD method using as a raw material gas or a light irradiation CVD method of cutting the Al—C bond or Al—Cl bond of the above raw material gas by direct light irradiation. When performing the above-described CVD method using (CH ₃ ) ₃ Al or AlCl ₃ as a raw material gas, hydrogen is allowed to flow in a large excess. For depositing Al in a thin and steep contact hole, the CVD method in which the substrate temperature is raised to 300 to 400 ° C. in a clean atmosphere containing no moisture or oxygen is excellent. After the patterning of the metal wiring 10 shown in FIG. 4 is completed, the interlayer insulating film 306 is deposited by the CVD method. 306 is the above-mentioned PSG film, the CVD method SiO ₂ film, or the Si ₃ N ₄ film formed by the (SiH ₄ + NH ₃ ) gas-based plasma CVD method when it is necessary to consider the water resistance. Is. In order to keep the hydrogen content in the Si ₃ N ₄ film low, a plasma CVD method using a (SiH ₄ + N ₂ ) gas system is used.

In order to increase the electrical breakdown voltage of the Si ₃ N ₄ film formed by causing the phenomenon of damage by the plasma CVD method and reduce the leak current, Si ₃ by the photo CVD method is used.
N ₄ film is excellent. There are two types of photo CVD methods. A method of irradiating 2537Å ultraviolet rays of a mercury lamp from the outside with a (SiH ₄ + NH ₃ + Hg) gas system, and (S
This is a method of irradiating the iH ₄ + NH) ₃ gas system with 1849 Å ultraviolet rays from a mercury lamp. In both cases, the substrate temperature is 150-
It is about 350 ° C.

Insulating films 305 and 3 are formed on the polysilicon on the emitter 7 by a mask aligning process and an etching process.
After the contact hole penetrating 06 is opened by reactive ion etching, Al, Al-Si,
A metal such as Al-Cu-Si is deposited. In this case,
Since the aspect ratio of the contact hole is large, CVD
The deposition by the method is superior. After patterning the metal wiring 8 in FIG. 15 , a Si ₃ N ₄ film or a PSG film 2 as a final passivation film is formed by CVD.
It is deposited by the method (FIG. 22).

Also in this case, the film formed by the photo CVD method is excellent. Reference numeral 12 is a metal electrode on the back surface made of Al, Al-Si, or the like.

The method for manufacturing the photoelectric conversion device of the present invention has various steps, and FIGS. 21 and 22 are merely examples.

An important point of the photoelectric conversion device of the present invention is how to reduce the leak current between the p region 6 and the n ⁻ region 5 and between the p region 6 and the n ⁺ region 7. n ^- region 5
Of course, to reduce the dark current by improving the quality of the isolation region 4 and the n ⁻ region 5 made of an oxide film or the like.
The interface is the problem. 21 and 22, for this purpose, amorphous Si is previously formed on the side wall of the isolation region 4.
A method of depositing and performing epitaxial growth has been described. In this case, the substrate S during epitaxial growth
Amorphous Si is single-crystallized by solid phase growth from i. Epitaxial growth is 850 ° C to 100
It is carried out at a relatively high temperature of about 0 ° C. Therefore, fine crystals often start to grow in the amorphous Si before the amorphous Si is single-crystallized by solid phase growth from the substrate Si, which causes deterioration of crystallinity.
The lower the temperature, the faster the solid-phase growth rate is in amorphous Si.
Before the selective epitaxial growth, 5
Amorphous Si is obtained by low-temperature treatment of about 50 ° C to 700 ° C.
If a single crystal is used, the interface characteristics are improved. At this time, if there is a layer such as an oxide film between the substrate Si and the amorphous Si, the start of solid phase growth is delayed, and therefore an ultra-high cleaning process that does not include such a layer at the boundary between the two is required.

For solid phase growth of amorphous Si, in addition to the above-described furnace growth, a rapid annealing technique of heating the substrate at a certain temperature and heating it with a fish lamp or an infrared lamp for, for example, several seconds to several tens seconds is also available. It is valid. When using these technologies, Si
The Si deposited on the side wall of the O ₂ layer may be polycrystalline. However, it is necessary to deposit it by a very clean process to make polycrystalline Si that does not contain oxygen, carbon, etc. at the crystal grain boundaries of the polycrystalline body.

After the Si on the side surface of SiO ₂ is monocrystallized, the Si is selectively grown.

When the leak current at the interface between the SiO ₂ isolation region 4 and the high resistance n ⁻ region 5 is inevitable, the high resistance n −
^- only the portion adjacent to the SiO ₂ isolation region 4 in the region 5, n
If the impurity concentration of the shape is increased, the problem of the leak current can be avoided. For example, only the n ⁻ region 5 in contact with the isolation SiO ₂ region 4 and having a thickness of about 0.3 to 1 μm,
For example, the n-type impurity concentration is increased to about 1 to 10 × 10 ¹⁶ cm ⁻³ . This structure can be formed relatively easily. After forming a thermal oxide film of about 1 μm on the substrate 1, it is deposited by the CVD method. Only first required thickness of the SiO ₂ film, keep the SiO ₂ film containing P of a predetermined amount. Further, SiO ₂ is deposited thereon by the CVD method to form the isolation region 4. In the subsequent high-temperature process, phosphorus is diffused from the SiO ₂ film containing phosphorus existing in the isolation region 4 in a sandwich shape into the high resistance n ⁻ region 5, and the interface has the highest impurity concentration. make.

That is, the structure as shown in FIG. 23 is formed. The isolation region 4 has a three-layer structure, 308 is a thermal oxide film SiO ₂ , and 309 is C containing phosphorus.
The VD method SiO ₂ film and 301 are CVD method SiO ₂ films. N adjacent to the isolation region 4 and between the n ⁻ region 5 and n
The region 307 is formed by diffusion from the SiO ₂ film 309 containing phosphorus. 307 is formed all around the cell. With this structure, the base-collector capacitance Cbc
Is large, but the base-collector leakage current is drastically reduced.

In FIG. 21 and FIG. 22, an example in which the isolation insulating region 4 is formed in advance and selective epitaxial growth is performed has been described, but a high resistance n ⁻ required on the substrate is described.
U-group isolation technology (A.Hayasaka et al, “U-groove isolation, in which a layer to be an isolation region is cut in a mesh shape by reactive ion etching after the layer is epitaxially grown to form the isolation region.
technique for highspeed bipolar VLSI'S ″, Tech.
Dig. Of IEDM. P.62, 1982, see also).

The photoelectric conversion device according to the present invention is a bipolar transistor in which a base region, most of which is adjacent to the surface of a semiconductor wafer, is in a floating state in a region surrounded by an isolation region made of an insulator. This is a device for photoelectrically converting optical information by controlling the potential of a base region which has been formed and brought into a floating state by an electrode provided in a part of the base region through a thin insulating layer. An emitter region composed of a high impurity concentration region is provided in a part of the base region, and this emitter is connected to a MOS transistor operated by a horizontal scan pulse. The above-mentioned electrodes provided on a part of the floating base region via a thin insulating layer are connected to the horizontal line. The collector provided inside the wafer may be composed of a substrate, or may be composed of a high-concentration impurity-embedded region separated for each horizontal line on a high resistance substrate of opposite conductivity type depending on the purpose. . The applied pulse voltage at the time of reading a signal is substantially higher than the pulse voltage at the time of refreshing the floating base region in the electrode provided via the insulating layer. In practice, a pulse train that waits for two kinds of voltage may be used, or, as described in the double capacitor structure, the capacitance C _ox of the refresh MOS capacitor electrode.
The capacitance C _ox of the read MOS capacitor electrode may be made larger than that. By applying a refresh pulse, the photo-excited carriers are accumulated in the floating base region in the reverse bias state to store a signal based on the optical signal, and at the time of reading the signal, the base and emitter are deeply biased in the forward direction. As described above, the read pulse voltage is applied so that the signal can be read at a high speed. It is needless to say that the photoelectric conversion device of the present invention may be realized by any structure as long as it has such characteristics, and is not limited to the structure described in the above configuration example. For example, the same applies to the structure described in the above configuration example and the structure in which the conductivity type is completely inverted. However, at this time, it is necessary to completely reverse the polarity of the applied voltage. In a structure in which the conductivity type is completely inverted, the region becomes n-type. That is, the impurities constituting the base are As and P.
become. When the surface of the area containing As and P is oxidized, As
And P pile up on the Si side of the Si / SiO ₂ interface. That is, a strong drift electric field from the surface to the inside is generated inside the base, the photoexcited holes immediately escape from the base to the collector side, and electrons are efficiently accumulated in the base.

When the base is p-type, boron is a commonly used impurity. When the surface of the p region containing boron is thermally oxidized, boron is incorporated into the oxide film, so that Si /
The boron concentration in Si near the SiO ₂ interface is slightly lower than the boron concentration inside. This depth is usually several 100 Å, although it depends on the oxide film thickness. Near this interface,
An anti-drift field for the electrons occurs, and the electrons photoexcited in this region tend to collect at the surface. Under this condition, the region in which the reverse drift electric field is generated becomes a dead region, but since the n ⁺ region exists in a part along the surface in the photoelectric conversion device of the present invention, p
The electrons collected at the Si / SiO ₂ interface of the region are
It flows into this n ⁺ region before it is recombined. Therefore, even if there is a region where, for example, boron is reduced in the vicinity of the Si / SiO ₂ interface and an inverse drift electric field is generated, it hardly becomes a dead region. Rather, When such regions are present at the Si / SiO ₂ interface, in order to be present within the accumulated holes pulled away from the Si / SiO ₂ interface, there is no effect of hole disappears at the interface of the p-layer The hole accumulation effect in the base is good, which is extremely desirable.

In addition to the solid-state image pickup device described above, the photoelectric conversion device according to the present invention includes, for example, an image input device, a facsimile, a workstation, a digital copying machine, an image input device such as a word processor, an OCR, a bar code reader. The present invention can also be applied to a photoelectric conversion subject detection device for autofocus such as a device, a camera, a video camera, and an 8 mm camera.

[0214] The photoelectric conversion device according to the present invention as has been described above is intended for accumulating carriers excited by light in the base region which is a control electrode region was made into a floating state. That is, the Base Store Image
It is a device that should be called a Sensor, and BASIS
Is abbreviated.

Since the photoelectric conversion device according to the present invention can form one pixel with one transistor, it is very easy to increase the density, and at the same time, its structure has less blooming and smear and high sensitivity. It has a wide range, and since it has an internal amplifying function, it generates a large signal voltage regardless of the wiring capacitance, so that it has a feature of low recording and easy peripheral circuits. For example, as a high-quality solid-state imaging device of the future, its industrial value is extremely high.

[0216]

According to the present invention, even at low frequencies, the
Qualitatively perform signal processing at the same speed as high-frequency processing
You can

[Brief description of drawings]

FIG. 1 is a light showing an embodiment of a signal processing device of the present invention .
It is a circuit block diagram of a power converter.

FIG. 2 shows another embodiment of the signal processing device of the present invention .
It is a circuit block diagram of a photoelectric conversion apparatus.

FIG. 3 is an equivalent circuit diagram of a photosensor cell according to an embodiment of the present invention during a refresh operation.

4A is a plan view of an optical sensor cell according to an embodiment of the present invention, FIG. 4B is a sectional view, and FIG. 4C is an equivalent circuit diagram.

FIG. 5 is a graph showing the relationship between the read time and the read voltage of the photosensor cell according to the embodiment of the present invention.

FIG. 6 is a graph showing the relationship between the accumulated voltage and the read time of the photo sensor cell according to the embodiment of the present invention.

FIG. 7 is a graph showing the relationship between the bias voltage and the read time of the photo sensor cell according to the embodiment of the present invention.

FIG. 8 is a graph showing a relationship between a refresh time and a base potential of an optical sensor cell according to an example of the present invention.

FIG. 9 is a graph showing the relationship between the refresh time and the base potential of the photo sensor cell according to the embodiment of the present invention.

FIG. 10 is a graph showing the relationship between the refresh time and the base potential of the photo sensor cell according to the embodiment of the present invention.

11 is a pulse timing chart of the photoelectric conversion device of FIG.

12 is a graph showing a potential distribution during each operation of the photoelectric conversion device of FIG.

13 is an equivalent circuit diagram related to output signals of the photoelectric conversion device of FIG.

14 is a graph showing the output voltage from the moment when the photoelectric conversion device of FIG. 15 becomes conductive, with respect to time.

FIG. 15 shows a photoelectric conversion device having one signal processing unit .
It is a circuit diagram.

FIG. 16 shows a read operation of the optical sensor cell according to the present invention .
It is an equivalent circuit diagram.

FIG. 17 is a circuit diagram showing another photoelectric conversion device.

FIG. 18 is a plan view for explaining a main structure of a modified example of the present invention.

19 is a circuit configuration diagram of a photoelectric conversion device configured by the optical sensor cell shown in FIG.

20 is a circuit configuration diagram of a photoelectric conversion device configured by the optical sensor cell shown in FIG.

FIG. 21 is a cross-sectional view showing an example of a method for manufacturing the photoelectric conversion device of the present invention.

FIG. 22 is a cross-sectional view showing an example of a method for manufacturing the photoelectric conversion device of the present invention.

FIG. 23 is a cross-sectional view showing an example of a method for manufacturing the photoelectric conversion device of the present invention.

FIG. 24 shows an optical sensor cell according to an embodiment of the present invention,
(A) is a sectional view, (b) is an equivalent circuit diagram thereof, and (c) is a potential distribution diagram.

FIG. 25 is a sectional view showing the main structure of another modification of the optical sensor cell.

[Explanation of symbols] 1 silicon substrate 2 PSG film 3 insulating oxide film 4 element isolation region 5 n ^- region (collector region) 6 p region (base region) 7, 7'n ⁺ region (emitter region) 8 wiring 9 electrode 10 Wiring 11 n ⁺ region 12 Electrode 13 Capacitor 14 Bipolar transistor 15,17 Junction capacitance 16,18 Diode 19,19 'Contact part 20 Light 28 Vertical line 30 Photosensor cell 31 Horizontal line 32 Vertical shift register 33,35 MOS transistor 36,37 Terminal 38 Vertical Line 39 Horizontal Shift Register 40 MOS Transistor 41 Output Line 42 MOS Transistor 43 Terminal 44 Transistor 45 Load Resistor 46 Terminal 47 Terminal 48 MOS Transistor 49 Terminal 61, 62, 63 Section 64 Collector Potential 67 Type 80,81 Capacity 82,83 Resistance 84 Current source 100,101,102 Horizontal shift register 111,112 Output line 138 Vertical line 140 MOS transistor 148 MOS transistor 150,150 'MOS capacitor 152,152' Photosensor cell 202,203, 205 Base potential 220 Buried p ⁺ region 222,225 Wiring 251 p ⁺ region 252 n ⁺ region 253 Wiring 300 Amorphous silicon 302 Nitride film 303 PSG film 304 Polysilicon 305 PSG film 306 Interlayer insulation film

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FIG. 16

Claims (8)

[Claims] 1. A control electrode region made of a semiconductor of a first conductivity type and a first electrode electrically made of a semiconductor of a second conductivity type different from the first conductivity type and electrically connected to an output circuit including a capacitive load. A transistor having a main electrode region and a second main electrode region made of a semiconductor of a second conductivity type, capable of storing carriers generated by receiving light energy in the control electrode region; A refresh operation for holding the first main electrode region at a reference potential and removing the carriers accumulated in the control electrode region in a refresh operation after reading a signal based on the carriers; In a photoelectric conversion device that performs an operation, a read operation, and a refresh operation, the refresh means includes a reference voltage source in the control electrode region with respect to the first and second main electrode regions. A photoelectric conversion device, which is means for independently applying a potential and biasing a junction between the first main electrode region and the control electrode region in a state of being held at the reference potential in a forward direction. 2. A semiconductor layer region of the second conductivity type is interposed in a part along an interface between the insulating layer provided on the control electrode region and the control electrode region. 1. The photoelectric conversion device described in 1. 3. The photoelectric conversion device according to claim 1, wherein the transistor is integrally formed with a semiconductor substrate made of a second conductivity type semiconductor. 4. The photoelectric conversion device according to claim 1, wherein the transistor is formed on a semiconductor substrate made of a first conductivity type semiconductor. 5. The refresh means includes a MOS transistor electrically connected to the first main electrode region, and the first main electrode region is connected to the reference potential via the MOS transistor during the refresh operation. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device is stored in the photoelectric conversion device. 6. The output circuit includes a shift register that transfers the signal to an output amplifier, and transfers the signal read to the capacitive load to the output amplifier. Photoelectric conversion device. 7. The photoelectric conversion device according to claim 1, wherein the transistor is a bipolar transistor, the first main electrode region is an emitter, and the second main electrode region is a collector. 8. A control electrode region made of a semiconductor of a first conductivity type and a first electrode electrically made of a semiconductor of a second conductivity type different from the first conductivity type and electrically connected to an output circuit including a capacitive load. A transistor having a main electrode region and a second main electrode region made of a second conductivity type semiconductor, capable of storing carriers generated by receiving light energy in the control electrode region; In the photoelectric conversion method using a photoelectric conversion device, which holds a main electrode region of the device at a reference potential and removes carriers accumulated in the control electrode region, a carrier is accumulated in the control electrode region. To irradiate the transistor with light for reading, a reading process for reading a signal based on the carriers stored in the control electrode region, and the refreshing means for controlling the signal. A potential is independently applied to the electrode region from a reference voltage source to the first and second main electrode regions, and the first main electrode region and the control electrode region are held at the reference potential. And a refreshing step of removing a carrier accumulated in the control electrode region by biasing a junction portion thereof with a forward direction, and a photoelectric conversion method.