JPH0817462B2 - Signal processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device,
In particular, the present invention relates to a signal processing device that processes output signals from a plurality of photosensor arrays provided on the same substrate.

[0002]

2. Description of the Related Art In recent years, research on photoelectric conversion devices, particularly solid-state image pickup devices, has been actively conducted with the progress of semiconductor technology, and some have begun to be put to practical use. These solid-state imaging devices can be broadly classified into two types: CCD type and MOS type. The CCD type imaging device forms a potential well under the MOS capacitor electrode, accumulates the charge generated by the incidence of light in this well, and sequentially moves these potential wells by a pulse applied to the electrode during reading. The principle is that the accumulated electric charges are transferred to the output amplifier and read. Some CCD type image pickup devices use a pn junction diode structure for the light receiving part and a CCD structure for the transfer part. On the other hand, the MOS-type image pickup device accumulates charges generated by the incidence of light in each of the photodiodes having a pn junction that constitutes a light receiving portion, and sequentially reads out the MOS switching transistors connected to the photodiodes at the time of reading. It is based on the principle that the charges accumulated by turning on are read out to the output amplifier section.

The CCD type image pickup device has a relatively simple structure, and in view of the noise that can be generated, only the capacitance value of the charge detector consisting of the floating diffusion in the final stage contributes to random noise. It is an imaging device with relatively low noise and is capable of low-illumination imaging. However, due to the process limitation of making a CCD type image pickup device, a MOS type amplifier is on-chip as an output amplifier, so 1 / f noise, which is easily noticeable on the image, is generated from the interface between silicon and the SiO ₂ film. To do. Therefore, although the noise is low, there is a limit in its performance. Also,
If the density is increased by increasing the number of cells to achieve higher resolution, the maximum amount of charge that can be stored in one potential well decreases, and the dynamic range cannot be obtained.
In the future, it will be a big problem in increasing the resolution of the solid-state imaging device. In addition, since the CCD type image pickup device transfers the accumulated charge while sequentially moving the potential well, even if one of the cells has a defect, the charge transfer is stopped there, or an extreme In addition, there is a disadvantage that the production yield is not improved.

On the other hand, the MOS type imaging device is slightly more complicated in structure than a CCD type imaging device, especially a frame transfer type device, but can be configured to have a large storage capacity, It has the advantage of having a wide range. Further, even if one of the cells has a defect, the defect does not affect other cells due to the XY address system, which is advantageous in terms of manufacturing yield. However, in this MOS type imaging device, since a wiring capacitance is connected to each photodiode at the time of signal reading, an extremely large signal voltage drop occurs, the output voltage is reduced, and the wiring capacitance is large, resulting in random noise. Drawbacks, and fixed pattern noise due to variations in the parasitic capacitance of each photodiode and MOS switching transistor for horizontal scanning, etc., making low-illuminance imaging difficult compared to CCD-type imaging devices. have.

Further, in the future high resolution of the image pickup apparatus, the size of each cell is reduced and the accumulated charge is reduced. On the other hand, the wiring capacity determined by the chip size does not decrease much even if the line width is reduced. Therefore, the MOS type image pickup device becomes more and more disadvantageous in terms of S / N.

[0006] The CCD type and MOS type imaging devices have the advantages and disadvantages described above, but are gradually approaching the level of practical use. However, it can be said that there is an essentially large problem in further increasing the resolution required in the future. On the other hand, regarding the solid-state imaging device,
Japanese Patent Application Laid-Open No. 56-150878, “Semiconductor imaging device”,
JP-A-56-157073, "Semiconductor image pickup device",
A new system has been proposed in Japanese Patent Application Laid-Open No. Sho 56-165473, entitled "Semiconductor Imaging Device". CCD-type and MOS-type imaging devices accumulate charges generated by light incidence on a main electrode (for example, the source of a MOS transistor).
In the method proposed here, a charge generated by light incidence is transferred to a control electrode (for example, a base of a bipolar transistor, a SIT (static induction transistor) or a MOS transistor).
It is based on a new idea of controlling the flowing current by the charge generated by light accumulated in the gate of a transistor). That is, CCD type, M
The OS type reads out the stored charge itself to the outside, whereas the method proposed here reads out the stored charge after amplifying the charge by the amplification function of each cell. From another point of view, a low impedance output is read out by impedance conversion.
Therefore, the method proposed here has high output, wide dynamic range, low noise, and since carriers (charges) excited by an optical signal are accumulated in the control electrode, nondestructive readout is possible. Has some benefits. Furthermore, it can be said that this method has a possibility for a higher resolution in the future.

However, this method is basically X-
The Y-address method is the Y-address method, and the element structure described in the above publication has a basic configuration in which each cell of a conventional MOS type image pickup device is combined with an amplification element such as a bipolar transistor or an SIT transistor. Therefore, it has a relatively complicated structure and has a possibility of high resolution, but there is a limit to high resolution as it is.

There are also limits in the points described below. JP-A-56-150878, JP-A-56-15
7073, JP-A-56-165473 and SIT (Stat
ic Injection Transistor) Application to image sensor, Technical Report of Television Society (hereinafter referred to as TV Society journal) "
FIG. 1 shows a representative example of a conventional technique involving one of the inventors of the present invention.

JP-A-56-150878, JP-A-56-15707
The 3 ^{JP, N +, P +, I} ( or ^P -, ^N -), ^N
The charge is accumulated in the P ⁺ region of the hook structure composed of the ⁺ region,
There is described a configuration of a system in which the potential of an N ⁺ region forming a capacitor with the ground potential is read by a switching transistor.

However, with this configuration, the output signal cannot be read out at high speed and with sufficient linearity. Also in the reset operation after reading, only the P ⁺ region is grounded, the output side is not reset, and a noticeable afterimage is often generated. Also, fixed pattern noise is large.

On the other hand, Japanese Unexamined Patent Publication No. 56-165473 discloses N ⁺
Region, a floating P ⁺ region, a high resistance region, and an N ⁺ region connected to a transparent electrode to which a pulse voltage is applied, N ⁺ , P ⁺ , I (or P ⁻ , N ⁻ ), The hook structure of the N ⁺ region is shown. The floating N ⁺ region is also one of the main electrode regions of the read transistor at the same time. During the read operation, the transistor is turned on and electrons flow into the positively charged N ⁺ region, and the voltage change is used as a signal. Read out. However, this also cannot read the output signal at high speed and with sufficient linearity. Also, in the reset operation after reading, the N ⁺ region on the transparent electrode side opposite to the output circuit is set to 0 or slightly negative potential, and there is no reset on the output side. Many occur. Furthermore, high speed refresh is not possible.

[0012] And, the TV conference journal shows a gate storage type photocell and a base storage type photocell. Among them, the gate storage type photocell has a configuration in which the gate region is set in a floating state and the gate region is reverse-biased in advance to a predetermined voltage via a refresh line via an insulating film and read to an output circuit of a source ground resistance load. However, with this configuration, sufficient linearity cannot be obtained when the output signal is read at high speed. This is because the output voltage does not reach the required value in a short time because a sufficient forward bias is not applied during reading. Further, since resetting is not performed on the output side, the resetting operation is insufficient and many afterimages occur.

On the other hand, the base storage type photocell has N ⁺ , P
^+, N ^-, N ⁺ has a phototransistor structure, a base in a floating state (P ^+), a collector (N ⁺⁾ of pulses to a voltage is applied, the capacitance and the switching MOS
An emitter follower output circuit including an FET and an emitter (N ⁺ ) to which the output circuit is connected. However, in this configuration, since reading is performed by applying a voltage to the collector, it is difficult to ensure linearity at high speed operation, as will be described later with reference to FIGS. 5, 6, and 7. Also, in refreshing, since the emitter and collector are simply grounded, fixed pattern noise is large and high-speed refreshing cannot be performed.

In addition to the above-mentioned prior art, US Pat. No. 3,624,428 and Japanese Patent Publication No. 50-38531 disclose an output circuit of a grounded-emitter resistance load for a transistor in which an electrode is provided on the base through an insulating layer. Is connected, the base is reversely biased to perform the accumulation operation, and the output circuit of the grounded-emitter resistor load reads the current. After all, however, the linearity and the afterimage characteristic are poor because of the destructive type current reading.

[0015]

The configuration of the conventional solid-state image pickup device and its problems have been described above. However, a signal read for reading a signal from each sensor pixel to an amplifier via a transistor sequentially turned on by a shift register. In a solid-state imaging device having a circuit, when the time for reading out a signal for one horizontal line is fixed, the higher the number of pixels, the faster the need for reading becomes. There is a problem that a high-speed analog-to-digital converter is required for applications such as analog-to-digital conversion and signal processing. [Object of the Invention] An object of the present invention is to provide a signal processing device capable of performing high-speed signal processing with a simple circuit configuration.

[0016]

The object of the present invention is to provide a plurality of optical sensor arrays each comprising a plurality of optical sensors provided on the same substrate, a reading means for reading an output signal from the optical sensor array, and a reading means. And a plurality of signal processing means provided corresponding to the shift register, and a plurality of signal processing means provided for the shift register. In the signal processing device in which means are respectively provided corresponding to the plurality of photosensor arrays and the signals transferred from the respective photosensor arrays are processed in parallel by the signal processing means, the photosensor outputs an emitter. A bipolar transistor connected to the transfer means via a line and having a base connected to the drive line of the read means, and the read means is connected to the base by Signal processing characterized in that it is means for applying a voltage from a flow line to forward bias a junction between a floating emitter and a base and reading the output signal as a voltage at a capacitive load of the output line. Achieved by the device.

[0017]

According to the present invention, when the output signals from the plurality of photosensor arrays are processed, the signals transferred from the respective photosensor arrays are processed in parallel by the plurality of signal processing means. Thus, compared to the case of performing signal processing, it is possible to perform signal processing at a low frequency at substantially the same speed as processing at a high frequency. Further, the present invention uses a bipolar transistor having a capacity as a load as an optical sensor, and is a nondestructive and amplified SN.
A high ratio output signal is obtained. Further, according to the present invention, a voltage is applied to the base from a drive line to read a signal as a base-emitter forward bias, the time required to charge up a capacitive load is shortened, high-speed reading can be performed, and linearity under low illuminance can be achieved. Is maintained. As described above, the high speed signal processing and the high speed reading from the optical sensor are combined to enable the high speed operation of the entire apparatus.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below in comparison with the case where there is one signal processing means. FIG. 1 is a circuit configuration diagram of a photoelectric conversion device using a signal processing device showing a preferred embodiment of the present invention. The signal processing means includes an amplifier including an output transistor 44 and a load resistor 45, and three amplifiers are provided here. In FIG. 1, each horizontal shift register 100, 1
The photosensor of each row connected to the MOS transistor controlled by 01 and 102 is a photosensor array. FIG. 15 is a circuit configuration diagram of a photoelectric conversion device showing a case where there is one signal processing unit.

In the embodiment shown in FIG. 1, three equivalent horizontal shift registers 100, 101 and 102 are provided, and when a start pulse is applied to a terminal 103 for applying these start pulses, the first column, (n + 1). ) Column, (2n + 1) column (n is an integer, and in this embodiment, the number of horizontal picture elements is 3
It is n. ) Will be read simultaneously. At the next time, the second column, (n
The +2) th column and the (2n + 2) th column are read. According to the present invention, when the time for reading out one horizontal line is fixed, the scanning frequency in the horizontal direction is 1/100 as compared with the system of FIG. 15 with one final stage amplifier. The frequency of 3 is sufficient, the horizontal shift ranger becomes simple, and when the signal processing means performs analog-digital conversion of the output signal from the photoelectric conversion device for signal processing, a high-speed analog-digital converter is not necessary. It is necessary and is a great advantage of the division read method by the signal processing device of the present invention.

In the embodiment shown in FIG. 1, three equivalent horizontal shift registers are provided, but the same function can be provided by only one horizontal shift register. An example of an embodiment in this case is shown in FIG. Figure 2
Of the embodiment shown in FIG. 1, only the horizontal switching MOS transistor and the intermediate part of the final stage amplifier are written, and the other parts are the same as those of the embodiment of FIG. It is omitted because it is the same.

In this embodiment, the output from one horizontal shift register 104 is the first column, the (n + 1) th column,
The gates of the switching MOS transistors in the (2n + 1) th column are connected to read those lines simultaneously. At the next time, the second row, the (n + 2) th row,
That is, the (2n + 2) th column is read.

Next, the operation of the photoelectric conversion device shown in FIG. 1 will be briefly described. The photoelectric conversion operation of the photoelectric conversion device shown in FIG. 1 includes a storage operation, a read operation, and a refresh operation. In the following description, for simplification of description, FIG.
Will be explained. First, referring to FIGS. 15 and 16, an output circuit is connected to a first main electrode region (emitter) of a photoelectric conversion cell including a transistor as shown by reference numeral 30 in FIG. This output circuit includes vertical lines 38, 38 ', 38 ", horizontal shift register 39, MO
S transistors 40, 40 ', 40 ", output line 4
1, a MOS transistor 42, an output transistor 44,
It is composed of load resistance 45, etc.
Each 38 ″ has a wiring capacitance as Cs as a capacitive load, as indicated by reference numeral 21 in FIG.

A vertical shift register 32 and buffer MOS transistors 33, 3 serve as reading means for reading a signal photoelectrically converted based on the accumulated charges.
3 ', 33 ", terminals 34, horizontal lines 31, 31', 3
1 "is provided in the circuit configuration.

During the storage operation, the emitter is floating or grounded, and the second main electrode region (collector) is biased to a positive potential. The control electrode region (base) is reverse biased with respect to the emitter, and the saturation voltage can be determined by controlling the base potential at this time. Thus, by appropriately setting the bias voltage, the cell itself can have a switching action.

During a read operation, the emitter is floated and the collector is biased to a positive potential . The potential of the control electrode region (base) is controlled by the reading means independently of the main electrode region (emitter / collector) . When the base is biased in the forward direction with respect to the emitter, high-speed reading can be performed while ensuring good linearity. The operation at this time will be described with reference to FIG. At the time of reading, a positive voltage V _R is independently applied from the wiring 10 to the floating emitter and the collector held at a positive potential, whereby the base potential is forward biased with respect to the emitter potential. This deeply biases the emitter-base junction forward. In this way, the current flows until the emitter potential becomes equal to the base potential, that is, the storage voltage generated by light irradiation. The time required at this time is further shortened by the action of the voltage V _R , and even in high-speed reading. Therefore, excellent linearity can be secured.

The refresh operation is as follows.
The emitter is a MOS transistor 4 as switching means.
8, 48 ', 48 "is connected to a first reference voltage source, which is indicated by a ground symbol, and is grounded, the collector being connected to the second reference voltage source, that is, at a positive or ground potential. , Vertical line 3 including capacitive load
3, 8, 38 ', 38 "are reset. Here, the case where the collector is grounded is shown in FIG. 3. In such a state, a voltage of positive potential V _RH is applied and the base of the control electrode region is controlled. By controlling the potential, at least the base-emitter is forward-biased so that holes accumulated in the base region flow out or electrons flow into the base region to eliminate accumulated charges. MOS is used as a refreshing means for applying a forward bias.
The transistors 48, 48 ', 48 ", the buffer MOS transistors 35, 35', 35", the terminal 36, and the terminal 3 serving as a reference voltage source for independently applying the potential _VRH to the base.
It is configured by providing 7 and the like.

Embodiments of the present invention will be described in detail below with reference to the drawings. Prior to the description of the embodiments of the present invention,
An optical sensor array whose output signal is processed by a signal processing device.
An example of B will be described. FIG. 4 is a diagram for explaining the basic structure and operation of the optical sensor cell of the optical sensor array . FIG. 4A is a plan view of the optical sensor cell.
4B is a sectional view of the AA ′ portion of the plan view of FIG.
FIG. 4C shows an equivalent circuit thereof. In addition,
4A, 4B, and 4C have the same reference numerals.

In FIG. 4, a plan view of the alignment arrangement method is shown, but it goes without saying that the arrangement can also be performed in the pixel shift method (interpolation arrangement method) in order to increase the horizontal resolution. This optical sensor cell has phosphorus (P), antimony (Sb), arsenic (A) as shown in FIGS.
s) is doped with an impurity such as n-type or n ⁺ -type silicon substrate 1, and a passivation film 2 usually made of a PSG film or the like, and an insulating oxide film 3 made of a silicon oxide film (SiO ₂ ). , An element isolation region 4 formed of an insulating film made of SiO ₂ or Si ₃ N ₄ or the like or a polysilicon film for electrically insulating the adjacent photosensor cells, and impurities formed by an epitaxial technique or the like. A low-concentration n ⁻ region 5, a p region 6 serving as a base of a bipolar transistor doped with an impurity such as boron (B) by using an impurity diffusion technique or an ion implantation technique,
An n ⁺ region 7 serving as an emitter of a bipolar transistor formed by an impurity diffusion technique, an ion implantation technique, or the like, for reading a signal to the outside, for example, aluminum (Al), A
A wiring 8 formed of a conductive material such as 1-Si or Al-Cu-Si, an electrode 9 for applying a pulse to the p region 6 in a floating state through the insulating film 3, and a wiring 10 thereof.
An n ⁺ region 1 having a high impurity concentration, which is formed by an impurity diffusion technique or the like in order to make ohmic contact with the back surface of the substrate 1.
1. An electrode 12 made of a conductive material such as aluminum for giving a substrate potential, that is, a collector potential of a bipolar transistor.

Reference numeral 19 in FIG. 4A is a contact portion for connecting the n ⁺ region 7 and the wiring 8. Further, the alternating portions of the wiring 8 and the wiring 10 are so-called two-layer wiring, which are insulated from each other in an insulating region formed of an insulating material such as SiO ₂ . That is, it has a metal two-layer wiring structure.

The capacitor Cox of the equivalent circuit of FIG.
13 is composed of an electrode 9, an insulating film 3, and a p-region 6 MOS structure, and the bipolar transistor 14 is an n ⁺ region 7 as an emitter, a p region 6 as a base, an n ⁻ region 5 with a low impurity concentration, and a collector. Of n or n ⁺ region 1 of FIG. As is apparent from these drawings, the p region 6 is a floating region.

In the second equivalent circuit of FIG. 4C, the bipolar transistor 14 is connected to the base-emitter junction capacitance Cb.
e15, pn junction diode Dbe of base / emitter
16, the junction capacitance Cbc17 of the base-collector, and the pn junction diode Dbc18 of the base-collector. Here, originally as an equivalent circuit diagram,
The symbols indicating the two differently oriented current sources to be written in parallel with the pn junction diode Dbe16 and the pn junction diode Dbc18 are omitted.

The basic operation of the optical sensor cell will be described below with reference to FIG. The basic operation of this photosensor cell is composed of a charge accumulation operation by light incidence, a read operation and a refresh operation. First, the charge storage operation will be described.

In the charge storage operation, for example, the emitter is grounded through the wiring 8 and the collector is biased to a positive potential through the wiring 12. The base is assumed to be in a negative potential, that is, in a reverse bias state with respect to the emitter 7, by applying a positive pulse voltage to the capacitor Cox13 through the wiring 10 in advance. The operation of applying a pulse to the Cox 13 to bias the base 6 to a negative potential will be described in detail later in the description of the refresh operation.

In this state, when light 20 enters from the front side of the photosensor cell as shown in FIG. 4, electron-hole pairs are generated in the semiconductor. Of these, electrons flow out to the n region 1 side because the n region 1 is biased to a positive potential, but holes are gradually accumulated in the p region 6. Due to the accumulation of the holes in the p region, the potential of the p region 6 gradually changes toward the positive potential.

In FIGS. 4A and 4B, the lower surface of the light-receiving surface of each sensor cell is almost entirely occupied by the p region, and a part thereof is n.
⁺ Area 7 As a matter of course, the concentration of electron-hole pairs excited by light is larger as it is closer to the surface. Therefore, many electron-hole pairs are also excited by light in the p region 6. If the photoexcited electrons in the p region flow out of the p region 6 immediately without recombination and are absorbed in the n region, the holes excited in the p region 6 are accumulated as they are. The p region 6 is changed in the positive potential direction. When the impurity concentration of the p region 6 is made uniform, the photoexcited electrons are diffused and the p region 6 and the n ⁻ region 5 are exposed to the p region.
It flows to the n ⁻ junction, and thereafter is absorbed by the n collector region 1 by the drift due to the strong electric field applied to the n ⁻ region. Of course, the electrons in the p region 6 may travel only by diffusion. However, if the p-type impurity concentration is reduced from the surface to the inside, the difference in impurity concentration may cause the difference in impurity concentration. An electric field Ed from inside to the surface in the base,

[0036]

[Equation 1]

Occurs. Here, W _B is the depth from the light incident side surface of the p region 6, k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, N _AS is the surface impurity concentration of the p base region 6, and N _Ai is p. It is the impurity concentration at the interface between the region 6 and the n ⁻ high resistance region 5. Here, if N _AS / N _Ai > 3, the electrons in the p region 6 travel by drift rather than diffusion. That is, in order to effectively operate the carrier excited by light in the p region 6 as a signal, the impurity concentration of the p region 6 is designed to decrease inward from the light incident side surface. Is desirable. When the p region 6 is formed by diffusion, the impurity concentration decreases toward the inside as compared with the light incident side surface.

A part below the light receiving surface of the sensor cell is occupied by the n ⁺ region 7. Normally, the depth of the n ⁺ region 7 is 0.
Since it is designed to have a thickness of about 2 to 0.3 μm or less, the amount of light absorbed in the n ⁺ region 7 is not so large originally, so there is no problem so much. However, for light on the short wavelength side, particularly for blue light, the presence of the n ⁺ region 7 causes a decrease in sensitivity. The impurity concentration of the n ⁺ region 7 is usually 1 × 1
It is designed to be about 0 ²⁰ cm ^-3 or more. The diffusion distance of holes in the n ⁺ region 7 doped with such a high concentration of impurities is about 0.15 to 0.2 μm. Therefore, the pouring hole which is photoexcited in the n ⁺ region 7 to enable the p region 6, n ⁺ region 7 may be desirable that the impurity concentration toward the interior has a structure to decrease from the light incident surface. If the impurity concentration distribution in the n ⁺ region 7 is as described above, a strong drift electric field is generated from the light incident side surface toward the inside, and the holes photo-excited in the n ⁺ region 7 are immediately shifted to the p region 6 by the drift. Flow into If the impurity concentration of each of the n ⁺ region 7 and the p region 6 is configured to decrease from the light incident side surface toward the inside, the n ⁺ region 7 and the p region existing on the light incident side surface side of the sensor cell. All the carriers photo-excited at 6 work effectively as optical signals. When this n ⁺ region 7 is formed by impurity diffusion from a silicon oxide film or a polysilicon film doped with As or P at a high concentration, it is possible to obtain an n ⁺ region having a desirable impurity gradient as described above. It is.

Finally, the accumulation of holes causes the base potential to change to the emitter potential, and in this case to the ground potential, where it is clipped. More specifically, the base-emitter is deeply biased in the forward direction, and is clipped at a voltage at which holes accumulated in the base start to flow out to the emitter. That is, the saturation potential of the photosensor cell in this case is approximately given by the potential difference between the bias potential and the ground potential when the p region 6 is first biased to a negative potential. In the case where the n ⁺ region 7 is not grounded and the charge generated by the light input is stored in a floating state, the p region 6 can store the charge to approximately the same potential as the n region 1.

The above is a qualitative outline of the charge accumulation operation, but a little more concrete and quantitative explanation will be given below. The spectral sensitivity distribution of this optical sensor cell is given by the following equation.

[0041]

[Equation 2]

Here, λ is the wavelength of light [μm], α is the attenuation coefficient of light in the silicon crystal [μm ⁻¹ ], and x is recombination loss on the semiconductor surface, which does not contribute to sensitivity.
Adlayer "(dead region) thickness [μm], y is epitaxial layer thickness [μm], T is transmittance,
The ratio of the amount of light that effectively enters the semiconductor is shown in consideration of reflection and the like with respect to the amount of incident light. Spectral sensitivity S (λ) and irradiance Ee of this optical sensor cell
The photocurrent Ip is calculated by the following equation using (λ).

[0043]

(Equation 3)

However, irradiance Ee (λ) [μW · cm ^-2
-Nm- ¹ ] is given by the following equation.

[0045]

[Equation 4]

However, E _V is the illuminance [Lu
x], P (λ) is the spectral distribution of the light incident on the light receiving surface of the sensor, and V (λ) is the relative luminous efficiency of the human eye. Using these formulas, in the photosensor cell having the epi-thickness layer of 4 μm, the photocurrent of about 280 nA / cm ⁻² is obtained when the light is illuminated by the A light source (2854 ° K) and the sensor light receiving surface illuminance is 1 [Lux]. The number of incident photons or the number of generated electron-hole pairs is 1.8 × 10 ¹² /
It is about cm ² · sec.

At this time, the potential Vp generated by the accumulation of holes excited by light in the base is Vp =
Given by Q / C. Q is the amount of charge of holes accumulated, and C is the junction capacitance obtained by adding Cbe15 and Cbc17. Now, the impurity concentration of the n ⁺ region 7 is set to 10 ²⁰ cm ⁻³ ,
The impurity concentration of 5 × 10 ¹⁶ cm ^-3 in the p region 6, n ^- region 5
The impurity concentration of 10 ¹³ cm ⁻³ and the area of the n ⁺ region 7 is 16
μm ² , the area of the p region 6 is 64 μm ² , and the thickness of the n ⁻ region 5 is 3 μm, the junction capacitance is about 0.014 pF, while the number of holes accumulated in the p region 6 is ,
The accumulation time is 1/60 sec, the effective light receiving area, that is, the area obtained by subtracting the areas of the electrodes 8 and 9 from the area of the p region 6 is 5
When it is about 6 μm ² , the number is 1.7 × 10 ⁴ . Therefore, the potential Vp generated by light incidence is about 190 mV.

It should be noted here that when the resolution is increased and the cell size is reduced, the amount of light incident on one photosensor cell decreases, and the accumulated charge amount Q
However, since the junction capacitance also decreases in proportion to the cell size as the cell size is reduced, the potential Vp generated by light incidence is kept almost constant. This is because the above-mentioned optical sensor cell has an extremely simple structure as shown in FIG. 4 and has a possibility that the effective light receiving surface can be made extremely large.

This is one of the reasons why the above-mentioned photosensor cell is advantageous as compared with the case of the interline type CCD. With the increase in resolution, in the interline type CCD image pickup device, the amount of charge transferred. However, since the area of the transfer portion becomes relatively large and the effective light receiving surface is reduced, the sensitivity, that is, the voltage generated by light incidence is reduced. Further, in the interline type CCD image pickup device, the saturation voltage is limited by the size of the transfer part and decreases more and more, whereas in the photo sensor cell of the present invention, as described above, The saturation voltage is determined by the bias voltage when the p region 6 is first biased to a negative potential, and a large saturation voltage can be secured.

The operation of reading out the voltage generated by the charges accumulated in p region 6 as described above will be described below. In the read operation state, the emitter and the wiring 8 are in a floating state, and the collector is maintained at the positive potential Vcc.

FIG. 16 shows an equivalent circuit. Here again, the pn junction diodes Dbe16 and p are originally equivalent circuits.
The symbols indicating two differently directed current sources to be written in parallel with the n-junction diode Dbc18 are omitted. now,
If the potential when the base 6 is biased to a negative potential before light irradiation is −V _B and the accumulated voltage generated by light irradiation is V _P , the base potential becomes −V _B + V _P. ing. When a positive voltage V _R for reading is applied to the electrode 9 through the wiring 10 in this state, the positive potential V _R becomes equal to the oxide film capacitance Cox 13 and the base-emitter junction capacitance C.
Be15 and the base-collector junction capacitance Cbc7 divide the capacitance, and the base has a voltage.

[0052]

(5) Cox ──────────── V _R Cox + Cbe + Cbc are added. Therefore, the base potential is

[0053]

[Equation 6] Cox −V _B + V _P + −−−−−−−−−−−− ··· V _R Cox + Cbe + Cbc. here,

[0054]

[Formula 7] Cox −V _B + ─────────── ·· V _R = 0 If the condition of Cox + Cbe + Cbc is satisfied, the base potential is the accumulated voltage V _P generated by light irradiation. It becomes itself. When the base potential is biased in the positive direction with respect to the emitter potential in this way, electrons are injected from the emitter into the base, and the collector potential is positive. To reach. The current flowing at this time is given by the following equation.

[0055]

(Equation 8)

Where A _j is the junction area between the base and the emitter, q is the unit charge (1.6 × 10 ⁻¹⁹ coulomb), D
_n is the diffusion constant of electrons in the base, n _pe is the electron concentration as a minority carrier at the emitter end of the p base, W _B is the base width, N _Ae is the acceptor concentration at the base emitter alone, and N _Ac is the collector end of the base. Acceptor concentration at, k is Boltzmann's constant, T
Is the absolute temperature, and V _e is the emitter potential.

This current is generated when the emitter potential V _e is the base potential, that is, the accumulated voltage V generated by light irradiation here.
It is evident from the above equation that the current flows until it becomes equal to _P. Temporal variation of this time the emitter potential V _e is calculated by the following equation.

[0058]

[Equation 9]

However, the wiring capacitance Cs is the capacitance 21 of the wiring 8 connected to the emitter. FIG. 5 shows an example of the change over time of the emitter potential calculated using the above equation. According to FIG. 5, it takes about 1 second for the emitter potential to become equal to the base potential. This is not due to the fact that the emitter potential V _e does not flow is close happens when too much current to the V _P. Therefore, the means to solve this is to apply the positive voltage V _R to the electrode 9 first,

[0060]

[Formula 10] Cox −V _B + ─────────── ・ VR _R = 0 Cox + Cbe + Cbc is set, but instead of this condition,

[0061]

[Equation 11] Cox −V _B + ─────────── ·· V _R = V _{Bias The} condition of Cox + Cbe + Cbc is inserted and the base potential is biased by V _{Bias in} an extra forward direction. . The current flowing at this time is given by the following equation.

[0062]

(Equation 12)

In FIG. 6, when V _Bias = 0.6 V, after a certain period of time, V _R applied to the electrode 9 is returned to zero volt, and the accumulated voltage V when the flowing current is stopped
The relationship between the read voltage and the emitter potential with respect to _P is shown. However, in FIG. 6, the read voltage is always added with a constant potential that depends on the read time due to the bias voltage component, but the value obtained by subtracting the amount of the error is plotted. When the positive voltage V _R applied to the electrode 9 is returned to zero volt, the reverse of the application

[0064]

Since Equation 13] _{Cox -─────────── · V R Cox + Cbe} + Cbc becomes voltage is added to the base potential, a base potential, before applying a positive voltage V _R state, i.e., - V _B
And the current is stopped because the emitter is reverse-biased. Taking According to FIG. 6 100 ns about more read time (i.e., time the application of the V _R to the electrode 9), the reserved voltage V _P and the read voltage linearity is ensured over a range of about four orders of magnitude, faster Is possible to read. In FIG. 6, the 45 ° line is a result when a sufficient time is taken for reading. In the above calculation example, the capacitance Cs of the wiring 8 is 4 pF, which is 0.014 pF of the junction capacitance of Cbe + Cbc. Figure that despite even about 300-fold compared large, accumulated voltage V _P generated in the p region 6 is not subject to any attenuation, and that the effect of the bias voltage, which is read out very fast and 6 shows. This is because the amplifying function of the photosensor cell according to the above configuration, that is, the charge amplifying function is effectively working.

On the other hand, in the conventional MOS type image pickup device, the accumulated voltage V _P is Cj · V _P / (Cj + Cs) (where Cj is the value of the MOS type image pickup device) due to the influence of the wiring capacitance Cs in such a reading process. The pn junction capacitance of the light receiving portion) occurs, and there is a drawback in that the read voltage value of two digits decreases. Therefore, in the MOS type image pickup device, fixed pattern noise due to variations in the parasitic capacitance of the switching MOS transistor for reading to the outside or random noise generated due to large wiring capacitance, that is, output capacitance is large, and the S / N ratio is high. However, in the photosensor cell having the configuration shown in FIGS. 4A, 4B, and 4C, the accumulated voltage generated in the p region 6 is read out to the outside. Is relatively large, fixed pattern noise and random noise due to output capacitance are relatively small, and it is possible to obtain a signal with a very good S / N ratio.

It has been shown above that when the bias voltage V _Bias is set to 0.6 V, linearity of about 4 digits can be obtained in a high-speed read time of about 100 nsec. This linearity, read time and bias voltage Further _details of the calculation result of the relationship of V _Bias are shown in FIG. 7.

In FIG. 7, the horizontal axis represents the bias voltage V _Bias.
And the vertical axis represents the read time. The parameters show the time dependence of the read voltage to 80%, 90%, 95%, and 98% of 1 mV when the storage voltage is 1 mV. As shown in FIG. 6, at an accumulation voltage of 1 mV, 80%, 90%, 95%,
At 98%, it is clear that the higher the accumulated voltage, the better the value.

According to FIG. 7, when the bias voltage V _Bias is 0.6 V, the read voltage becomes 80% of the accumulated voltage and the read time becomes 0.12 μs, and 90% becomes 0.2.
It can be seen that 7 μs and 95% are 0.54 μs and 98% are 1.4 μs. Further, it is shown that higher-speed reading is possible if the bias voltage V _Bias is set to be larger than 0.6 V. As described above, when the read time and the required linearity are determined from the overall design of the imaging device, the required bias voltage V _Bias can be determined by using the graph of FIG.

Another advantage of the optical sensor cell having the above structure is that holes accumulated in the p region 6 can be read nondestructively because the recombination probability of electrons and holes in the p region 6 is extremely small. is there. That is, when returning the voltage V _R which has been applied to the electrode 9 during the readout to zero volts, the potential of the p region 6 becomes reverse biased before the application of the voltage V _R, the reserved voltage V _P generated by light irradiation As long as the light is not newly irradiated, it is stored as it is. This means that when the photosensor cell according to the above configuration is configured as a photoelectric conversion device, a new function can be provided in terms of system operation.

The time during which the storage voltage V _P can be held in the p region 6 is extremely long, and the maximum holding time is rather limited by the dark current thermally generated in the depletion layer of the junction. That is, the photosensor cell is saturated by the thermally generated dark current. However, in the optical sensor cell according to the above configuration, the region where the depletion layer spreads is the n ⁻ region 5 which is a low impurity concentration region, and this n ⁻ region 5 is about 10 ¹² cm ⁻³ to 10 ¹⁴ cm ^−3. Since the impurity concentration is extremely low, the crystallinity is good, and there are few electron-hole pairs that are thermally generated, as compared with the MOS type and CCD type image pickup devices. For this reason, the dark current is smaller than other conventional devices. That is, the photosensor cell according to the above configuration has a structure with essentially low dark current noise.

Next, the operation of refreshing the charges accumulated in p region 6 will be described. In the photosensor cell according to the above configuration, as described above, the charge accumulated in the p region 6 does not disappear in the read operation. Therefore, in order to input new optical information, a refresh operation for extinguishing previously accumulated electric charges is required. At the same time, it is necessary to charge the potential of the floating p region 6 to a predetermined negative voltage.

In the photosensor cell having the above structure, the refresh operation is performed by applying a positive voltage to the electrode 9 through the wiring 10, similarly to the read operation. At this time, the emitter is grounded through the wiring 8. The collector is the electrode 12
To ground or positive potential. FIG. 3 shows an equivalent circuit of the refresh operation. However, an example in which the collector side is grounded is shown.

When a voltage of positive voltage V _RH is applied to the electrode 9 in this state, the oxide film capacitance Cox1 is formed on the base 22.
3, the base-emitter junction capacitance Cbe15,
By dividing the junction capacitance Cbc17 between collectors,

[0074]

[Formula 14] Cox ─────────── ・ V _RH Cox + Cbe + Cbc The voltage is instantaneously applied as in the previous read operation. With this voltage, the base-emitter junction diode Dbe16 and the base-collector junction diode Dbc18 are forward-biased and in a conducting state, current starts to flow, and the base potential gradually decreases.

At this time, the change in the potential V of the base in the floating state is approximately represented by the following equation.

[0076]

## EQU15 ## dV (Cbe + Cbc)-=-(i ₁ + i ₂ ) dt where

[0077]

[Equation 16]

I ₁ is the current flowing through the diode Dbc, i
₂ is a current flowing through the diode Dbe. A _b is the base area, Ae is the emitter area, Dp is the diffusion constant of holes in the collector, p _ne the hole concentration of the thermal equilibrium in the collector, Lp is the mean free path, n _pe is in the base of the hole in the collector It is the electron concentration in thermal equilibrium. At i ₂ , the current due to hole injection from the base side to the emitter is negligible since the impurity concentration of the emitter is sufficiently higher than the impurity concentration of the base.

The above-mentioned formula is an approximation of stepwise junction, which is deviated from stepwise junction in an actual device, and the base is thin and has a complicated concentration distribution. However, the refresh operation can be explained with a good approximation. Of the current i ₁ flowing between the base and collector in the above equation, q · Dp · p _ne / Lp represents the current due to holes, that is, the component in which holes flow from the base to the collector side. In the photosensor cell according to the above configuration, the impurity concentration of the collector is designed to be slightly lower than that of a normal bipolar transistor so that the current due to the hole easily flows.

FIG. 8 shows an example of the time dependence of the base potential calculated using this equation. The abscissa indicates the lapse of time from the moment when the refresh voltage V _RH is applied to the electrode 9, that is, the refresh time, and the ordinate indicates the base potential. Also, the initial potential of the base is used as a parameter. The initial potential of the base is a potential indicated by the base in a floating state at the moment when the refresh voltage V _RH is applied, and is determined by V _RH , Cox, Cbe, Cbc, and electric charges accumulated in the base.

As shown in FIG. 8, the potential of the base does not depend on the initial potential, but always drops according to one straight line on a semi-logarithmic graph after a certain period of time. FIG. 9 shows experimental values of changes in base potential with respect to refresh time.
Compared to the calculation example shown in FIG. 8, the test device used in this experiment has a considerably large dimension, so the absolute value does not match the calculation example, but the change in the base potential with respect to the refresh time is on a semi-logarithmic graph. It is proved that it is changing linearly. This experimental example shows a value when both the collector and the emitter are grounded.

Now, assuming that the maximum value of the storage voltage V _P due to light irradiation is 0.4 [V] and the voltage V applied to the base by the refresh voltage V _RH is 0.4 [V], as shown in FIG. The maximum value of the initial base potential is 0.8 [V], and after 10 ^-15 [sec] after the refresh voltage is applied, the base potential starts to drop in a straight line, and after 10 ^-5 [sec], light is emitted. When there is not, that is, when the initial base potential is 0.4 [V], it matches the potential change.

There are two ways in which the p region 6 is charged to a negative potential by applying a positive voltage through the MOS capacitor Cox for a certain period of time and removing the positive voltage. One is an operation in which holes having a positive charge flow out of the p region 6 into the n region 1 which is mainly in the ground state, whereby negative charges are accumulated. In order for holes from the p region 6 to flow unilaterally to the n region 1 and to prevent electrons in the n region 1 from flowing into the p region 6 too much, the impurity density of the p region 6 is changed to the impurity density of the n region 1. It should be higher.
On the other hand, electrons from the n ⁺ region 7 and the n region 1 flow into the p region 6 and recombine with holes, thereby forming the p region 6.
The operation of accumulating negative charges can also be performed. In this case, the impurity density of n region 1 is higher than that of p region 6. p
The operation of accumulating negative charges by holes flowing out of the region 6 is much faster than the operation of accumulating negative charges by electrons flowing into the base of the p region 6 and recombining with holes. However, according to the experiments performed so far, it has been confirmed that even the refresh operation of injecting electrons into the p region 6 exhibits a sufficiently fast time response to the operation of the photoelectric conversion device.

When a large number of optical sensor cells having the above structure are arranged in the XY direction to form a photoelectric conversion device, the accumulated voltage V _{P in} each sensor cell is 0 to 0 in the above example depending on the image.
Although it fluctuates between 0.4 [V], a constant voltage of about 0.3 [V] remains in the base of all sensor cells at 10 ^-5 [sec] after application of the refresh voltage V _RH. , change in storage voltage V _P by the image it can be seen that disappear all. That is, in the photoelectric conversion device using the optical sensor cell according to the above configuration, the complete refresh mode in which the base potentials of all the sensor cells are brought to zero volts by the refresh operation (at this time, 10 [sec] is required in the example of FIG. 8), There are two transient refresh modes in which a certain constant voltage remains in the base potential, but the fluctuation component due to the accumulated voltage V _P disappears (in this case, 10 [μsec] to 1 in the example of FIG. 8).
0 [sec] refresh pulse). In the above example,
The voltage V applied to the base by the refresh voltage V _RH
Although the _A and 0.4 V, the voltage V _A 0.6
[V], the transient refresh mode is
According to FIG. 8, it occurs in 1 [nsec], and refreshing can be performed at an extremely high speed. The selection between operation in the complete refresh mode and operation in the transient refresh mode is determined by the purpose of use of the photoelectric conversion device.

When the voltage remaining at the base in this transient refresh mode is V _K , the refresh voltage V _RH
Is applied, the transient state at the moment when V _RH is returned to zero volt,

[0086]

## EQU17 ## Since a negative voltage of Cox −−−−−−−−−−−−−− ・ V _RH Cox + Cbe + Cbc is added to the base, the base potential after the refresh operation by the refresh pulse is

[0087]

Equation 18] _{Cox V K -─────────── · V RH Cox} + Cbe + Cbc , and the base is reverse biased with respect to the emitter.

In the storage operation for storing the carriers excited by light, it was explained that the base is in the reverse bias state in the storage state. This refresh operation brings the refresh and the base into the reverse bias state. The two operations of going forward are performed at the same time.

FIG. 10 shows the base potential after the refresh operation with respect to the refresh voltage V _RH .

[0090]

[Number 19] shows the experimental values of the change in the _{Cox V K -─────────── · V RH Cox} + Cbe + Cbc. The value of Cox is taken as a parameter from 5 pF to 100 pF. The circles are experimental values, and the solid line is

[0091]

[Expression 20] Cox V _K −−−−−−−−−−−−−− V _RH Shows a calculated value calculated from Cox + Cbe + Cbc. At this time, V _K =
0.52 V, and Cbc + Cbe = 4 pF. However, the probe capacity of the observation oscilloscope is 13 pF
Are connected in parallel to Cbc + Cbe. Like this
The calculated value and the experimental value completely match, and the refresh operation has been experimentally confirmed.

In the above refresh operation, FIG.
As described above, an example in which the collector is grounded has been described, but it is also possible to perform the operation with the collector at a positive potential. At this time, even if the refresh pulse is applied to the base-collector junction diode Dbc18,
If the positive potential applied to the collector is higher than the potential applied to the base by this refresh pulse, the current will flow through only the base-emitter junction diode Dbe16 since the non-conductive state is maintained. For this reason, the decrease in the base potential becomes relatively slower than when the collector is grounded, but basically, exactly the same fast refresh operation as described above is performed.

That is, the relationship of the base potential with respect to the refresh time in FIG. 8 is that the oblique straight line when the base potential in FIG. 8 decreases shifts to the right side, that is, in the direction requiring more time. Therefore, if the same refresh voltage V _RH as when the collector is grounded is used, it takes time to refresh. However, if the refresh voltage V _RH is slightly increased, a high-speed refresh operation can be performed as in the case where the collector is grounded. It is possible.

The above is the description of the basic operation of the photosensor cell according to the above-described configuration, which includes the charge accumulation operation, the read operation, and the refresh operation by the incident light. As explained above,
The basic structure of the optical sensor cell having the above structure is described in the above-mentioned JP-A-56-150878 and JP-A-56-15.
It has a very simple structure as compared with Japanese Patent Application Laid-Open No. 7073 and Japanese Patent Application Laid-Open No. 56-165473, and can sufficiently cope with high resolution in the future. The advantages of output, wide dynamic range, non-destructive readout, etc. are preserved as they are.

Next, the photosensor cells having the above-described structure are arranged in a two-dimensional array , and the signal processing device is used to transmit signals.
A configuration example of a photoelectric conversion device which performs signal reading will be described with reference to the drawings. Before explaining the present invention, here
In the case where there is only one signal processing means, photoelectric conversion
The configuration and operation of the device will be described.

The basic optical sensor cell structure is two-dimensionally 3 × 3.
FIG. 15 shows a circuit configuration diagram of the photoelectric conversion device arranged in the above.
The basic optical sensor cell 30 surrounded by the dotted line described above
(At this time, it is shown that the collector of the bipolar transistor is connected to the substrate and the substrate electrode.), Horizontal lines 31, 31 ', 31 "for applying the read pulse and the refresh pulse, for generating the read pulse Vertical shift register 32, vertical shift register 3
Buffer M between 2 and the horizontal line 31, 31 ', 31 "
Terminals 34 for applying a pulse to the gates of the OS transistors 33, 33 ', 33 ", and buffer MOS transistors 35, 3 for applying a refresh pulse.
5 ', 35 ", terminal 36 for applying a pulse to its gate, terminal 3 for applying a refresh pulse
7. Vertical lines 38, 38 ', 38 "for reading the accumulated voltage from the basic photosensor cell 30, a horizontal shift register 39 for generating a pulse for selecting each vertical line,
MOS transistors for gate 40, 40 ', 40 "for opening and closing each vertical line, an output line 41 for reading the accumulated voltage to the amplifier section, and a MOS transistor for refreshing the charges accumulated in the output line after reading. 42, a terminal 43 for applying a refresh pulse to the MOS transistor 42, a bipolar transistor 44 for amplifying an output signal, a transistor 44 such as MOS, FET, J-FET, a load resistor 45, and a terminal for connecting the transistor and a power supply. 46, an output terminal 47 of the transistor, MOS transistors 48, 48 ', 48 "for refreshing the charges accumulated in the vertical lines 40, 40', 40" in the read operation, and a MOS transistor 4
This photoelectric conversion device is constituted by terminals 49 for applying pulses to the gates of 8, 48 ', 48 ".

The operation of this photoelectric conversion device will be described with reference to the pulse timing charts shown in FIGS. In FIG. 11, section 61 corresponds to the refresh operation, section 62 corresponds to the accumulation operation, and section 63 corresponds to the read operation. At time t ₁ , the substrate potential, that is, the collector potential 64 of the photosensor cell portion is kept at the ground potential or the positive potential, but FIG. 11 shows that it is kept at the ground potential. Whether it is the ground potential or the positive potential, as described above, the time required for refreshing is different, and the basic operation does not change. The potential 65 of the terminal 49 is high, the MOS transistors 48, 48 ', 48 "are kept conductive, and each photosensor cell is grounded through the vertical lines 38, 38', 38". Further, a voltage for conducting the buffer MOS transistor is applied to the terminal 36 as shown by the waveform 66, and the buffer MOS transistors 35, 35 ', 35 "for all-screen batch refresh are in the conducting state. When a pulse like the waveform 67 is applied to 37, a voltage is applied to the base of each photosensor cell through the horizontal lines 31, 31 'and 31 ", and as described above, the refresh operation is started and the charge is accumulated before that. Charge is refreshed according to the complete refresh mode or the transient refresh mode. Whether to enter the complete refresh mode or the transient refresh mode is determined by the pulse width of the waveform 67.

At time t ₂ , as described above, the base of the transistor of each photosensor cell is reverse biased with respect to the emitter, and the operation proceeds to the next accumulation section 62. In the refresh section 61, as shown in the figure, all the other applied pulses are kept in the low state.

In the accumulation operation section 62, the substrate voltage,
That is, the collector potential waveform 64 of the transistor is set to a positive potential. As a result, electrons of the electron-hole pairs generated by the light irradiation can quickly flow to the collector side. However, keeping the collector potential at a positive potential is not an essential condition since imaging is performed with the base in a reverse bias state with respect to the emitter, that is, a negative potential. There is no change in the typical accumulation operation.

In the storage operation state, the potential 65 of the gate terminals 49 of the MOS transistors 48, 48 ', 48 "is 65.
Is kept high as in the refresh period, and each M
The OS transistor remains conductive. Therefore, the emitter of each photosensor cell is connected to the vertical line 38, 38 ', 3
8 ". Holes are accumulated in the base due to strong light irradiation, and when the base is saturated, that is, when the base potential is in a forward bias state with respect to the emitter potential (ground potential), The hole is a vertical line 38,
38 ', 38 ", where the base potential change stops and is clipped. Thus, the emitters of the vertically adjacent photosensor cells are commonly connected by vertical lines 38, 38', 38". Even
When the vertical lines 38, 38 ', 38 "are grounded in this way, no blooming phenomenon occurs.

A method for avoiding this blooming phenomenon is M
Even when the OS transistors 48, 48 ', 48 "are in the non-conducting state and the vertical lines 38, 38', 38" are in the floating state, the substrate potential, that is, the collector potential 64 is set to a slightly negative potential and the hole This can also be achieved by allowing the base potential to flow toward the collector side before the emitter when the base potential changes in the positive potential direction due to the accumulation.

After the accumulation section 62, the reading section 63 starts from time t ₃ . At time t _3, MOS transistors 48, 48 ', the potential 65 of the gate terminal 49 of the 48 "to low, and the horizontal lines 31, 31', 3
1 "buffer MOS transistors 33, 33 ', 3
The potential 68 of the 3 ″ gate terminal is set to high, and the respective MOS transistors are turned on. However, the timing of setting the potential 68 of the gate terminal 34 to high is not an indispensable condition that it is time t ₃ . Any time earlier than that is fine.

At time t ₄ , of the outputs of the vertical shift register 32, the one connected to the horizontal line 31 has the waveform 6
At this time, since the MOS transistor 33 is in a conductive state, reading of each of the three photosensor cells connected to the horizontal line 31 is performed. This read operation is as previously described,
The signal voltage generated by the signal charge stored in the base region of each photosensor cell is directly applied to the vertical lines 38, 3
8 ', 38 ". The pulse width of the pulse voltage from the vertical shift register 32 at this time is such that the read voltage with respect to the storage voltage maintains a sufficient linearity as shown in FIGS. The pulse voltage is set, and the pulse voltage is adjusted so that the emitter is forward biased by V _{Bias as} described above.

Next, at time t ₅ , of the outputs of the horizontal shift register 39, only the output to the gate of the MOS transistor 40 connected to the vertical line 38 has the waveform 7
0, the MOS transistor 40 becomes conductive, and the output signal is output through the output line 41.
The current enters the output transistor 44, is amplified, and is output from the output terminal 47. After the signal in this manner is read, since the output line 41 is left signal charge due to wiring capacitance, at time t _6, MOS transistor 42
A pulse is applied to the gate terminal 43 as shown in the pulse waveform 71, the MOS transistor 42 is turned on, the output line 41 is grounded, and the remaining signal charges are refreshed. In the same manner, the switching MOS transistors 40, 40 ', 40 "are sequentially turned on to read the signal output of the vertical lines 38, 38', 38". After reading the signals from the photosensor cells for one line arranged horizontally in this way, the vertical lines 38, 3 are read.
Similar to the output line 41, signal charges due to the wiring capacitance of the output line 41 remain in 8'and 38 ", so that the MOS transistors 48 and 48 'connected to the vertical lines 38, 38' and 38" are connected. , 48 ″ is made high to its gate terminal 49 as shown by the waveform 65 to make it conductive, and this residual signal charge is refreshed.

Next, at time t ₈ , of the outputs of the vertical shift register 32, the output connected to the horizontal line 31 ′ becomes high as shown by the waveform 69 ′, and the accumulation of each photosensor cell connected to the horizontal line 31 ′ is accumulated. The voltage is read out to each vertical line 38, 38 ', 38 ". Thereafter, the signal is read out from the output terminal 47 by the same operation as before.

In the above description, the application field in which the accumulation section 62 and the reading section 63 are clearly divided, for example, the operation state applied to the still video which has been actively researched and developed recently has been described. However, it can be applied to an application field in which the operation in the accumulation section 62 and the operation in the reading section 63 are simultaneously performed, such as a television camera, by changing the pulse timings in FIGS. 11 and 12. However, the refresh at this time requires a refresh function for each line, not a full screen batch refresh. For example, after the signal of each photosensor cell connected to the horizontal line 31 is read, the time t
MOS transistors 48, 48 'for erasing charges remaining in the vertical line at _7, to conduct 48 ", applying a refresh pulse to the horizontal line 31 at this time. That is, even at the time t ₇ in the waveform 69 This can be achieved by using a vertical shift register configured to generate pulses having different pulse voltages and pulse widths as at time t _{4. Thus} , except for the double pulse operation, the right side of FIG. In place of the device for applying the batch refresh pulse installed on the right side, a second vertical shift register similar to that on the left side is provided on the right side, and the timing can be achieved by shifting the timing from the vertical register provided on the left side. It is possible.

At this time, the degree of freedom in the operation of suppressing the blooming by manipulating the potentials of the emitter and collector of each photosensor cell in the accumulation state as described above is reduced. However, as it has been explained in the basic operation, the read state, since the such a structure can high-speed reading at the time of applying a V _Bias becomes bias voltage to the base, as can be seen from the graph of FIG. 5, V _Bias Vertical line 2 due to saturation of each photosensor cell when no voltage is applied.
The amount of signal charges flowing out to 8, 28 ', 28 "is extremely small, and the blooming phenomenon does not pose any problem.

Also, with respect to the smear phenomenon, the photoelectric conversion device according to this configuration example can obtain extremely excellent characteristics. The smear phenomenon is a problem that occurs in operation and structure in which charge is transferred where light is irradiated in a CCD type image pickup device, particularly in a frame transfer type,
In the interline type, there is a problem that occurs because carriers generated in a deep part of the semiconductor due to long-wavelength light are accumulated in the charge transfer portion.

Further, in the MOS type image pickup device, there is a problem that carriers generated in a deep semiconductor region are accumulated by light of a long wavelength on the drain side of a switching MOS transistor which is grounded to each photosensor cell. On the other hand, in the photoelectric conversion device according to the present configuration example, there is no smear phenomenon that occurs due to operation and structure, and there is no phenomenon that carriers generated in the semiconductor deep portion are accumulated due to long wavelength light. However, among the electrons and holes generated relatively near the surface of the emitter of the photosensor cell, there is a concern about the development that electrons are accumulated, but this is because the emitter is grounded in the accumulation operation state during the batch refresh operation. Therefore, electrons are not accumulated, and no smear phenomenon occurs. In the case of a line refresh operation applied to a normal television camera, the vertical line is grounded and refreshed before reading the accumulated voltage to the vertical line during the horizontal blanking period. The electrons accumulated during one horizontal scanning period flow out, so that the smear phenomenon hardly occurs. As described above, in the photoelectric conversion device according to the present configuration example, smear development occurs only to an essentially negligible degree in terms of structure and operation, and one of the great advantages of the photoelectric conversion device according to the present configuration example. Is one.

Further, the operation of suppressing the blooming phenomenon by operating the respective potentials of the emitter and the collector in the accumulation operation state has been described above, but it is also possible to control the γ characteristic by utilizing this. That is, during the accumulation operation, the potential of the emitter or the collector is temporarily set to a certain negative potential, and the holes accumulated in the base more than the number of carriers giving the negative potential out of the carriers accumulated in the base are changed to the emitter or the collector. The operation of flowing to the collector side is performed. As a result, the relationship between the storage voltage and the incident light amount shows the characteristic of γ = 1 of the silicon crystal when the incident light amount is small, and shows the characteristic that γ is smaller than 1 when the incident light amount is large. That is, γ =
It is possible to have the characteristic of 0.45. If the above operation is performed once in the middle of the accumulation operation, a one-fold line approximation is obtained. If the negative potential applied to the emitter or the collector is appropriately changed twice, a two-fold line type γ characteristic can be provided.

Further, in the above configuration example, the silicon substrate is used as a common collector, but it is also possible to provide a buried n ⁺ region like a bipolar transistor and divide the collector for each line. Note that, in addition to the pulse timing shown in FIG. 11, a clock pulse for driving the vertical shift register 32 and the horizontal shift register 39 is necessary for the actual operation.

FIG. 13 shows an equivalent circuit related to the output signal. The capacitance C _V 80 is the wiring capacitance of the vertical lines 38, 38 ′, 38 ″, and the capacitance C _H 81 is the wiring capacitance of the output line 41. The equivalent circuit on the right side of FIG. And M for switching
OS transistor 40, 40 ', 40 "is conductive, indicating a resistance value in its conductive state by a resistor R _M 82. The resistance of the amplification transistor 44 r _e 83
And an equivalent circuit using the current source 84. The MOS transistor 42 for refreshing the charge accumulation caused by the wiring capacitance of the output line 41 is non-conductive in the read state and has a high impedance, so that it is omitted in the equivalent circuit on the right.

Each parameter of the equivalent circuit is determined by the size of the photoelectric conversion device actually configured. For example, the capacitance C _V 80 is about 4 pF, and the capacitance C _H 81
Is about 4 pF, and the resistance R of the conductive state of the MOS transistor
FIG. 14 shows an example in which the output signal waveform observed at the output terminal 47 is calculated assuming that _M 82 is about 3 KΩ and the current amplification factor β of the bipolar transistor 44 is about 100.

In FIG. 14, the horizontal axis represents the switching MOS.
The vertical axis represents the time [μs] from the moment when the transistors 40, 40 ′, 40 ″ are turned on, and the vertical axis represents the vertical lines 38, 38 ′, 3
The output voltage [V] that appears at the output terminal 47 when the signal charge is read from each photosensor cell and a voltage of 1 volt is applied to the wiring capacitance C _V 80 of 8 ″ is shown.

The output signal waveform 85 shows that the load resistance R _E 45 is 1
0KΩ, 86 is a load resistor R _E 45 5KΩ, 87 are those when the load resistor R _E 45 is 2K ohms, the peak value in either the, 0.5V about by the capacitance division of the C _V 80 and C _H 81 It has become. As a matter of course, the larger the load resistance R _E 45 is, the smaller the attenuation amount is, and the desired output waveform is obtained. The rise time is as fast as about 20 nsec for the above parameter values. By reducing the resistance R _M of the switching MOS transistors 40, 40 ′ and 40 ″ in the conductive state and the wiring capacitances C _V and C _H , it is possible to read data at a higher speed.

In the photoelectric conversion device using the photosensor cell having the above structure, the voltage appearing at the output is large due to the amplification function of each photosensor cell, and therefore the amplification amplifier at the final stage is considerably larger than that of the MOS type image pickup device. A simple one will do. In the above example, an example in which a single-stage bipolar transistor is used has been described. However, it is of course possible to use another method such as a two-stage structure. When a bipolar transistor is used as in this example, the problem of 1 / f noise that is easily noticeable on an image generated from the MOS transistor of the last stage amplifier in the CCD imaging device does not occur in the photoelectric conversion device of this configuration example. It is possible to obtain an image having an extremely good S / N ratio.

Another example of the structure of the photoelectric conversion device will be described below. This configuration example is intended to solve the inconvenience in the transient refresh mode. In FIG.
The potential levels at the emitter, base, and collector parts during the cycle of transient refresh operation, accumulation operation, read operation, and transient refresh operation are shown. The voltage level of each portion is a potential seen from the outside, and there are some portions that do not partially match the internal potential level.

To simplify the explanation, the diffusion potential between the emitter and the base is omitted. Therefore, when the emitter and the base are represented at the same level in FIG.

[0119]

[Equation 21]

That is, there is a diffusion potential given by. In FIG. 12, state represents a refresh operation, state represents a storage operation, state represents a read operation,
The states indicate the operating states when the emitter is grounded. In addition, the potential level is negative at the upper side of 0 volt,
The lower side shows the positive potential, respectively. It is assumed that the base potential before the state is zero volts, and that the collector potential is all biased to the positive potential from the state.

The above series of operations will be described with reference to the timing chart of FIG. As shown by the waveform 67 in FIG. 11, time t ₁
When a positive potential, that is, the refresh voltage V _RH is applied to the terminal 37, the base has the potential 200 as shown in FIG.

[0122]

[Expression 22] Cox ──────────── V _RH Cox + Cbe + Cbc A partial pressure is applied. This potential gradually decreases toward the zero potential from time t ₁ to t ₂ , and becomes the potential 201 shown by the dotted line in FIG. 12 at time t ₂ . This potential is the potential V _K remaining at the base in the transient refresh mode, as described above. At time t ₂ , as shown by a waveform 67, the base is set at the moment when the refresh voltage V _RH returns to the zero voltage.

[0123]

[Equation 23] Cox − ─────────── V _RH Cox + Cbe + Cbc is generated by capacitance division as before, so that the base adds the remaining voltage V _K to the newly generated voltage. It becomes the electric potential. That is, the base potential 202 shown in the state, which is

[0124]

## EQU24 ## Cox V _K − ──────────── V _RH Cox + Cbe + Cbc

When light is incident on such an emitter in a reverse bias state, holes generated by this light are accumulated in the base region.
Base potential 202 according to the intensity of the incident come light base potential 203 and 203 'changes toward increasingly positive potential as the 203 ". The voltage generated by the light V _P
And

[0126] Then as the waveform 69, the voltage from the vertical shift register to the horizontal line, i.e., the read voltage V _R
Is applied to the base

[0127]

(25) Since the voltage Cox ─────────── VR _R Cox + Cbe + Cbc is added, the base potential 204 when no light is emitted is

[0128]

[Number 26] Cox V _K + ─────────── the _{(V R -V RH) Cox +} Cbe + Cbc. The potential 204 at this time is, as described above,
It is set so that the emitter is biased in the forward direction by about 0.5 to 0.6 V. Also, the base potential 20
5, 205 ', 205 "are each

[0129]

Cox (V _R −V _RH ) V _K + V _P + ──────────── Cox + Cbe + Cbc Cox (V _R −V _RH ) V _K + V _P ′ + ──────── ──── Cox + Cbe + Cbc Cox ( V R -V RH) V K + V P "+ ─────────── given by Cox + Cbe + Cbc.

The base potential is thus
When forward biased, electrons are injected from the emitter side, and the emitter potential gradually moves in the positive potential direction. The emitter potential 206 with respect to the base potential 204 when light is not irradiated is about 50 to 100 mV when the read pulse width is about 1 to 2 μs when the forward bias is set to 0.5 to 0.6 V. , If this voltage is V _B , the emitter potentials 207, 2
07 'and 207 "have sufficient linearity as long as the pulse width is 0.1 μs or more as in the previous example.
_P + V _B , V _P ′ + V _B , and V _P ″ + V _B.

After a certain read time, when the read voltage V _R becomes zero potential as shown by the waveform 69, the base has

[0132]

[Equation 28] Cox − ─────────── ・ V _R Cox + Cbe + Cbc Since the voltage is added, the base potential becomes the state before the read pulse is applied, that is, the reverse bias state, as in the state. And the change in the potential of the emitter stops. That is, the base potential 208 at this time is

[0133]

Cox V _K − ─────────── ・ V _RH Cox + Cbe + Cbc Base potentials 209, 209 ′, and 209 ″ are respectively

[0134]

[Formula 30] Cox V _K + V _P −─────────── ・ V _RH Cox + Cbe + Cbc Cox V _K + V _P ′ −─────────── ・ V _RH Cox + Cbe + Cbc Cox V _K + given by _{V P "-─────────── · V RH Cox} + Cbe + Cbc. This is exactly the same as the state before the reading begins.

In this state, the optical information signal on the emitter side is read out to the outside. After this reading is completed, each switching MOS transistor 48, 4
8 ', 48 "are turned on and the emitter is grounded, as in the state where the emitter is grounded.
The cycle goes through the refresh operation, the accumulation operation, and the read operation, and then returns to the state. At this time, before the first refresh operation is started, the base potential starts from zero potential, but goes around once. After that, the base potential

[0136]

[Expression 31] Cox V _K −─────────── ・ V _RH Cox + Cbe + Cbc and the potentials obtained by adding V _P , V _P ′, and V _P ″, respectively. Therefore, in this state, even if the refresh voltage V _RH is applied, the base potentials are V _K , V _K + V _P , V _K + V _P ′, respectively.
V _K + V _P ″. In this case, a sufficient forward bias is not applied to the base, and where the light is strongly applied, the forward bias amount is large, so that the optical information is lost.
It is obvious from the calculation example of the refresh operation shown in FIG. 8 that the information of the weak light portion remains without disappearing.

Such a phenomenon is peculiar to the transient refresh mode, and in the complete refresh mode, such a problem does not occur because it takes a long refresh time until the base potential always becomes zero potential. A method of using the transient refresh mode capable of high-speed refresh and avoiding such inconvenience will be described below.

One way to solve this is that the base potential 210 is in the negative potential direction, that is, in the reverse bias direction with respect to the emitter in the state,
In the next state, it suffices to bring the base potential 210 to the zero potential or a slightly positive potential by some method before the refresh pulse is applied.

FIG. 24 (a) is a sectional view of an optical sensor cell for achieving this, and FIG. 24 (b) is an equivalent circuit diagram thereof.
The internal potential diagrams are shown in (c). FIG.
(A) differs from the sensor cell shown in FIG. 4 only in that it has a buried p ⁺ region 220. In the equivalent circuit diagram of FIG. 24B, the base region 6 of the sensor cell is the collector, the buried p ⁺ region 220 is the emitter, and a part of the high resistance n ⁻ region 5 between the base region 6 and the collector region 1 is the base. The pnp transistor 221 is added. The base region of the pnp transistor is loosely coupled with the collector region 1 of the sensor cell, and is shown by a dotted line in the equivalent circuit. Also, this buried p ⁺ region 2
20 is connected inside the crystal like a wiring 222,
It has a structure that voltage can be applied from outside the sensor area.

As is apparent from FIG. 24B, the p ⁺ buried region 220 forms one line in the horizontal line direction as indicated by 222, so in practice,
In FIG. 24 (a), it should be shown as a p ⁺ buried region continuously connected to the left and right. In FIG. 24A, a p ⁺ region is schematically shown in a part for the sake of clarity.

The potential for the internal electrons is as shown in FIG. 24C, and the buried p ⁺ region 22 is used.
The potential distribution in the vertical cross section that does not include 0 is no different from that shown in FIG. 12, but the potential distribution in the vertical cross section that includes the embedded p ⁺ region 220 has the potential distribution as indicated by the dotted line 223. ing. However, in this figure, the potential distribution is shown when the buried p ⁺ region 220 is biased to a slightly positive potential. In this state, the embedded p
^{When the +} region 220 is further biased in the positive potential direction, the n ⁻ region existing between them is completely punched through,
Holes flow into the base region 6 of the sensor cell from the p ⁺ region, and the potential of the base region 6 moves in the positive potential direction due to the holes.

Punch through the n ^- region and p ⁺
To pour holes from region 220 into the p base region,
When the thickness d of the n ⁻ region, the impurity density N, and the voltage applied to the p ⁺ region 220 are V _P ⁺

[0143]

[Equation 32]

Design as follows. V _bi is the diffusion potential of the p ⁺ n ⁻ junction. Therefore, in the state of FIG. 12, by applying a positive voltage to the buried p ⁺ region 220 through the wiring 222 and injecting holes into the p base region, the base potential 210 is set to zero potential or slightly as described above. By bringing the positive potential, it is possible to solve the disadvantageous phenomenon in the transient refresh mode. At this time, the voltage applied to the buried p ⁺ region 220 is slightly smaller than the voltage applied to the sensor cell collector 1, that is, the buried p ⁺ region 220 and the n region 1 of the collector are not forward biased. In a state
It is possible to sufficiently pass the holes into the base region 6.

Impurities forming the p ⁺ region (usually boron)
Generally has a large diffusion constant, and problems of autodoping and diffusion occur when the high resistance n ⁻ region 5 is formed by using the epitaxial technique. However, due to the low temperature of the epitaxial technique, the autodoping from the buried p ⁺ region is caused. And a device is made to suppress diffusion as much as possible.

The above-mentioned one structural example is different only in that the buried p ⁺ region is added to the basic photosensor cell by diffusion or ion implantation as described above, and the method of forming the latter part may be exactly the same. FIG. 25 shows a cross-sectional view of an optical sensor cell for explaining another configuration example. Figure 2
In the cross-sectional view shown in FIG. 5, the embedded p ⁺ shown in FIG.
Instead of the region 220, when the base region 6 is formed, the P region 224 is simultaneously formed on the front surface side. This P
A pnp transistor having the region 224 as an emitter, the low impurity n ⁻ region 5 as a base, and the base 6 of the photosensor cell as a collector is formed. This is because the pnp transistor having the vertical structure is formed as shown in FIG. 24, whereas the pnp transistor having the horizontal structure is formed. Therefore, in the configuration example of FIG. 25, it is the wiring 2 on the front surface side that supplies the voltage to the P region 224.
25.

The equivalent circuit of the configuration example shown in FIG. 25 is
Although the pnp transistor has a vertical structure and a horizontal structure, it is exactly the same as the equivalent circuit shown in FIG. 24B, and its operation is also exactly the same as that already described. In the cross-sectional view shown in FIG. 25, p ⁺ region 2
24, the wiring 225 thereof is shown in the same cross section as the MOS capacitor electrode 9, the emitter region 7 and the wiring 8 for the sake of convenience of explanation, but they can be arranged in other parts of the same photosensor cell. This is determined by design factors such as the shape of the window on which light is incident and the wiring.

As described above, in the photoelectric conversion device using the optical sensor cell according to the above-mentioned configuration, the amplifier at the final stage may be extremely simple, so that only one amplifier at the final stage is provided. Instead of the type shown in FIG. 15, it is possible to preferably use a configuration in which a plurality of amplification amplifiers are installed and one screen is divided and read out as in the present invention.

FIG. 1 shows an example of a division read method by the signal processing device of the present invention. The embodiment shown in FIG. 1 is an example in which the horizontal direction is divided into three and three final stage amplifiers are installed.
The basic operation is almost the same as that described using the configuration example of FIG. 15 and the timing diagrams of FIGS. 11 and 12, but in the embodiment of FIG. 1, three equivalent horizontal shift registers 100 and 101 are provided. , 102, and when the start pulse is applied to the terminal 103 for applying these start pulses, the first column, the (n + 1) th column, and the (2n + 1) th column (n is an integer, and in this embodiment, the horizontal The output of each sensor cell connected to the direction picture element number is 3n). At the next time, the second row, (n + 2)
The second and (2n + 2) th columns will be read. According to this embodiment, when the time for reading one horizontal line is fixed, the scanning frequency in the horizontal direction is 1/3 as compared with the system with one final stage amplifier.
, The horizontal shift ranger becomes simpler,
In addition, a high-speed analog-to-digital converter is not necessary for applications such as analog-to-digital conversion of output signals from the photoelectric conversion device and signal processing, which is a great advantage of the divided read method.

In the embodiment shown in FIG. 1, three equivalent horizontal shift registers are provided, but a similar function can be provided by only one horizontal shift register. An example of this case is shown in FIG. The embodiment of FIG. 2 is a horizontal switching M of the embodiment shown in FIG.
Only the intermediate portion of the OS transistor and the final stage amplifier is shown, and the other portions are omitted since they are the same as in the embodiment of FIG.

In this embodiment, the output from one horizontal shift register 104 is set to the 1st column, the (n + 1) th column, (2n
+1) It is connected to the gates of the switching MOS transistors in the column, and these lines are read simultaneously. At the next time point, the second row, the (n + 2) th row, the (2n +
2) The column number is read.

According to this embodiment, each switching MO
Although the number of wirings to the gate of the S transistor is increased, only one horizontal shift register can operate. In the examples of FIGS. 1 and 2, three output amplifiers are provided, but it goes without saying that the number may be increased according to the purpose.

In both the embodiments of FIGS. 1 and 2, the start pulse and clock pulse of the horizontal shift register and the vertical shift register are omitted, but these are provided in the same chip as other refresh pulses. Or a clock pulse generator provided on another chip.

In this divided read method, when horizontal line batch or full screen batch refresh is performed, the nth column and (n
The accumulation time is slightly different between the photosensor cells in the (+1) th column, which may cause a slight discontinuity in the dark current component and the signal component, which may be noticeable on the image. Is small and practically no problem. Also, even if this exceeds the permissible limit, using an external circuit to correct it will generate a sine wave, subtract it from the dark current component, and multiply and divide this by the signal component. This is easily possible by using the conventional correction technique performed by

When a color image is picked up by using such a photoelectric conversion device, a stripe filter, a mosaic filter, or the like is integrated on the photoelectric conversion device, or a separately prepared color filter is attached. A color signal can be obtained by combining them.

As an example, when the R, G, and B stripe filters are used, in the photoelectric conversion device using the photosensor cell according to the above configuration, the R signal, the G signal, and the B signal are respectively output from separate final stage amplifiers. It is possible to obtain.
An example of this structure is shown in FIG. Similar to FIG. 2, this FIG. 17 also shows only around the horizontal shift register. Others are the same as in FIGS. 1 and 15, except that the first column is an R color filter, the second column is a G color filter, the third column is a B color filter, and the fourth column is an R color filter. The color filter is attached to. FIG. 17
, Each vertical line of the 1st, 4th, 7th, ... Is connected to the output line 110, which takes out the R signal. Each of the vertical lines in the second, fifth, eighth,... Columns is connected to an output line 111, which takes out a G signal.
Similarly, the vertical lines of the third column, the sixth column, the ninth column, ... Take out the B signal connected to the output line 112.
The output lines 110, 111 and 112 are respectively connected to on-chip refresh MOS transistors and final stage amplifiers, for example, emitter follower type bipolar transistors, and each color signal is output separately.

FIG. 18 is a diagram for explaining the basic structure and operation of another example of the photosensor cell that constitutes the photoelectric conversion device .
Shown in Further, FIG. 19 shows an equivalent circuit thereof and an overall circuit configuration diagram. The photosensor cell shown in FIG. 18 is a photosensor cell capable of simultaneously performing a read operation and a line refresh by the same horizontal scan pulse. In FIG. 18, the point different from the configuration already shown in FIG. 4 is that in the case of FIG. 4, only one MOS capacitor electrode 9 is connected to the horizontal line wiring 10 on the side of vertically adjacent photosensor cells. Also, when the MOS capacitor electrode 120 is connected, when viewed from one photosensor cell,
It is a double capacitor type, and the emitters 7 and 7'of the photosensor cells vertically adjacent to each other in the figure
Is a wiring 8 and a wiring 121 which are two-layer wiring,
(Although one vertical line looks like one in FIG. 18, two lines are arranged through an insulating layer.)
That is, the emitter 7 is connected to the wiring 8 through the contact hole 19 and the emitter 7'is connected to the wiring 121 through the contact hole 19 '.

This becomes more apparent when the equivalent circuit of FIG. 19 is viewed. That is, the MOS capacitor 150 connected to the base of the photosensor cell 152 is connected to the horizontal line 31, and the MOS capacitor 151 is connected to the horizontal line 31 '. Further, the MOS capacitor 150 'of the photosensor cell 152' adjacent to the bottom of the photosensor cell 152 in the drawing is connected to the common horizontal line 31 '.

The emitters of the photosensor cells 152 are alternately connected to the vertical lines 38, the emitters of the photosensor cells 152 'are connected to the vertical lines 138, the emitters of the photosensor cells 152 "are connected to the vertical lines 38, and so on. In the equivalent circuit, the vertical line 3 is different from the image pickup device of FIG. 15 except for the basic optical sensor cell section described above.
8, a switching MOS transistor 148 for refreshing the vertical line 138, a switching MOS transistor 148 for refreshing the vertical line 138, a switching MOS transistor 40 for selecting the vertical line 38, and a switching MOS transistor for selecting the vertical line 138. 140 is added and one output amplifier system is added. This output system has a switching M for refreshing each line.
The configuration is such that the OS transistors 48 and 148 are connected, and the switching M for horizontal scanning is further used.
A configuration using only one output amplifier as shown in FIG. 20 using OS transistors is also possible. FIG. 20 shows only the vertical line selection and output amplifier system of FIG.

According to the photosensor cell of FIG. 18 and the configuration example shown in FIG. 19, the following operation is possible. That is, when the reading operation of each photosensor cell connected to the horizontal line 31 is completed and the horizontal blanking period in the television operation is completed, the output pulse from the vertical shift register 32 is output to the horizontal line 31 '. Through 151, the optical sensor cell 15 whose reading has been completed
Refresh 2. At this time, switching MOS
Transistor 48 is conductive and vertical line 38 is grounded.

Further, the MO connected to the horizontal line 31 '
The output of the photosensor cell 152 'is read out on the vertical line 138 through the S capacitor 150'. At this time, as a matter of course, the switching MOS transistor 148 is turned off and the vertical line 138 is in a floating state. In this way, with one vertical scan pulse, it is possible to simultaneously refresh the photosensor cells that have already been read and read the photosensor cells of the next line with the same pulse. At this time, as already described, the voltage for refreshing and the voltage for reading are different because a bias voltage is applied during reading because of the necessity of high-speed reading.
As shown in FIG. 5, it is achieved by changing the areas of the MOS capacitor electrode 9 and the MOS capacitor electrode 120 so that different voltages are applied to the bases of the respective photosensor cells even if the same voltage is applied to each electrode. ing.

That is, the area of the refresh MOS capacitor is smaller than the area of the read MOS capacitor. As shown in FIG. 4B, when the sensor cells are not refreshed all at once but refreshed line by line as in this example, the collector is made of an n type or an n substrate. However, it may be desirable to have separate collectors for each horizontal line. When the collector is the substrate, the collectors of all the photosensor cells are in the common region, so that a constant bias voltage is applied to the collector in the accumulation and light reception read states. Of course, as described above, the floating base refresh can be performed between the emitters even when the bias voltage is applied to the collector. However, in this case, at the same time as the refreshing of the base region is performed, a wasteful current flows between the emitter and collector of the cell to which the refresh pulse is applied, resulting in a large power consumption. In order to overcome these disadvantages, the collectors of all the sensor cells are not used as a common area, and the collectors of the sensor cells arranged in each horizontal line are common, but the collectors of each horizontal line are separated from each other. That is, in connection with the structure of FIG. 4, the substrate is of p-type, and n ⁺ collectors separated from each other by horizontal lines in the p-type substrate.
The structure has an embedded region. N of adjacent horizontal lines
⁺ Embedded regions may be separated by a structure in which ap region is interposed. Insulator isolation is better at reducing collector capacitors buried along horizontal lines.
In FIG. 4, since the collector is composed of the substrate, the isolation regions surrounding the sensor cell are all provided to almost the same depth. On the other hand, in order to separate the collectors for each horizontal line from each other, the separation region in the horizontal line direction is set to be deeper than the separation region in the vertical line direction by a necessary value.

If the collector is separated for each horizontal line, if the collector voltage of that horizontal line is grounded at the end of the read operation and the refresh operation, the above-described emitter-collector current does not flow. , Does not increase power consumption. When the refresh operation ends and the charge accumulation operation by the optical signal is started, a predetermined bias voltage is applied to the collector region again.

According to the equivalent circuit of FIG. 19, the output is alternately output to the output terminals 47 and 147 for each horizontal line. This is, as I already explained,
With the configuration shown in FIG. 20, it is possible to take out the output from one amplifier.

According to the photoelectric conversion device described above, it is possible to perform line refreshing with a relatively simple structure, and it can be applied to the application fields such as ordinary television cameras. As another configuration example, a type in which a plurality of outputs are taken out from one photosensor cell by a configuration in which a plurality of emitters are provided in the photosensor cell or a configuration in which a plurality of contacts are provided in one emitter can be considered.

This is because each optical sensor cell of the photoelectric conversion device described above has an amplifying function, so even if a plurality of wiring capacitors are connected to each optical sensor cell in order to take out a plurality of outputs from one optical sensor cell, This is because the accumulated voltage Vp generated inside the sensor cell can be read out to each output without any attenuation.

As described above, with the structure in which a plurality of outputs can be taken out from each photosensor cell, many advantages can be obtained in signal processing or noise countermeasures for a photoelectric conversion device in which a large number of photosensor cells are arranged. It is possible to add. Next, an example of a manufacturing method of the above-described photoelectric conversion device will be described. 21 and 22 show selective epitaxial growth (N. Endo et al, “Novel device isolation technology”).
ogy with selected epitaxial growth "Tech. Dig. of
1982 IEDM, pp. 241-244), an example of the manufacturing method is shown.

An n ⁺ region 11 for contact is provided by diffusion of As or P on the back surface side of the n-type Si substrate 1 having an impurity concentration of about 1 to 10 × 10 ¹⁶ cm ^-3 . In order to prevent auto doping from the n ⁺ region, an oxide film and a nitride film are usually provided on the back surface although not shown in the figure.

The substrate 1 has a uniform impurity concentration and oxygen concentration. That is, a crystal wafer having a carrier line time that is sufficiently long and uniform is used. As such a material, for example, a crystal by the MCZ method is suitable. An oxide film of about 1 μm is formed on the surface of the substrate 1 by wet oxidation. That is, oxidation is performed in an H ₂ O atmosphere or an (H ₂ + O ₂ ) atmosphere. To obtain a good oxide film without causing stacking faults and the like, 900 ° C.
High pressure oxidation at moderate temperatures is suitable.

A SiO ₂ film having a thickness of, for example, about _{2 to 4} μm is deposited thereon by CVD. (N ₂ + SiH ₄ + O
₂ ) Deposit a SiO ₂ film of desired thickness at a temperature of about 300 to 500 ° C. in a gas system. The molar ratio of O ₂ / SiH ₄ is set to about 4 to 40, depending on the temperature. By the photolithography process, the oxide film in the part which becomes the isolation region between the cells is left and the oxide films in the other regions are (CF ₄ + H ₂ ), C ₂
Removal by reactive ion etching using a gas such as F ₄ , CH ₂ F ₂ (step (a) in FIG. 21), for example,
10 μm when one pixel is provided for 10 × 10 μm ^2.
The SiO ₂ film is left in the form of pitch mesh. The width of the SiO ₂ film is selected to be, for example, about 2 μm. The damage layer and the contamination layer on the surface due to the reactive ion etching are
After removing by r / Cl ₂ gas-based plasma etching or wet etching, vapor deposition in ultra-high vacuum, or sputtering in which the atmosphere is sufficiently cleaned by a load lock method, or a CO ₂ laser beam is applied to SiH ₄ gas. Amorphous silicon 301 is deposited by irradiation with low pressure photo CVD (step (b) in FIG. 21), CBrF
_{3, CCl 2 F 2, Cl} SiO 2 by anisotropic etching using reactive ion etching using a ₂ or the like of the gas
Amorphous silicon other than those deposited on the side surface of the layer is removed (step (c) in FIG. 21). As before, the damage layer and the contaminated layer are sufficiently removed, and then the surface of the silicon substrate is sufficiently cleaned. Selective growth of a silicon layer is carried out by a (H ₂ + SiH ₂ , Cl ₂ + HCl) gas system. Number 10 Tor
The growth is performed under a reduced pressure of r, and the substrate temperature is 900 to 10
The molar ratio of 00 ° C. and HCl is set to a value higher than a certain level. If the amount of HCl is too small, selective growth does not occur.
Although a silicon crystal layer grows on the silicon substrate,
Since silicon on the O ₂ layer is etched by HCl, silicon is not deposited on the SiO ₂ layer ((d) of FIG. 21). The thickness of the n ⁻ layer 5 is, for example, 3 to 5 μm.
m. The impurity concentration is preferably 10 ¹² to 10 ¹⁶
Set it to about cm ^-3 . Of course, this range may be deviated, but in a state where the impurity is completely depleted by the diffusion potential of the pn ^- junction or an operating voltage is applied to the collector, at least the impurity concentration and the n ^- region are completely depleted. It is desirable to choose the thickness.

Since HCl gas which is usually available contains a large amount of water, an oxide film is always formed on the surface of a silicon substrate, and thus high quality epitaxial growth cannot be expected. HCl containing a large amount of water reacts with the material of the cylinder while in the cylinder and contains a large amount of heavy metal mainly composed of iron, so that an epitaxial layer easily contaminated with heavy metal tends to be formed. Since it is more desirable for the epitaxial layer used for the optical sensor cell to have a smaller dark current component, it is necessary to suppress contamination by heavy metals to the utmost limit. Of course, an ultra-high purity material is used for SiH ₂ Cl ₂ , but HCl has a particularly low moisture content, preferably at least a moisture content of 0.5 ppm.
Use the following: Of course, the lower the water content, the better. In order to further improve the quality of the epitaxially grown layer, the substrate is first subjected to high-temperature treatment at about 1150 to 1250 ° C. to remove oxygen from the vicinity of the surface, and then subjected to a long-term heat treatment at about 800 ° C. to generate many micro defects inside the substrate. It is also very effective to use a substrate having a denuded zone and capable of performing intrinsic gettering. Since epitaxial growth is performed in a state where the SiO ₂ layer 4 as an isolation region exists,
A lower growth temperature is desirable to reduce the uptake of oxygen from SiO ₂ . In the commonly used high frequency heating method, there is much contamination from the carbon susceptor, and it is difficult to further lower the temperature. The wafer direct heating method by lamp heating without bringing in a carbon susceptor into the reaction chamber can make the growth atmosphere the cleanest and can grow a high-quality epitaxial layer at a low temperature.

Ultrahigh-purity molten sapphire having a lower vapor pressure is suitable for the wafer support in the reaction chamber. The raw material gas can be preheated easily, and even if a large flow of gas is flowing, it is easy to make the wafer in-plane temperature uniform, that is, the wafer direct heating method by lamp heating that generates almost no thermal stress produces high-quality epitaxial layers. Suitable to get. UV irradiation on the wafer surface during growth
Further improve the quality of the epitaxial layer.

Amorphous silicon is deposited on the side wall of the SiO ₂ layer which becomes the isolation region 4 (step (c) in FIG. 21). Since amorphous silicon is easily single-crystallized by solid phase growth, the crystal near the interface with the SiO ₂ separation region 4 is very excellent. After forming the high resistance n ⁻ layer 5 by selective epitaxial growth (step (d) in FIG. 21), the P region 6 having a surface concentration of about 1 to 20 × 10 ¹⁶ cm ⁻³ is diffused from the doped oxide, or A low-dose ion implantation layer is used as a source to form a predetermined depth by diffusion. The depth of the p region 6 is, for example, 0.6 to
It is about 1 μm.

The thickness and impurity concentration of p region 6 are determined by the following ideas. To increase the sensitivity, the p region 6
It is desirable to reduce the impurity concentration of and reduce Cbe. Cbe is approximately given as follows.

[0175]

[Expression 33]

However, Vbi is the diffusion potential between the emitter and the base,

[0177]

(Equation 34)

Given by Here, ε is the dielectric constant of the silicon crystal, N _D is the impurity concentration of the emitter, N _A is the impurity density of the portion adjacent to the emitter of the base, and n _i is the true carrier concentration. As Cbe is reduced to reduce the N _A, the sensitivity is increased, but since the the N _A is made too small base region will completely become depleted in punching through state at operating conditions, is too low can Absent. It is set to such an extent that the base region is not completely depleted and does not enter a punch-through state.

After that, (H ₂ + O
₂ ) Several tens to several hundreds of square meters by gas steam oxidation
A thermal oxide film 3 having a thickness of about 800 is formed at a temperature of about 800 to 900.degree. Thereon, the (SiH ₄ + NH ₃₎ based nitride film by CVD gas (Si ₃ N ₄₎ 302 500~15
It is formed with a thickness of about 00Å. Formation temperature is 700-90
It is about 0 ° C. The NH ₃ gas, also commonly available alongside the HCl gas, contains a large amount of moisture. When NH ₃ gas having a high moisture content is used as a raw material, a nitride film having a high oxygen concentration is obtained, and reproducibility is poor.
The result is that a selective ratio cannot be obtained by selective etching with the O ₂ film. The NH ₃ gas also has a water content of at least 0.1.
It should be 5 ppm or less. It goes without saying that the smaller the water content, the better. A PSG film 300 is further deposited on the nitride film 302 by CVD. The gas system is, for example, (N ₂ + SiH ₄ + O ₂ + PH ₃ ),
A PSG film having a thickness of about 2000 to 3000 Å is deposited by CVD at a temperature of about 300 to 450 ° C. (step (e) in FIG. 21). An As-doped polysilicon film 304 is deposited on the n ⁺ region 7 and the refresh and read pulse application electrodes by a photolithography process including two mask alignment processes. In this case, a p-doped polysilicon film may be used. For example, a PSG film and Si are formed on the emitter by two photolithography processes.
_The 3N ₄ film and the SiO ₂ film are all removed, and the underlying Si
Only the PSG film and the Si ₃ N ₄ film are etched, leaving the O ₂ film. Then, the As-doped polysilicon is replaced with (N ₂
+ SiH ₄ + AsH ₃ ) or (H ₂ + SiH ₄ + A
sH ₃ ) gas is deposited by the CVD method. Deposition temperature is 5
The film thickness is about 50 ° C to 700 ° C and the film thickness is 1000 to 2000Å. As a matter of course, non-doped polysilicon may be deposited by the CVD method, and then As or P may be diffused.
The polysilicon film except for the emitter and the refresh and read pulse application electrodes is masked, and is removed by etching after the photolithography process. Further, when the PSG film is etched, P is caused by lift-off.
The polysilicon deposited on the SG film is removed in a self-aligned manner (step (f) in FIG. 21). The etching of the polysilicon film is performed using C ₂ Cl ₂ F ₄ , (CBrF ₃ +
Cl ₂ ), etc. is used for etching, and the Si ₃ N ₄ film is C
Etching is performed with a gas such as H ₂ F ₂ .

Next, after depositing the PSG film 305 by the gas-based CVD method as described above, contact holes are formed on the polysilicon film for the refresh pulse and read pulse electrodes by a mask aligning process and an etching process. Open. In such a state, Al, Al-Si, Al-
A metal such as Cu-Si is deposited by vacuum evaporation or sputtering, or (CH ₃ ) ₃ Al or AlCl ₃
Al is deposited by a plasma CVD method using as a raw material gas, or a light irradiation CVD method in which the Al—C bond or the Al—Cl bond of the above raw material gas is cut by direct light irradiation. When the above-described CVD method is performed using (CH ₃ ) ₃ Al or AlCl ₃ as a raw material gas, hydrogen is allowed to flow in a large excess. In order to deposit Al in a thin and steep contact hole, a CVD method in which the substrate temperature is raised to a film thickness of 300 to 400 ° C. in a clean atmosphere free of moisture and oxygen is excellent. After the patterning of the metal wiring 10 shown in FIG. 4 is completed, the interlayer insulating film 306 is deposited by the CVD method. 306 is the above-mentioned PSG film, the CVD method SiO ₂ film, or the Si ₃ N ₄ film formed by the (SiH ₄ + NH ₃ ) gas-based plasma CVD method when it is necessary to consider the water resistance. Is. In order to keep the hydrogen content in the Si ₃ N ₄ film low, a plasma CVD method using a (SiH ₄ + N ₂ ) gas system is used.

In order to increase the electrical breakdown voltage of the Si ₃ N ₄ film formed by causing the phenomenon of damage by the plasma CVD method and reduce the leak current, Si ₃ by the photo CVD method is used.
N ₄ film is excellent. There are two types of light CVD methods. (SiH ₄ + NH ₃ + Hg) gas system for externally irradiating ultraviolet rays of 2537 ° from a mercury lamp;
This is a method of irradiating an iH ₄ + NH) ₃ gas system with ultraviolet rays of 1849 ° from a mercury lamp. In both cases, the substrate temperature is 150-
It is about 350 ° C.

By the mask aligning process and the etching process, the insulating films 305 and 3 are formed on the polysilicon on the emitter 7.
After the contact hole penetrating 06 is opened by reactive ion etching, Al, Al-Si,
A metal such as Al-Cu-Si is deposited. In this case,
Since the aspect ratio of the contact hole is large, CVD
The deposition by the method is superior. After patterning the metal wiring 8 in FIG. 15, a Si ₃ N ₄ film or a PSG film 2 as a final passivation film is formed by CVD.
It is deposited by the method (FIG. 22).

Also in this case, the film formed by the photo CVD method is excellent. Reference numeral 12 denotes a metal electrode made of Al, Al-Si or the like on the back surface. The above-described method for manufacturing the photoelectric conversion device has a great variety of steps, and FIGS. 21 and 22 describe only one example.

An important point of such a photoelectric conversion device is how to reduce the leak current between the p region 6 and the n ⁻ region 5 and between the p region 6 and the n ⁺ region 7. It goes without saying that the quality of the n ⁻ region 5 is improved to reduce the dark current, but the interface between the isolation region 4 made of an oxide film or the like and the n ⁻ region 5 is a problem. In FIGS. 21 and 22, for that purpose, a method of depositing amorphous Si on the side wall of the isolation region 4 in advance and performing epitaxial growth has been described. In this case, the substrate Si
Amorphous Si is single-crystallized by solid phase growth from. Epitaxial growth is 850 ° C to 1000
It is carried out at a relatively high temperature of about ℃. Therefore, before amorphous Si is monocrystallized by solid phase growth from the substrate Si, microcrystals often start to grow in the amorphous Si, which causes deterioration of crystallinity. The lower the temperature, the faster the solid-phase growth rate becomes than the rate at which microcrystals start to grow in amorphous Si. Therefore, before the selective epitaxial growth, 55
When amorphous Si is single-crystallized by a low temperature treatment of about 0 ° C. to 700 ° C., the characteristics of the interface are improved. This time,
If there is a layer such as an oxide film between the substrate Si and the amorphous Si, the initiation of solid phase growth is delayed, so an ultra-high cleaning process that does not include such a layer at the boundary between the two is required.

For solid phase growth of amorphous Si, in addition to the above-described furnace growth, a rapid annealing technique of heating the substrate at a certain temperature and heating with a fish lamp or an infrared lamp for, for example, several seconds to several tens seconds is also applicable. It is valid. When using these technologies, Si
The Si deposited on the side wall of the O ₂ layer may be polycrystalline. However, it is necessary to deposit by a very clean process, and to make polycrystalline Si containing no oxygen, carbon, or the like at the crystal grain boundaries of the polycrystalline body.

After the Si on the side surface of SiO ₂ is single-crystallized, the Si is selectively grown. If the leakage current at the interface between the SiO ₂ isolation region 4 and the high resistance n ⁻ region 5 is a problem, the n-type impurity concentration is increased only in the portion of the high resistance n ⁻ region 5 adjacent to the SiO ₂ isolation region 4. In this case, the problem of the leakage current is avoided. For example, 0.3 of n ⁻ region 5 in contact with isolated SiO ₂ region 4
Only a region having a thickness of about 1 μm, for example, 1 to 10 × 1
The n-type impurity concentration is increased to about 0 ¹⁶ cm ^-3 . This structure can be formed relatively easily. After forming a thermal oxide film of about 1 μm on the substrate 1, a thermal oxide film is deposited thereon by a CVD method. Only first required thickness of the SiO ₂ film, keep the SiO ₂ film containing P of a predetermined amount. Further, the separation region 4 is formed by depositing SiO ₂ thereon by CVD.
Make. From the phosphorus-containing SiO ₂ film present in a sandwich state in the isolation region 4 in the subsequent high-temperature process,
Phosphorus diffuses into the high-resistance n ⁻ region 5 to form a favorable impurity distribution in which the interface has the highest impurity concentration.

That is, the structure as shown in FIG. 23 is formed. The isolation region 4 has a three-layer structure, 308 is a thermal oxide film SiO ₂ , and 309 is C containing phosphorus.
A VD method SiO ₂ film 301 is a CVD method SiO ₂ film. Adjacent to the isolation region 4, between the n ⁻ region 5,
A region 307 is formed by diffusion from the SiO ₂ film 309 containing phosphorus. 307 is formed all around the cell. With this structure, the base-collector capacitance Cbc
Is large, but the base-collector leakage current is drastically reduced.

In FIG. 21 and FIG. 22, an example in which the isolation insulating region 4 is formed in advance and selective epitaxial growth is performed has been described. However, a high resistance n ⁻ required on the substrate is described.
U-group isolation technology (A.Hayasaka et al, “U-groove isolation, in which a layer to be an isolation region is cut in a mesh shape by reactive ion etching after the layer is epitaxially grown to form the isolation region.
technique for highspeed bipolar VLSI'S ″, Tech.
Dig. Of IEDM. P.62, 1982, see also).

The photoelectric conversion device described above forms a bipolar transistor in which a base region, most of which is adjacent to the surface of a semiconductor wafer, is in a floating state in a region surrounded by an isolation region made of an insulator. An apparatus for photoelectrically converting optical information by controlling the potential of a floating base region by an electrode provided in a part of the base region through a thin insulating layer. An emitter region including a high impurity concentration region is provided in a part of the base region, and the emitter is connected to a MOS transistor operated by a horizontal scan pulse. The above-described electrode provided in a part of the floating base region via a thin insulating layer is connected to a horizontal line. The collector provided inside the wafer may be composed of a substrate, or may be composed of a high-concentration impurity-embedded region separated for each horizontal line on a high resistance substrate of opposite conductivity type depending on the purpose. . An electrode provided through an insulating layer,
The applied pulse voltage when reading a signal is substantially higher than the pulse voltage when refreshing the floating base region. Indeed, the two may be used a pulse train to wait for voltage, as described in the double capacitor structure, to increase the capacity C _ox of the read MOS capacitor electrode compared to the capacitance C _ox of the refreshing MOS capacitor electrode You may keep it. By applying a refresh pulse, the photo-excited carriers are accumulated in the floating base region that is in the reverse bias state, and the signal based on the optical signal is stored.
At the time of reading the signal, a characteristic is that the reading pulse voltage is applied so that the base and the emitter are deeply biased in the forward direction so that the signal can be read at a high speed. It is needless to say that the photoelectric conversion device of the present invention may be realized by any structure as long as it has such characteristics, and is not limited to the structure described in the above configuration example.

For example, of course, the same applies to the structure described in the above configuration example and the structure in which the conductivity type is completely inverted. However, at this time, it is necessary to completely reverse the polarity of the applied voltage. In a structure where the conductivity type is completely inverted, the region becomes n-type. That is, the impurities constituting the base are As and P. When the surface of the region containing As or P is oxidized, As or P piles up on the Si side of the Si / SiO ₂ interface. That is, a strong drift electric field from the surface to the inside is generated inside the base, the photoexcited holes immediately escape from the base to the collector side, and electrons are efficiently accumulated in the base.

When the base is p-type, boron is a commonly used impurity. When the surface of the p-region containing boron is thermally oxidized, boron is taken into the oxide film, so that Si /
The boron concentration in Si near the SiO ₂ interface is slightly lower than the boron concentration inside. This depth is usually several 100 Å, although it depends on the oxide film thickness. Near this interface,
A reverse drift electric field occurs for the electrons, and the electrons photoexcited in this region tend to collect on the surface. If this is left as it is, the region in which this reverse drift electric field is generated becomes a dead region, but since the n ⁺ region exists in a part along the surface in the photoelectric conversion device of this configuration , p
Electrons collected at the Si / SiO ₂ interface in the region are
It flows before being recombined into this n ⁺ region. For this reason, for example, even if there is a region where boron is reduced near the Si / SiO ₂ interface and a reverse drift electric field is generated, the region hardly becomes a dead region. Rather, when such a region exists at the Si / SiO ₂ interface, the accumulated holes are separated from the Si / SiO ₂ interface so as to be present inside. The hole accumulation effect in the base is improved, which is highly desirable.

In addition to the solid-state image pickup device described above, the photoelectric conversion device according to the present configuration has, for example, an image input device such as an image input device, a facsimile, a workstation, a digital copying machine, a word processor, an OCR, a bar code reader. The present invention can also be applied to a photoelectric conversion subject detection device for autofocus such as a device, a camera, a video camera, and an 8 mm camera.

The photoelectric conversion device described above stores carriers excited by light in the base region, which is the control electrode region in the floating state. That is, Ba
It is a device that should be called a seStore Image Sensor, and is abbreviated as BASIS.

In the photoelectric conversion device according to this structure , one transistor can form one pixel, and therefore, it is extremely easy to increase the density, and at the same time, due to its structure, there is little blooming and smear and high sensitivity. It has a wide range, and since it has an internal amplifying function, it generates a large signal voltage regardless of the wiring capacitance, so that it has a feature of low recording and easy peripheral circuits. For example, as a future high quality solid-state imaging device, its industrial value is extremely high.

[0195]

According to the present invention, it is possible to perform signal processing even at low frequencies at substantially the same speed as processing at high frequencies.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a photoelectric conversion device showing an embodiment of a signal processing device of the present invention.

FIG. 2 is a circuit configuration diagram of a photoelectric conversion device showing another embodiment example of the signal processing device of the present invention.

FIG. 3 is an equivalent circuit diagram during a refresh operation of the optical sensor cell .

4A is a plan view of an optical sensor cell , FIG. 4B is a sectional view, and FIG. 4C is an equivalent circuit diagram.

FIG. 5 is a graph showing the relationship between the read time and the read voltage of the optical sensor cell .

FIG. 6 is a graph showing the relationship between the accumulated voltage of the optical sensor cell and the read time.

FIG. 7 is a graph showing the relationship between the bias voltage of the optical sensor cell and the read time.

FIG. 8 is a graph showing the relationship between the refresh time of the optical sensor cell and the base potential.

FIG. 9 is a graph showing a relationship between a refresh time of an optical sensor cell and a base potential.

FIG. 10 is a graph showing a relationship between a refresh time of an optical sensor cell and a base potential.

11 is a pulse timing chart of the photoelectric conversion device of FIG.

12 is a graph showing a potential distribution during each operation of the photoelectric conversion device of FIG.

13 is an equivalent circuit diagram related to output signals of the photoelectric conversion device of FIG.

14 is a graph showing the output voltage from the moment when the photoelectric conversion device of FIG. 15 becomes conductive, with respect to time.

FIG. 15 is a circuit diagram of a photoelectric conversion device having one signal processing unit.

FIG. 16 is an equivalent circuit diagram during a read operation of the photosensor cell according to the present invention.

FIG. 17 is a circuit diagram illustrating another photoelectric conversion device.

FIG. 18 is a plan view for explaining the main structure of a modified example of the optical sensor cell .

19 is a circuit configuration diagram of a photoelectric conversion device configured by the optical sensor cell shown in FIG.

20 is a circuit configuration diagram of a photoelectric conversion device configured by the optical sensor cell shown in FIG.

FIG. 21 is a cross-sectional view showing an example of a method for manufacturing the photoelectric conversion device .

FIG. 22 is a cross-sectional view showing the example of the method for manufacturing the photoelectric conversion device .

FIG. 23 is a cross-sectional view showing the example of the method for manufacturing the photoelectric conversion device .

FIG. 24 shows an optical sensor cell , (a) is a sectional view,
(B) is an equivalent circuit diagram thereof, and (c) is a potential distribution diagram.

FIG. 25 is a sectional view showing the main structure of another modification of the optical sensor cell.

[Explanation of symbols]

1 Silicon substrate 2 PSG film 3 Insulating oxide film 4 Element isolation region 5 n ^- region (collector region) 6 p region (base region) 7, 7'n ⁺ region (emitter region) 8 wiring 9 electrode 10 wiring 11 n ⁺ region 12 electrodes 13 capacitors 14 bipolar transistors 15 and 17 junction capacitances 16 and 18 diodes 19 and 19 'contact parts 20 light 28 vertical lines 30 photosensor cells 31 horizontal lines 32 vertical shift registers 33 and 35 MOS transistors 36 and 37 terminals 38 vertical lines 39 Horizontal shift register 40 MOS transistor 41 output line 42 MOS transistor 43 terminal 44 transistor 45 load resistor 46 terminal 47 terminal 48 MOS transistor 49 terminal 61, 62, 63 section 64 collector potential 67 waveform 80, 81 Capacitance 82, 83 Resistance 84 Current source 100, 101, 102 Horizontal shift register 111, 112 Output line 138 Vertical line 140 MOS transistor 148 MOS transistor 150, 150 'MOS capacitor 152, 152' Photosensor cell 202, 203, 205 Base potential 220 Buried p ⁺ region 222, 225 wiring 251 p ⁺ region 252 n ⁺ region 253 wiring 300 amorphous silicon 302 nitride film 303 PSG film 304 polysilicon 305 PSG film 306 interlayer insulating film

Claims (5)

[Claims] 1. A plurality of optical sensor arrays each comprising a plurality of optical sensors provided on the same substrate, reading means for reading output signals from the optical sensor arrays, and transferring the read output signals. Transfer means, a shift register connected to the transfer means, and a plurality of signal processing means provided corresponding to the shift register,
In the signal processing device, wherein the plurality of signal processing means are respectively provided corresponding to the plurality of photosensor arrays, and the signals transferred from the respective photosensor arrays are processed in parallel by the signal processing means. The sensor comprises a bipolar transistor whose emitter is connected to the transfer means through an output line and whose base is connected to the drive line of the read means, wherein the read means applies a voltage to the base from the drive line to cause a floating state. A signal processing device which is a means for biasing the junction between the emitter and the base in the forward direction and reading the output signal as a voltage in a capacitive load of the output line. 2. The signal processing device according to claim 1, wherein
A signal processing device comprising a plurality of shift registers, each of which corresponds to each signal processing means, and which performs parallel processing for simultaneously scanning a plurality of photosensor arrays. 3. The signal processing device according to claim 1, wherein
The signal processing device is characterized in that one shift register is provided for each of the plurality of photosensor arrays and performs parallel processing for simultaneously scanning the plurality of photosensor arrays. 4. The signal processing device according to claim 1, wherein
The signal processing device, wherein the transfer means is a MOS transistor. 5. The signal processing device according to claim 1, wherein
The signal processing device, wherein the signal processing means includes an amplifier.