JPH0620120B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an element isolation region, and more particularly to a semiconductor device that effectively utilizes an element isolation region formed of a one conductivity type semiconductor.

INDUSTRIAL APPLICABILITY The present invention is applied to, for example, a photoelectric conversion device of a system in which carriers generated by photoexcitation are accumulated and a stored voltage generated by the accumulated carriers is read.

[Prior art]

FIG. 1 shows a photoelectric conversion device described in Japanese Patent Application No. 58-120755, and FIG. 1 (a) is a plan view of the photoelectric conversion device in which photosensor cells are two-dimensionally arranged. (b) is the sectional view on the AA 'line.

In FIGS. 1A and 1B, n ⁺ silicon substrate 101
Optical sensor cells are arranged on the top, and each optical sensor cell is
It is electrically insulated from an adjacent photosensor cell by an element isolation region 102 made of SiO ₂ , Si ₃ N ₄ or polysilicon.

Each photosensor cell has an n ⁻ region 103 having a low impurity concentration formed by an epitaxial technique or the like, a base of a bipolar transistor doped with a P type impurity (for example, boron), and a p-channel MOS transistor source. A region 104, ap region 105 serving as the drain of the P-channel MOS transistor, an n ⁺ region 106 serving as the emitter of the bipolar transistor, a gate electrode 108 of the P-channel MOS transistor sandwiching the oxide film 107, and the p region 104 through the oxide film 107. It is composed of a MOS capacitor electrode 109 for applying a pulse to the substrate, an emitter electrode 110, an electrode 111 for giving a predetermined potential to the p region 105, and the like.

The operation of the optical sensor cell having such a configuration will be described.

First, in the charge accumulation operation, the p region 104, which is the base, is biased to a negative voltage with respect to the n ⁺ region 106, and holes generated by light are accumulated. By accumulating holes,
The potential of the p region 104 changes in the positive direction, but the potential of the p region 104 of each photosensor cell varies depending on the intensity of light.

The read operation is performed in this state. That is, when the read pulse voltage V _R is applied to the MOS capacitor electrode 109, the p region 104 becomes a positive potential, information accumulated in the p region 104 is read out to the n ⁺ region 106 side an emitter. The read pulse voltage V _R is the ground potential,
Information is output from the n ⁺ region 106 to the outside through the emitter electrode 110.

Next, a refresh operation is performed by applying a negative pulse to the gate electrode 108 in a state where the potential of the p region 104 differs depending on the intensity of light. This negative pulse causes P
The channel MOS transistor becomes conductive and p region 1
The holes accumulated in 04 are removed and the p region 104 is fixed to a predetermined negative voltage. That is, this refresh operation causes the base p region 104
Has been completely initialized, and thereafter, the above-mentioned accumulation, reading, and refreshing operations are repeated.

In this way, by fixing the p region 104, which is the base, to a predetermined negative voltage during the refresh operation, it is possible to erase the optical information completely and at high speed regardless of the intensity of the light.

However, particularly in a photoelectric conversion device, it is desirable to effectively use the element surface in response to the demand for improved sensitivity and higher resolution.

In this respect, the conventional photoelectric conversion device is not sufficient. That is, as shown in FIG. 1, since the device isolation region 102 made of an insulating material is provided, the device becomes larger by this region and becomes conductive when refreshed.
It is necessary to specially provide a wiring for applying a predetermined negative voltage to one main electrode region of the channel MOS transistor.

On the other hand, in the case of an element isolation region made of a semiconductor, 2 to 4 μm
When the inside of the chip is drawn with the width of, the resistance value becomes 2500 to 5000 times the sheet resistance, and the problem of potential distribution occurs.

Further, if the element isolation region is to be formed deeply, the width will be widened to the same extent and the element surface will be wasted.
Further, JP-A-55-30855 discloses an image sensor in which a clear region for extracting the carriers accumulated in the gate of the static induction transistor surrounds a part of each pixel. However, in the image sensor, since the clearing operation is performed only by the MOS transistor integrated with the gate, noise may appear in the output signal due to ON / OFF of the MOS transistor.

[Object of the Invention]

The present invention has been made in view of the above conventional problems, and an object thereof is to provide a semiconductor device capable of realizing complete element isolation, having a low resistance value of an element isolation region, and effectively utilizing an element surface. To do.

[Outline of Invention]

In order to achieve the above object, a semiconductor device according to the present invention comprises a control electrode region made of a semiconductor of a first conductivity type and capable of accumulating carriers by receiving light energy, and a second conductivity type different from the first conductivity type. A semiconductor device having a phototransistor having first and second main electrode regions made of a semiconductor of a positive type, and an output circuit connected to the first main electrode region, the first main electrode region Is electrically coupled to a first reference voltage source to eliminate carriers accumulated in the control electrode region, and the control electrode region is electrically connected to the second reference voltage source. Second switch means for mechanically coupling, wherein the second switch means is to bring the control electrode region and an element isolation region made of a semiconductor of the first conductivity type into a conductive state at a suitable time, The element The isolation region forms a lower region made of a semiconductor of the first conductivity type formed on the surface of a semiconductor substrate of the second conductivity type, and then forms at least a part of the second main electrode region on the lower region. The lower region and the upper region obtained by forming an upper region made of a first conductivity type semiconductor in contact with the lower region from the surface side of the semiconductor layer It is characterized by including a region.

[Work]

According to the present invention, the potential of the control electrode area is made constant by the second switch means, and the main electrode area connected to the output circuit is also made constant potential by the first switch means. A current flows between itself and the main electrode region, and a refresh operation is performed. Therefore, it is possible to prevent the noise caused by the second switch means from appearing on the output circuit side. Moreover, high integration can be achieved by utilizing the element isolation region composed of a plurality of regions in the vertical direction as the second switch means.

That is, according to the technique disclosed in Japanese Patent Laid-Open No. 55-30855, the gate potential once becomes equal to the constant potential (V _B ) when the MOS transistor is turned on, but the gate potential is V _B when it is turned off due to the gate capacitance of the MOS transistor. It changes to + α. Since this variation α depends largely on the variation in the gate capacitance of each cell, the fixed pattern noise remains as the initial potential of the gate even though the reset operation is performed.

On the other hand, if the reset operation of fixing the main electrode region on the signal output circuit side to a predetermined potential is also used, a current flows in the junction between the control electrode region and the main electrode region, and the variation α is converged. Therefore, the potential (initial potential) of the control electrode region of each cell becomes constant.

Example of Invention

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a manufacturing process diagram of an embodiment of a method for manufacturing a semiconductor device according to the present invention. In this embodiment, the case of a photoelectric conversion device is taken up.

First, as shown in FIG. 2 (a), the impurity concentration is 1 × 1.
0 ^{15 to} 5 × 10 ¹⁷ cm ^-3 (desirably 1 × 10 ¹⁶ to 1 × 1
An n ⁺ layer 2 for ohmic contact having an impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ is formed by diffusion of P, As or Sb on the back surface of the n-type silicon substrate 1 of 0 ¹⁷ cm ⁻³ ). . Subsequently, the oxide film a1 is formed on the substrate 1 and the n ⁺ layer 2 to a thickness of 500 to 1500Å, respectively.

Next, a thickness of 0.8 to 1.5 μm is formed on the oxide film a1 on the substrate 1 side.
m resist a2 is applied and resist patterning is performed [FIG. 2 (b)].

Then, B ⁺ is ion-implanted using the resist a2 as a mask (the amount of ion implantation is 1 × 10 ¹³ to 1 × 10 ¹⁵ c).
m ^-2 ). After the ion implantation, the resist a2 is (H ₂ SO ₄ + H ₂ O ₂ )
And heat treatment is performed at 1000 ° C. to 1100 ° C. for 1 to 2 hours. By this heat treatment, boron implanted near the surface of the substrate 1 is pushed by thermal diffusion, and p
^{A +} region a3 is formed [FIG. 2 (c)].

Then, the oxide film a1 formed on the front and back is removed, and n ⁺
An oxide film 3 having a thickness of 3000 to 7000Å is formed on the layer 2 by the CVD method [FIG. 2 (d)].

The oxide film 3 is called a back coat and prevents generation of impurity vapor when the substrate 1 is heat-treated.

Next, the surface of the substrate 1 was heated at a temperature of 1000 ° C. and HCl2 / mi.
After etching n and H ₂ under the condition of 60 / min for about 1.5 minutes, the source gas SiH ₂ Cl ₂ (100%) was added at 1.2 / mi.
n, doping gas (H ₂ diluted PH ₃ , 20PPM) 100c.
c. The n ⁻ epitaxial layer 4 (hereinafter, referred to as the n ⁻ layer 4) is formed under a reduced pressure of 120 to 180 Torr at a growth temperature of 1000 ° C. The single crystal growth rate at this time is 0.
5 μm / min, thickness 2 to 10 μm, and impurity concentration 1 × 10 ¹² to 10 ¹⁶ cm ⁻³ , preferably 10 ¹² to 10
^{It is 14} cm ^-3 .

When the n ⁻ layer 4 is grown, the impurity (B) diffuses from the p ⁺ region a3 to the growing n ⁻ layer 4 and the p ⁺ region 6 is formed.
a is formed [FIG. 2 (e)].

In the low pressure epitaxial method, the pressure inside the reaction furnace is reduced to 80 to 200 Torr by a rotary pump or the like for epitaxial growth, and a high quality epitaxial layer with high resistance and less autodoping from the substrate can be grown. .

In order to improve the quality of the n ⁻ layer 4, the substrate is first subjected to a high temperature treatment of about 1150 to 1250 ° C. to remove oxygen from the vicinity of the surface and then subjected to a long-term heat treatment of about 800 ° C. for microdefects inside the substrate. A large number of
It is also extremely effective to use a substrate having a denuded zone and capable of intrinsic gettering.

Then, an oxide film 5 having a thickness of 4000 to 8000Å is formed on the n ⁻ layer 4 by pyrogenec oxidation (H ₂ + O ₂ ), wet oxidation (O ₂ + H ₂ O), or steam oxidation (N ₂ + H ₂ O). Form. Further, high-pressure oxidation at a temperature of 800 to 1000 ° C. is suitable for obtaining a good oxide film without stacking faults.

Then, in order to form the element isolation region, a part of the oxide film 5 is selectively removed by the photolithography method [FIG. 2 (f)].

Next, the boron nitride formed on the wafer (hereinafter
BN) is placed in a diffusion furnace facing the wafer shown in FIG. 2 (f), and heat treatment is performed at 800 ° C. in an atmosphere of H ₂ + O ₂ + N ₂ to oxidize the boron glass containing the impurity B. Membrane 5
And n ^{− on} layer 4. Then, the adhered impurities B are shallowly diffused by applying heat treatment at 1100 ° C. for 5 to 15 minutes in an N ₂ atmosphere.

At that time, the boron glass which is formed on the surface and causes nonuniform diffusion is removed by hydrofluoric acid + HNO ₃ .

Furthermore, oxidization is performed in an atmosphere of H ₂ + O _{2 at} 800 ° C. (30 to
60 minutes). By this oxidation, it is possible to take defects in the vicinity of the surface generated in the step of adhering the boron glass and the impurities B that have not been completely removed into the oxide film.

The oxide film thus formed is removed with hydrofluoric acid to expose a clean and defect-free surface.

Then, at 900 to 1000 ° C., in an atmosphere of H ₂ + O ₂ for 15 to 4
Pushing in for 0 minutes (drive-in), p ⁺ area 6
b and the oxide film 7 are formed [FIG. 2 (g)].

Thus, the p ⁺ regions 6a and 6b are connected to each other to form the p ⁺ element isolation region (6a + 6b). Hereinafter, the p ⁺ element isolation region (6a + 6a) will be referred to as the p ⁺ element isolation region 6.

Further, as shown in FIG. 2 (f), after forming the oxide film 5, BSG (boron silicate glass; SiO ₂ film containing B as an impurity) as a diffusion source is formed by the CVD method, and indentation is performed. Then, the p ⁺ region 6b can be formed similarly to the above diffusion.

When the p ⁺ element isolation region 6 is formed in this manner, the oxide film 7 (provided that the oxide film 5 is included) is selectively removed by etching in order to form a base region next, and the buffer film for buffer is formed there. An oxide film 8 is formed [FIG. 2 (h)].

The oxide film 8 is provided to prevent channeling and prevent surface defects when the base region is formed by ion implantation, and has a thickness of 500 to 1500Å. Further, the oxide film 3 of the back coat is completely removed in this step.

Next, B ⁺ ions or B generated using BF ₃ as a source gas.
Implant F ₂ ⁺ ions into the wafer. At this time, the oxide film 7 serves as a mask, and B ⁺ ions are implanted only under the oxide film 8.
The surface concentration is 1 × 10 ^{15 to} 5 × 10 ¹⁸ cm ⁻³ , preferably 1 to 20 × 10 ¹⁶ cm ⁻³ , and the ion implantation amount is 7 × 1.
0 ¹¹ to 1 × 10 ¹⁵ cm ^-2 , preferably 1 × 10 ¹² to 1 × 1
It is 0 ¹⁴ cm ^-2 .

When the ions are implanted in this way, 1000 to 1100
A p-type base region 9 is formed to a predetermined depth by thermal diffusion in a N ₂ atmosphere at a temperature of ₂ ° C. (FIG. 2 (i)).

The depth of the base region 9 is, for example, about 0.6 to 1 μm.

The thickness and impurity concentration of the base region 9 are determined by the following ideas. To increase the sensitivity, it is desirable to reduce the impurity concentration of the base region 9 to reduce the base-emitter capacitance C _be . _Cbe is roughly given as follows.

However, V _bi is the diffusion potential between the emitter and base, Given in. Where ε is the dielectric constant of the silicon crystal, N _D
Is the impurity concentration of the emitter, N _A is the impurity density of the base adjacent to the emitter, n _i is the intrinsic carrier concentration, A _e is the area of the base region, k is the Boltzmann constant, T is the temperature, and q is the unit charge. is there. As N _A becomes smaller, C _be becomes smaller and the sensitivity rises.However, if N _A is made too small, the base region will be completely depleted in the operating state and become a punching through state, so it is not too low. Can not. It is set to such an extent that the base region is not completely depleted and a punching through state does not occur.

As a method of forming the base region 9, BSG is deposited on the wafer by a CVD method, and 1100 to 1200
There is also a method of forming the impurity B by diffusing it to a predetermined depth by thermal diffusion at ℃.

The BSG deposition conditions at this time are as follows: deposition temperature 350 to 450 ° C.
The gas is B ₂ H ₆ + SiH ₄ + O ₂ , and the boron concentration in BSG is 1 × 10.
²¹ is ~5 × 10 ²¹ cm ^-3.

When the p ⁺ element isolation region 6 and the base region 9 are formed in this way, the oxide films 7 and 8 are removed, and a gas (O ₂ + HCl + N ₂ ) is used, and the temperature is 850 to 1000 ° C.
Then, an oxide film 10 having a thickness of several tens to several hundreds of liters is formed [FIG. 2 (j)].

Instead of the oxide film 10, a nitride film (Si
₃ N ₄ ) is also acceptable. The nitride film has a dielectric constant about twice that of SiO ₂ and can obtain a large capacitor capacity. Further, the oxide film (SiO ₂ film) has an advantage that the interface between Si and SiO ₂ is stable, and thermal stress and interface state are small.

When the oxide film 10 is formed, p ⁺ ions are added at 5 × 10 ¹⁰ -1.
X 10 ¹³ cm ^-2 ions are implanted. This ion implantation is performed to determine the threshold voltage V _th of the P channel MOS formed between the base region 9 and the element isolation region 6. In this embodiment, the threshold voltage is set to 0.5-2V.

Then, a nitride film 11 (Si ₃ N ₄ ) is formed on the oxide film 10 to a thickness of 500 to 1500 Å [FIG. 2 (k)]. The formation temperature is 700 to 900 ° C.

Next, a PSG film 12 having a thickness of 2000 is further formed on the nitride film 11.
After forming up to 3000 Å, the oxide film 10, the nitride film 11 and the PSG film 12 are all removed from the portion to become the emitter by the photolithography process including the mask alignment process twice, and the gate of the P-channel MOS transistor and the capacitor C are removed. _{At the ox} portion, the nitride film 11 and the PSG film 12 are removed by etching, leaving the oxide film 10 [FIG. 2 (l)].

After that, As-doped polysilicon is added (N ₂ + SiH ₄ + AsH ₃ ).
Alternatively, it is deposited by a CVD method using (H ₂ + SiH ₄ + AsH ₃ ) gas. The deposition temperature is about 550 ° C to 900 ° C, and the thickness is 200.
It is 0-7000Å. Of course, non-doped polysilicon may be deposited by the CVD method and then As or P may be diffused.

Then, the deposited polysilicon film is removed by etching after the mask alignment photolithography process, and PSG
By etching the film 12, the PSG can be lifted off.
The polysilicon deposited on the film 12 is removed in a self-aligning manner, and the polysilicon 13 and 14 have a thickness of 200
0-7000Å is formed [Fig. 2 (m)].

However, the etching of the deposited polysilicon is C ₂ Cl
₂ F _4, carried out in a gas system such as _{(CB r F 3 + Cl 2} ), the etching of the nitride film 11 is performed with a gas such as CH ₂ F _2.

Subsequently, heat treatment is performed to diffuse the impurities (As) from the polysilicon 13 into the base region 9 to form the n ⁺ emitter region 15 [FIG. 2 (n)].

Next, a PSG film 16 having a thickness of 3000 to 7000 Å is deposited by the above-described gas-based CVD method, and subsequently, a contact hole is opened on the polysilicon 14 by a mask aligning process and an etching process. Electrode 17 (A
metal such as l, Al-Si and Al-Cu-Si) is deposited by vacuum evaporation or sputtering [Fig. 2 (o)].

Subsequently, an interlayer insulating film 18 such as a PSG film or a SiO ₂ film is deposited by a CVD method to a thickness of 3000 to 6000Å. Then, the polysilicon 13 is subjected to a mask alignment and etching process.
A contact hole is opened on the top surface of the electrode 19 (Al, Al-Si,
A metal such as Al-Cu-Si) is formed [Fig. 2 (p)].

And finally, the passivation film 20 (PSG film or Si ₃
N ₄ film, etc.) is formed by the CVD method, and electrodes 2 are formed on the back surface of the wafer.
1 (metal such as Al, Al-Si, Au) is formed and completed [Fig. 2 (g)].

FIG. 3 is a manufacturing process drawing of another embodiment of the present invention.

In FIG. 2 (e), the n ⁻ layer 4 is epitaxially grown to a thickness of 1 to 5 μm under the same conditions as when the n ⁻ epitaxial layer was grown. At that time, the p ⁺ region 6a is formed.

Then, an oxide film a4 having a thickness of 500 to 150 is formed on the n ⁻ layer 4.
0Å is formed, and a resist a5 is further applied thereon to perform resist patterning [FIG. 3 (a)].

Then, B ⁺ is ion-implanted using the resist a5 as a mask (ion implantation amount 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² ).
After the ion implantation, the resist 95 is removed by (H ₂ SO ₄ + H ₂ O ₂ ) and heat treatment is performed at 1000 ° C. to 1100 ° C. for 1 to 2 hours.

By this heat treatment, boron (B) implanted near the surface of the n ⁻ layer 4 is pushed by thermal diffusion, and the p ⁺ region a is formed.
6 is formed and connected to the p ⁺ region 6a. Then, the oxide film a4 is removed [FIG. 3 (b)].

Subsequently, a thickness of 3000 to 70 is formed on the n ⁺ layer 2 on the back surface of the wafer.
An oxide film of 00Å is formed by the CVD method (back coat).

Then, n ^- on the layer 4 n ^- layer 22 is epitaxially grown in the same conditions, to form a ^{p +} region 6b Third FIG
(c)]. The thickness of the n ⁻ layer 22 is 1 to 5 μm, and the impurity concentration is the same as that of the n ⁻ layer 4.

Next, the p ⁺ region 6c is formed by the same method as shown in FIG. 3A, and the p ⁺ regions 6a, 6b and 6c form the p ⁺ element isolation region 6.

Hereinafter, by the steps shown in FIGS. 2 (g) to 2 (q),
The photoelectric conversion device shown in FIG. 3 (d) is completed.

FIG. 4 is a plan view of a photoelectric conversion device in which the photosensor cells shown in FIGS. 2 (q) and 3 (d) are two-dimensionally arranged.

Next, the configuration and operation of this embodiment will be described with reference to FIG. 2 (q) and FIG.

In FIG. 2 (q) and FIG. 4, an n ⁻ epitaxial layer 4 is formed on an n-type silicon substrate 1, and p ⁻ is formed therein.
^{The +} element isolation regions 6 (here, 6a and 6b) are electrically insulated from each other to form a photosensor cell.

In each photosensor cell, a p base region 9 serving as a control electrode region of a bipolar transistor serving as a phototransistor, an n ⁺ emitter region 15 serving as a first main electrode region, and an oxide film 10 are sandwiched on the n ⁻ epitaxial layer 4. Capacitor C for applying a pulse to the gate of the P-MOS transistor and the p base region 9
An electrode polysilicon 14 that also serves as an _ox electrode, an electrode polysilicon 13 connected to the n ⁺ emitter region 15, and an electrode 19 connected to the polysilicon 13 and an electrode connected to the polysilicon 14. It is composed of 17 etc. In FIG. 2 (q), n ⁻ epitaxial layer 4,
And a part of the n-type silicon substrate 1 is the second main electrode region of the phototransistor, the p ⁺ region 6a is the lower region,
The p ⁺ region 6b is the upper region. Further, in FIG. 3D, the n ⁻ layer 22, the n ⁻ layer 4, and a part of the n-type silicon substrate 1 are the second main electrode regions of the phototransistor, and the p ⁺ regions 6a and p ^+. Regions 6b are a lower region and an upper region, respectively, and are p ⁺ regions 6a and p ⁺ regions 6 respectively.
c is the lower region and the upper region, respectively.

The basic operation of the optical sensor cell having such a configuration will be described below.

First, in the charge storage operation, after applying a reverse bias potential to the n ⁺ emitter region 15 in the p base region 9, the potential of the polysilicon 14 is maintained at a positive potential higher than the threshold voltage of the P-MOS transistor, The P-MOS transistor is turned off, and holes generated by light are accumulated in the p base region 9.

Due to the accumulation of holes, the potential of the p base region 9 changes in the positive direction, but the potential of the p base region 9 of each photosensor cell varies depending on the intensity of light.

In this state, a positive read pulse voltage V _R is applied to the polysilicon 14 from the electrode 17. Since the voltage V _R is positive,
The P-MOS transistor remains off.

When the read pulse voltage _{V R} is applied to the polysilicon 14, becomes forward biased with respect to the p base region 9 is the ^{n +} emitter region 15, p of ^{n +} emitter region 15
Electrons are injected into the base region 9, and the potential of the n ⁺ emitter region 15 gradually changes in the positive potential direction. That is,
The information stored in p base region 9 is read out to the emitter side.

After the reading is disturbed for a certain period of time and the pulse voltage V _R is applied, when the polysilicon 14 becomes the ground potential, the p base region 9 is reverse biased with respect to the n ⁺ emitter region 15.
The potential change of the n ⁺ emitter region 15 stops.

In this state, the information on the emitter side is read out through the polysilicon 13 and the electrode 19.

When this reading is completed, the electrode 19 is grounded and the n ⁺ emitter region 15 becomes the ground potential. However, in this state, the potential corresponding to the intensity of light, that is, the optical information is still stored in the p base region 9, so that the optical information needs to be removed.

Therefore, the P-MO is formed on the polysilicon 14 through the electrode 17.
A negative pulse voltage V _RH exceeding the threshold voltage V _th of the S transistor is applied. As a result, the P-MOS transistor becomes in a dynamic state, the holes accumulated in the p base region 9 are removed, and the potential of the p base region is fixed to a predetermined negative voltage applied to the p ⁺ element isolation region 6.

By this refresh operation, the p base region 9 is brought into a completely initial state, and thereafter, the above-mentioned storage, read and refresh operations are repeated.

As described above, since the positive pulse of the polysilicon 14 is applied at the time of reading and the negative pulse is applied at the time of refreshing to turn on the P-MOS transistor, the above operation does not interfere.

By the way, when strong light hits a part of the photoelectric conversion device in which the photosensor cells are arranged as shown in FIG. 4, the p base region 9 of the photosensor cells in that part is forward biased with respect to the n ⁺ emitter region 15. Then, the signal is read out to the emitter side and the blooming phenomenon occurs.

In order to prevent this, the polysilicon 14
At a potential of the p base region 9 approaching zero potential, that is, before a signal is read to the emitter side.
It may be set so that the P-MOS transistor becomes conductive.

By setting the potential of the polysilicon 14 in this way,
Before the p base region 9 and the n ⁺ emitter region 15 are in the forward bias state, the P-MOS transistor is in a dynamic state, excess charges flow out to the p ⁺ element isolation region 6 side, and the blooming phenomenon is prevented. .

FIG. 5 is a circuit diagram of this embodiment. However, although the case where the number of pixels is 2 × 2 = 4 is taken as an example here, a circuit having an arbitrary number of pixels n × n can be easily configured from the circuit of FIG.

In the figure, each of the optical sensor cells E _{11 to} E ₂₂ is shown in FIG.
(q) or the configuration shown in FIG. 3 (d). That is, the p base region 9 of the bipolar transistor 301
And the polysilicon 14 facing each other with the oxide film 10 in between.
Form a capacitor C _ox 302, and the p base region 9, the p ⁺ element isolation region 6, and the polysilicon 14 are formed.
Thus, the P-MOS transistor 303 that serves as the second switch means is formed. In this embodiment, the polysilicon 14
, _Which also serves as one electrode of the capacitor _{Co x} 302 and the gate of the P-MOS transistor 303.
It can also be configured separately as shown in FIG.

Each electrode 17 of the photosensor cells E ₁₁ and E ₁₂ is connected to the first parallel output terminal of the shift register A via a switching transistor (hereinafter referred to as SWT) 304, and further connected to a terminal T ₃ via an SWT 305. Has been done.

The electrodes 17 of the photosensor cells E ₂₁ and E ₂₂ are SWT
It is connected to the second parallel output terminal of the shift register A via 306, and further connected to the terminal T ₃ via SWT307.

The gate terminals of SWT304 and 306 are terminals T
₁ , each gate terminal of SWT305 and 307 is terminal T
₂ are each connected.

The emitter electrode 19 of each bipolar transistor 301 of the photosensor cells E ₁₁ and E ₂₁ is connected to the output terminal via the SWT 308 and further serves as a first switch means.
It is grounded through SWT309.

Each emitter electrode 19 of the photosensor cells E ₁₂ and E ₂₂
Is connected to the output terminal via the SWT 310, and is further grounded via the SWT 311 serving as the first switch means.

The gate terminals of the SWTs 308 and 310 are connected to the first and second parallel output terminals of the shift register B, respectively, and the gate terminals of the SWTs 309 and 311 are connected to the terminal T ₄ .

A predetermined negative voltage V is applied to the source region of the P-MOS transistor 303 of each photosensor cell, that is, the p ⁺ element isolation region 6.
_BB is applied, and a predetermined positive voltage V _CC is applied to the collector electrode 21 of the bipolar transistor 301 of each photosensor cell.
Is being applied.

Moreover, a voltage is applied to each of the terminals T _{1 to} T ₄ at a predetermined timing to turn on the corresponding SWT.

A shift pulse is input to the shift registers A and B at a predetermined timing, and a high level (positive voltage V _R ) is sequentially output from each parallel output terminal.

The operation of the circuit of this embodiment having such a configuration will be briefly described.

First, the SWTs 304, 306, 308, and 310 are turned off, and the SWTs 305, 307, 309, and 311 are turned on, and a negative voltage pulse for refresh is applied to the terminal T ₃ . As a result, the all-optical sensor cell E
Refresh operations _{11 to} E ₂₂ are performed.

Subsequently, the SWTs 305 and 307 are turned off, and the charge accumulation operation is performed. As a result, optical information at that location is stored in each p base region 9.

Next, the SWTs 309 and 311 are turned off, the SWTs 304 and 306 are turned on, and the operation of sequentially reading the accumulated information is performed.

First, by setting the first parallel output terminal of the shift register A to a high level, a positive voltage V _R is applied to each electrode 17 of the photosensor cells E ₁₁ and E ₁₂ , and the information stored in the p base region 9 is stored. Is read to the emitter side. Subsequently, the first and second parallel output terminals of the shift register B are sequentially set to the high level, and the SWT308 and SWT310 are sequentially turned on. By this operation, the increased salary accumulated in the optical sensor cells E ₁₁ and E ₁₂ is sequentially output to the outside.

Next, the second parallel output terminal of the shift register A is set to a high level and the shift register B is operated as described above, so that the information stored in the photosensor cells E ₂₁ and E ₂₂ is similarly sequentially output to the outside. Output.

When the reading is completed in this way, the above-described refresh operation is performed, and thereafter, the accumulation, reading, and refresh operations are repeated.

〔The invention's effect〕

As described in detail above, in the semiconductor device according to the present invention, the element isolation region is formed in a plurality of stages, so that the element isolation region having a narrow width and a deep width can be obtained.

Since the element isolation region is deeply formed, element isolation is complete.

Since the width of the element isolation region is narrow, the element surface can be effectively used, and the element can be made smaller.

Since the width of the element isolation region is narrow and deep, the resistance value can be suppressed to a low value even if the element isolation region is laid around in the chip, and the potential distribution can be substantially prevented even when a potential is applied. it can.

[Brief description of drawings]

FIG. 1 (a) is a plan view of a conventional photoelectric conversion device, FIG. 1 (b) is a plan view of the line AA ′, and FIGS. 2 (a) to (q) are manufacturing of a semiconductor device according to the present invention. Manufacturing process drawing of the first embodiment of the method, FIGS. 3 (a) to (d) are manufacturing process drawings of the second embodiment of the present invention with a part omitted, and FIG. FIG. 5 is a plan view of the device manufactured by the above method, and FIG. 5 is a circuit diagram for explaining the operation of the device manufactured by the first or second embodiment. 1 ... Substrate, 4 ... Epitaxial layer, 6 ... Element isolation region, 9 ... Base region, 10 ... Oxide film, 13, 14
...... Polysilicon (for electrodes), 15 ・ ・ ・ Emitter region.

Claims (3)

[Claims] 1. A control electrode region made of a semiconductor of a first conductivity type capable of accumulating carriers by receiving light energy, and first and second semiconductors of a second conductivity type different from the first conductivity type. In a semiconductor device having a phototransistor having, and an output circuit connected to the first main electrode region, the first main electrode region is provided with respect to a first reference voltage source. First switch means for electrically coupling and eliminating carriers accumulated in the control electrode region, and second switch means for electrically coupling the control electrode region to a second reference voltage source. And the second switch means places the control electrode region and an element isolation region made of a semiconductor of the first conductivity type in a conductive state at a suitable time, wherein the element isolation region is of the second conductivity type. Table of semiconductor substrate After forming a lower region made of a semiconductor of the first conductivity type formed thereon, a semiconductor layer of a second conductivity type which is at least a part of the second main electrode region is formed on the lower region, and thereafter. A semiconductor device including the lower region and the upper region, which is obtained by forming an upper region made of a semiconductor of a first conductivity type in contact with the lower region from a surface side of the semiconductor layer. 2. The semiconductor device according to claim 1, wherein the phototransistor is a bipolar transistor. 3. The semiconductor device according to claim 1 or 2, wherein the second switch means is a PMOS transistor.