JPH07123160B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device , and more particularly to efficiently manufacturing peripheral elements at the same time and shining strong light.
Also relates to a semiconductor device that does not malfunction . The present invention is, for example, a photoelectric conversion method in which carriers generated by photoexcitation are accumulated and the accumulated voltage generated by the accumulated carriers is read.
It is applied to exchange devices .

[0002]

2. Description of the Related Art FIG. 14 shows a photoelectric conversion device described in Japanese Patent Application No. 58-120755.
FIG. 14A is a plan view of a photoelectric conversion device in which photosensor cells are two-dimensionally arranged, and FIG. 14B is a sectional view taken along the line AA ′.

In FIGS. 14A and 14B, n ⁺
Photosensor cells are arranged on a silicon substrate 101, and each photosensor cell is electrically insulated from an adjacent photosensor cell by an element isolation region 102 made of SiO ₂ , Si ₃ N ₄ or polysilicon.

Each photosensor cell includes an n ⁻ region 103 having a low impurity concentration formed by an epitaxial technique or the like, a base of a bipolar transistor doped with p type impurities (such as boron), and a P channel MO.
The p region 104 which becomes the source of the S transistor and the p region 10 which becomes the drain of the P channel MOS transistor.
5. n ⁺ that becomes the emitter of the bipolar transistor
A gate electrode 108 of the P-channel MOS transistor sandwiching the region 106 and the oxide film 107, a MOS capacitor electrode 109 for applying a pulse to the p region 104 through the oxide film 107, an emitter electrode 110, and a p region 10.
5 is provided with an electrode 111 or the like for applying a predetermined potential.

The operation of the optical sensor cell having such a configuration will be described. First, in the charge accumulation operation, the p region 104, which is the base, is biased to a negative voltage with respect to the n ⁺ region 106, and holes generated by light are accumulated. Due to the accumulation of holes, the potential of the p region 104 changes in the positive direction, but the potential of the p region 104 of each photosensor cell varies depending on the intensity of light.

A read operation is performed in this state. That is, the read pulse voltage V _R is the MOS capacitor electrode 109.
Is applied to the p region 104, the p region 104 has a positive potential, and the information accumulated in the p region 104 is the n ⁺ region 10 which is the emitter.
6 side is read. Then, the read pulse voltage V _R is set to the ground potential, and the n ⁺ region 106 moves from the emitter electrode 110.
Information is output to the outside through.

Next, a refresh operation is performed by applying a negative pulse to the gate electrode 108 in a state where the potential of the p region 104 differs depending on the intensity of light. By this negative pulse, the P-channel MOS transistor is rendered conductive, the holes accumulated in p region 104 are removed, and p region 104 is fixed at a predetermined negative voltage. That is, the refresh operation completes the initialization of the base p region 104, and thereafter, the above-described operations of accumulation, reading, and refresh are repeated.

As described above, by fixing the p region 104, which is the base, to a predetermined negative voltage during the refresh operation,
Optical information can be completely erased at high speed regardless of the intensity of light.

[0009]

However, particularly in the photoelectric conversion device, it is desirable to effectively utilize the element surface in response to the demand for improved sensitivity and higher resolution.

In this respect, the conventional photoelectric conversion device is not sufficient. That is, as shown in FIG. 14, since the device isolation region 102 made of an insulating material is provided, the device becomes larger by this region and one main electrode of the P-channel MOS transistor which becomes conductive at the time of refreshing. It is necessary to specially provide a wiring for applying a predetermined negative voltage to the region. Further, since the step of forming the element isolation region made of an insulating material is required independently, there is a problem that the manufacturing process becomes complicated especially when the peripheral elements are formed on the same chip. In addition, in JP-A-55-30855
Is a capacitor stored in the gate of the static induction transistor.
A clear area for pulling out the rear surrounds a part of each pixel.
Image sensors are described. However,
In the image sensor, the clear operation is integrated with the gate
Since only the MOS transistor is used,
The noise due to the on / off of the transistor appears in the output signal.
There were times when it happened. Also, even when exposed to strong light
For example, in an overflowing carrier like blooming
More malfunctions may occur.

The present invention has been made in view of the above conventional problems, and its purpose is to effectively utilize the element surface and simultaneously form peripheral elements to simplify the manufacturing process.
It is to provide a semiconductor device . Furthermore, another aspect of the present invention
The purpose is to create a semiconductor device that does not easily malfunction even when exposed to strong light.
To provide.

[0012]

In order to achieve the above object , the semiconductor device according to the present invention is a semiconductor of the first conductivity type.
Accumulate carriers by receiving light energy
Possible control electrode area and second different from the first conductivity type
First and second main electrode regions made of a conductive type semiconductor,
And a phototransistor having a contact with the first main electrode region.
A connection output circuit, a semiconductor device having a front
Electrically connect the first main electrode area to the first reference voltage source.
Disappears from carriers accumulated in the control electrode region
The first switch means for controlling the
A second switch for electrically coupling to the second reference voltage source.
Switch means and laterally arranged to the phototransistor
As a peripheral element formed in the semiconductor region of the first conductivity type
An insulating gate having a main electrode region made of a second conductivity type semiconductor.
And a gate-type transistor.

The semiconductor device of the present invention is of the first conductivity type.
It is made of semiconductor and receives light energy
Control electrode area that can store
First and second main electrodes made of a second conductivity type semiconductor
A phototransistor having a region, and the first main electrode
A semiconductor device having an output circuit connected to the region,
There are, transistor for the control electrode region and the main electrode region
And the transistor has a
The control electrode region is electrically connected and during the accumulation operation period.
Is characterized in that it conducts even when the voltage reaches a predetermined potential.
It

According to the present invention, the control is performed by the second switch means.
The potential of the control electrode area is kept constant and the first switch
The main electrode area connected to the output circuit is fixed by
By setting the potential, the control electrode area and the main electrode area
A current flows between them to perform a refresh operation. Therefore
Noise from the second switch means appears on the output circuit side
Can be prevented. Moreover, the element as the second switch means
High integration is possible by using the separation region.

That is, according to the technique disclosed in JP-A-55-30855.
When the MOS transistor is turned on, the gate potential is
Once it reaches a constant potential (V _B ), the MOS transistor
The gate potential is V _B + α when off due to the gate capacitance of
Fluctuates. This variation α depends on the variation of the gate capacitance of each cell.
Since it largely depends on the woodpecker, what is the reset operation?
No, fixed pattern noise remains as the initial potential of the gate.
It is.

On the other hand, the main electrode area on the signal output circuit side
If you also use a reset operation that fixes the region to a predetermined potential,
A current flows in the junction between the control electrode area and the main electrode area, causing fluctuation
The variation of the component α is converged and the voltage of the control electrode area of each cell is
The position (initial potential) is constant .

Further , according to the present invention, a refresh transistor is used.
Can use a transistor to absorb excess photocarriers
Therefore, it does not malfunction even when exposed to strong light.
Further, the peripheral element is formed in the surrounding semiconductor region.
Therefore, the optical carrier is absorbed here, and no malfunction occurs.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First, a method of manufacturing a semiconductor device of the present invention
Will be described.

4 to 13 show one embodiment of the semiconductor device of the present invention.
It is a manufacturing process diagram showing a manufacturing method of the embodiment, the case of a photoelectric conversion device is taken up in the present embodiment.

First, as shown in FIG. 4 , on the back surface of the n-type substrate 1 having an impurity concentration of 1 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ ,
An n ⁺ layer 2 for ohmic contact having an impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ is formed by diffusion of P, As or Sb. Subsequently, a thickness of 3000 to 7 is formed on the n ⁺ layer 2.
A 000Å oxide film 3 (for example, a SiO ₂ film) is formed by the CVD method. The oxide film 3 is called a back coat,
It is intended to prevent generation of impurity vapor when the substrate 1 is heat-treated.

Next, the surface of the substrate 1 is heated at a temperature of 1000.degree.
HCl 2 liters / min, H ₂ 60 liters / m
After etching for about 1.5 minutes under the condition of in, the source gas SiH ₂ Cl ₂ (100%) is added to 1.2 liter / mi.
n, doping gas (H ₂ diluted PH ₃ , 20 PPM) is passed through 100 cc, growth temperature is 1000 ° C., 120 to 180
N ⁻ epitaxial layer 4 under reduced pressure of Torr
(Hereinafter, referred to as n ⁻ layer 4) is formed. At this time, the single crystal growth rate is 0.5 μm / min, the thickness is 2 to 10 μm,
The impurity concentration is 1 × 10 ¹² to 10 ¹⁶ cm ⁻³ , preferably 10 ¹² to 10 ¹⁴ cm ⁻³ ( FIG. 5 ).

In order to improve the quality of the n ⁻ layer 4, the substrate is first subjected to a high temperature treatment of about 1150 to 1250 ° C. to remove oxygen from the vicinity of the surface, and then a long-term heat treatment of about 800 ° C. is applied to the inside of the substrate. It is also extremely effective to use a substrate having a denuded zone and capable of intrinsic gettering by generating a large number of microdefects.

Then, a thickness of 4000 to 80 is formed on the n ⁻ layer 4.
Pyrogeneck oxidation (H ₂ + O) of the oxide film of 00Å
₂ ), wet oxidation (O ₂ + H ₂ O), or steam oxidation (N ₂ + H ₂ O). Furthermore, high-pressure oxidation at a temperature of 800 to 1000 ° C. is suitable for obtaining a good oxide film without stacking faults.

Then, in order to form a p-type semiconductor region (hereinafter referred to as a p-well) for the element isolation region and the peripheral element, a part of the oxide film 5 is selectively removed by photolithography, and then, Then, the oxide film 6 for buffer is formed to a thickness of 500 to 1500Å ( FIG. 6 ).

Next, using the oxide film 5 as a mask, B ⁺ ion implantation is performed (ion implantation amount 1 to 10 × 10 ¹² c).
m ^-2 ). Then, heat treatment at 1150 to 1200 ° C. for 5
Perform for 10 hours, push in impurities (drive-in), p
Well 7 and element isolation regions 8 and 9 are formed simultaneously ( FIG. 7 ).

Then, after removing the oxide films 5 and 6,
An oxide film 10 having a thickness of 500 to 1500 Å and a nitride film 11 (Si ₃ N ₄ ) are formed thereon. Then, the nitride film 11 is patterned to form a region (channel stopper) for separating peripheral elements ( FIG. 8 ).

Then, using the nitride film 11 as a mask, B ⁺
Ion implantation is performed (ion implantation amount 1 to 10 × 10 ¹³ c
m ⁻² ), and then the p region 12 for channel stop is formed by heat treatment at 1000 ° C. for 10 minutes. Then, perform pyrogenec oxidation at 1000 ° C to obtain a thickness of 8
000 to 12000 Å separation area 13 is formed ( Fig.
9 ).

Then, the nitride film 11 is removed to a thickness of 0.
A resist 14 having a thickness of 7 to 1.2 μm is applied on the oxide film 10, and a base region is formed and resist patterning is performed for an element isolation region to be overlaid ( FIG. 10 ).

Next, using the resist 14 as a mask, B ⁺
Ion implantation (ion implantation amount 7 × 10 ¹¹ to 1 × 10
¹⁵ cm ^-2 ). Then, after removing the resist 14, N ₂
Heat treatment is performed at 1000 to 1100 ° C. in the atmosphere to form p regions 15 and 16 and base region 17 over element isolation regions 8 and 9. Then, (H ₂ + O
₂ ) Oxidize at 1000 ° C. for 1 to 2 hours in a gas to form an oxide film 18 having a thickness of 3000 to 5000 Å. However, the oxide film 18 includes the oxide film 10 ( FIG. 11 ).

The depth of the base region 17 is, for example, 0.6-.
About 1 μm, but the base region 17 and the p region 1
As a method of forming 5, 16, there is also a method of depositing BSG on a wafer and diffusing the impurity B to a predetermined depth by thermal diffusion at 1100 to 1200 ° C.

Next, the P-channel MOS transistor and the capacitor portion and the emitter portion, and the peripheral element (here, N-channel MOS transistor) portion are patterned to form the gate oxide film 19 with a thickness of several tens to several hundreds of Å. Formed ( FIG. 12 ).

After the oxide film 19 is formed, B ⁺ ions are implanted (ion implantation amount 5 × 10 ¹⁰ to 1 × 10 ¹² c).
m ^-2 ). The ion implantation is a P channel MOS formed between the base region 17 and the element isolation region (p region) 15.
This is performed to determine the threshold voltage V _{th of the} transistor.

Next, the oxide film 19 in the emitter portion and the oxide film 19 in the source and drain portions of the N-channel MOS transistor are patterned, and As-doped polysilicon is formed thereon (N ₂ + SiH ₄ + AsH ₃ ). Alternatively, a (H ₂ + SiH ₄ + AsH ₃ ) gas is deposited by a CVD method to a thickness of 2000 to 7,000 Å. Of course, non-doped polysilicon may be deposited by the CVD method and then As or P may be diffused.

Then, the deposited polysilicon film is removed by etching after the mask aligning photolithography step to form polysilicon 20, 21 and 22. However, the etching of the deposited polysilicon is performed using C ₂ Cl ₂
It is performed in a gas system such as F ₄ , (CBrF ₃ + Cl ₂ ).

Subsequently, heat treatment is performed to diffuse the impurities (As) from the polysilicon 21 into the base region 17 to form the n ⁺ emitter region 23.

Subsequently, P ⁺ and As ⁺ ions are added at 1 × 10 ¹⁴
˜1 × 10 ¹⁶ cm ⁻² ions are implanted. Ions are masked by the field oxide film 18 and the polysilicon 20, 21, 22 and are implanted only in a predetermined portion. Further, by heat treatment, NMOS source and drain 24 and 25 are formed ( FIG. 13 ).

Next, a PSG having a thickness of 3000 to 7000Å
A film 26 is deposited by the CVD method, and then a contact hole is opened on the polysilicon 20 by a mask aligning process and an etching process. Electrode 27 in this contact hole
(Metal such as Al, Al-Si, Al-Cu-Si) is deposited by vacuum evaporation or sputtering.

Subsequently, an interlayer insulating film 28 such as a PSG film or a SiO ₂ film is deposited by the CVD method to a thickness of 3000 to 6000Å. Then, contact holes are opened on the polysilicons 21 and 22 by a mask alignment and etching process to form electrodes 29 and 30 (Al, Al-Si, A).
a metal such as 1-Cu-Si).

Finally, the passivation film 31
(PSG film or Si ₃ N ₄ film or the like) is formed by the CVD method, and electrodes (metals such as Al, Al—Si, Au, etc.) are formed on the back surface of the wafer to complete the semiconductor device of this embodiment ( FIG.
1 ).

Although the N-channel MOS transistor is taken as the peripheral element in the present embodiment, it is needless to say that it is not limited to this and a CMOS or the like may be used. That is, any peripheral element that requires a semiconductor region having the same conductivity type as the element isolation regions 8 and 9 may be used.

FIG . 2 shows the optical sensor cell shown in FIG.
It is a top view of the photoelectric conversion device arranged in dimension.

Next, with reference to FIGS. 1 and 2, the configuration and operation of the semiconductor device of this embodiment.

[0044] In the photosensor cell shown in FIG. 1 and FIG. 2, n on the substrate 1 of n-type silicon ^- epitaxial layer 4 is formed, p ⁺ isolation regions 15 and 16 therein
(However, here, including 8 and 9) are electrically insulated from each other to form a photosensor cell.

[0045] Each light sensor cell, n ^- control of light transistor serving as a bipolar transistor on the epitaxial layer 4
P base region 17 serving as a control electrode region , first main electrode region
With the n ⁺ emitter region 23 and the oxide film 18 sandwiched between
Polysilicon 20 for the electrode to the gate and the p base region 17 of the -MOS transistor also serves as a capacitor C _OX electrode for applying a pulse, n ⁺ emitter region 23
And the electrode 29 connected to the polysilicon 21, the electrode 29 connected to the polysilicon 21, the electrode 27 connected to the polysilicon 20, and the like. Note that n
Type silicon substrate 1 and part of the n ⁻ epitaxial layer 4
It becomes the second main electrode region of the phototransistor. Also, p ⁺
The element isolation regions 15 and 8 and the p base region 17 are the second switch.
Source / drain of P-MOS transistor as a switching means
It becomes the in area.

The basic operation of the optical sensor cell having such a structure will be described below.

First, the charge accumulation operation is performed in the p base region 17
After applying a reverse bias potential to the n ⁺ emitter region 23, the potential of the polysilicon 20 is maintained at a positive potential higher than the threshold voltage of the P-MOS transistor, the P-MOS transistor is turned off, and the p-base is turned on. Holes generated by light are accumulated in the region 17.

By accumulating holes, the p base region 17 is formed.
Potential changes in the positive direction, but the potential of the p base region 17 of each photosensor cell varies depending on the intensity of light.

In this state, a positive read pulse voltage V _R is applied to the polysilicon 20 from the electrode 27. Voltage V _R
Is positive, the P-MOS transistor remains off.

The read pulse voltage V _R is the polysilicon 20.
Is applied to the n ⁺ emitter region 23, the p base region 17 is forward biased, and electrons are injected from the n ⁺ emitter region 23 into the p base region 17,
The potential of n ⁺ emitter region 23 gradually changes in the positive potential direction. That is, the information accumulated in p base region 17 is read out to the emitter side.

[0051] After a certain time the read pulse voltage V _R is applied, the polysilicon 20 becomes the ground potential, becomes reverse biased state with respect to the p base region 17 n ⁺ emitter region 23, the n ⁺ emitter region 23 The potential change stops.

In this state, the information on the emitter side is read out through polysilicon 21 and electrode 29.

When this reading is completed, the electrode 29 is grounded and the n ⁺ emitter region 23 becomes the ground potential. However, in this state, the potential corresponding to the intensity of light, that is, the optical information is still stored in the p base region 17, so it is necessary to remove this optical information.

Therefore, a negative pulse voltage V _RH exceeding the threshold voltage V _th of the P-MOS transistor is applied to the polysilicon 20 through the electrode 27. This makes P-
The MOS transistor becomes conductive, and the p base region 1
The holes accumulated in 7 are removed, and the potential of the p base region 17 is fixed to a predetermined negative voltage applied to the p ⁺ element isolation region 15.

By this refresh operation, the p base region 17 is brought into a completely initial state, and thereafter, the above-mentioned accumulation,
The read and refresh operations are repeated.

By the way, when a strong light hits a part of the photoelectric conversion device in which the photosensor cells are arranged as shown in FIG. 2 , the p base region 17 of the photosensor cell in that part is forwarded with respect to the n ⁺ emitter region 23. A directional bias is applied, a signal is read out to the emitter side, and a blooming phenomenon occurs.

In order to prevent this, during the accumulation operation, the potential of the polysilicon 20 is set to P- while the potential of the p base region 17 is close to zero potential, that is, before the signal is read to the emitter side. It may be set so that the MOS transistor becomes conductive.

By setting the potential of the polysilicon 20 in this way, the p base region 17 and the n ⁺ emitter region 23 are formed.
Before and become the forward bias state, the P-MOS transistor becomes conductive, excess charges flow out to the side of the p ⁺ element isolation region 15, and the blooming phenomenon is prevented.

It should be noted that, as shown in FIG.
The NMOS transistor has the same conductivity as the p base region 17.
It is provided in the electric p well 7 and, for example, the p base region.
Even if excess optical carriers (holes) overflow from area 17,
The photo carrier disappears in the p-well 7 and the NMOS transistor
Never flows into the source / drain region of the star
Then, the overflowed photo carriers of the NMOS transistor
It does not adversely affect the operation.

FIG . 3 is a circuit diagram of the semiconductor device of this embodiment. However, although the case where the number of pixels is 2 × 2 = 4 is taken as an example here, a circuit having an arbitrary number of pixels n × n can be easily configured from the circuit of FIG.

In the figure, each of the optical sensor cells E _{11 to} E _{22 is shown.}
Has the structure shown in FIGS. That is, the p base region 17 of the bipolar transistor 301
And the polysilicon 20 facing each other with the oxide film 18 in between.
Form a capacitor C _OX 302, and the p base region 17, the p ⁺ element isolation region 15, and the polysilicon 20 form a P-MOS transistor 303 that serves as a second switch means . In this embodiment, the polysilicon 20 is connected to one electrode of the capacitor C _OX 302 and P-M.
Although it also serves as the gate of the OS transistor 303, it can be configured separately as in the conventional example (FIG. 14).

Electrodes 27 of photosensor cells E ₁₁ and E ₁₂
Is a switching transistor (hereinafter referred to as SWT)
It is connected to the first parallel output terminal of the shift register A via 304, and further connected to the terminal T ₃ via SWT305.

Electrodes 27 of photosensor cells E ₂₁ and E ₂₂
Is connected to the second parallel output terminal of the shift register A via the SWT 306, and is further connected to the terminal T ₃ via the SWT 307.

The gate terminals of the SWTs 304 and 306 are connected to the terminal T ₁ , and the gate terminals of the SWTs 305 and 307 are connected to the terminal T ₂ .

The emitter electrode 29 of each bipolar transistor 301 of the photosensor cells E ₁₁ and E ₂₁ is SWT3.
08 is connected to the output terminal via the first switch
It is grounded through SWT309 which is a means .

Each emitter electrode 29 of the photosensor cells E ₁₂ and E ₂₂ is connected to the output terminal via the SWT 310, and is further grounded via the SWT 311 serving as the first switch means .

The gate terminals of the SWTs 308 and 310 are connected to the first and second parallel output terminals of the shift register B, respectively, and the SWTs 309 and 311 are connected.
Each gate terminal of is connected to terminal T ₄ .

A predetermined negative voltage V _BB is applied to the source region of the P-MOS transistor 303 of each photosensor cell, that is, the p ⁺ element isolation region 15, and a predetermined negative voltage V _BB is applied to the collector electrode of the bipolar transistor 301 of each photosensor cell. The positive voltage V _CC is applied.

A voltage is applied to each of the terminals T _{1 to} T ₄ at a predetermined timing to turn on the corresponding SWT.

A shift pulse is input to the shift registers A and B at a predetermined timing, and a high level (positive voltage V _R ) is sequentially output from each parallel output terminal.

Here, the SWTs 304 to 311 are the peripheral elements.

The operation of the circuit of this embodiment having such a configuration will be briefly described.

First, the SWTs 304, 306, 308, and 310 are turned off, and the SWTs 305, 307, and 30 are turned off.
With 9 and 311 turned on, a negative voltage pulse for refresh is applied to the terminal T ₃ . As a result, the refresh operation of the all-optical sensor cells E _{11 to} E ₂₂ is performed.

Then, the SWTs 305 and 307 are turned off to perform the charge accumulation operation. This allows each p
The light information at that location is stored in the base region 17.

Next, the SWTs 309 and 311 are turned off and the SWTs 304 and 306 are turned on, and the operation of sequentially reading the accumulated information is performed.

First, by setting the first parallel output terminal of the shift register A to a high level, a positive voltage V _R is applied to each electrode 27 of the photosensor cells E ₁₁ and E ₁₂ , and accumulated in the p base region 17. Information is read to the emitter side. Subsequently, the first and second parallel output terminals of the shift register B are sequentially set to the high level, and the SWT308, and the SW
The T310 is sequentially turned on. By this operation, the information accumulated in the optical sensor cells E ₁₁ and E ₁₂ is sequentially output to the outside.

Next, the second parallel output terminal of the shift register A is set to the high level and the shift register B is operated as described above, so that the information stored in the photosensor cells E ₂₁ and E ₂₂ is similarly stored. Output sequentially to the outside.

When the reading is completed in this way, the above-described refresh operation is performed, and thereafter, the accumulation, reading, and refreshing operations are repeated.

[0079]

As described in detail above , according to the semiconductor device of the present invention , noise can be suppressed.
It In addition, using a reset transistor
Can be prevented.

In addition, peripheral elements are controlled by phototransistors.
Can be formed in a semiconductor region of the same conductivity type as the electrode region
The excess photocarriers overflow the control electrode area.
Is absorbed by the semiconductor region and adversely affects peripheral elements.
Does not reach.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a semiconductor device of the present invention .
It is a side view.

FIG. 2 is a plan view of the semiconductor device of this embodiment.

FIG. 3 is a diagram for explaining the operation of the semiconductor device of this embodiment .
It is a circuit diagram.

FIG. 4 shows a manufacturing method of an embodiment of a semiconductor device of the present invention .
It is to manufacturing process diagrams.

FIG. 5 shows a manufacturing method of an embodiment of the semiconductor device of the present invention .
It is to manufacturing process diagrams.

FIG. 6 shows a manufacturing method of an embodiment of a semiconductor device of the present invention .
It is to manufacturing process diagrams.

FIG. 7 shows a manufacturing method of an embodiment of the semiconductor device of the present invention .
It is to manufacturing process diagrams.

FIG. 8 shows a manufacturing method of an embodiment of a semiconductor device of the present invention .
It is to manufacturing process diagrams.

FIG. 9 shows a manufacturing method of an embodiment of the semiconductor device of the present invention .
It is to manufacturing process diagrams.

FIG. 10 shows a manufacturing method of an embodiment of the semiconductor device of the present invention .
Is a manufacturing process drawing showing.

FIG. 11 shows a manufacturing method of an embodiment of the semiconductor device of the present invention .
Is a manufacturing process drawing showing.

FIG. 12 shows a manufacturing method of an embodiment of the semiconductor device of the present invention .
FIG.

FIG. 13 shows a method of manufacturing a semiconductor device according to an embodiment of the present invention .
FIG.

FIG. 14A is a plan view of a conventional photoelectric conversion device,
(B) is the AA 'line sectional view.

[Explanation of reference symbols] 1 substrate 4 n ^- epitaxial layer 8, 15, 9, 16 element isolation region 17 p ⁺ base region 23 n ⁺ emitter region

Claims (4)

[Claims] 1. Light energy comprising a semiconductor of the first conductivity type
Control electrode area that can accumulate carriers by receiving
And a semiconductor of a second conductivity type different from the first conductivity type
A first and a second main electrode region consisting of
Yusuke and register, and an output circuit connected to the first main electrode region
In the semiconductor device according to claim 1, the first main electrode region is electrically connected to the first reference voltage source.
Carriers that are bound to each other and stored in the control electrode region are erased.
To electrically switch the control electrode area to the second reference voltage source.
Second switch means for coupling, and a first conductivity type semi-conductor disposed laterally of the phototransistor.
As a peripheral element formed in the conductor region, a second conductivity type half
Insulated gate type transistor having a main electrode region made of a conductor
And a semiconductor device. 2. The semiconductor device according to claim 1, wherein
The second switch means is a P-channel MOS transistor
And the insulated gate transistor is an N-channel MO
A semiconductor device that is an S transistor. 3. The semiconductor device according to claim 1 , wherein the phototransistor is a bipolar transistor. 4. Light energy comprising a semiconductor of the first conductivity type
Control electrode area that can accumulate carriers by receiving
And a semiconductor of a second conductivity type different from the first conductivity type
A first and a second main electrode region consisting of
Yusuke and register, and an output circuit connected to the first main electrode region
A semiconductor device having a transistor having the control electrode region as a main electrode region.
However , if the transistor becomes conductive during the refresh operation,
In both cases, the control electrode area has a predetermined voltage during the accumulation operation.
A semiconductor device characterized by conducting even when it reaches the position
Place