JPS61114572A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive securely separating an element and miniaturizing by forming an element separation region forming a reverse conductive type polycrystalline semiconductor in a groove formed with a required depth at the position where the element separation region is to be formed. CONSTITUTION:An n<+> layer 2 for ohmic contact and an oxide film 3 are formed on the back surface of an n-type silicon substrate 1, an n<-> epitaxial layer 4 and an oxide film 5 are formed on the front surface of the substrate 1 and a groove G for forming an element separation region is formed using the film 5 as a mask. Then, polysilicon 6 is buried in the groove G and the silicon 6 is made the element separation region 6 diffusing boron in the silicon 6. Then, an oxide film 7 for buffer is formed on the surface, a B<+> ion is implanted in a wafer using a resist 8 as a mask, the resist 8 is removed, a (p) region 9 to be made a base is formed by heat treatment and an oxide film 10, polysilicon 13, 14, an n<+> emitter region 15, electrodes 17, 19, an interlayer insulation film 18 and a passivation film 20 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device having an element isolation region, and particularly relates to a method for manufacturing a semiconductor device having an element isolation region. The present invention relates to a method of manufacturing a semiconductor device that is separated into two parts.

[Prior art]

FIG. 4(&) is a plan view of the photoelectric conversion device described in Japanese Patent Application No. 120755/1982, and FIG. 4(b) is a sectional view taken along the line A-A'.

In FIGS. 4(-) and 4(b), optical sensor cells are arranged on an n+ silicon substrate 101, and each sensor cell is connected to the adjacent optical sensor cell by an element isolation region 102 made of 5io2, 5tsN4, polysilicon, or the like. electrically isolated from

Each optical sensor cell has the following configuration.

Low impurity concentration n formed by epitaxial technology etc.
By doping a p-type impurity (such as Tatoebazolone) on the ``'' region 103, p regions 104 and 10 are formed.
5 is formed, and an n+ region 106 is formed in the p region 104.

P regions 104 and 105 are the source and drain of a p-channel MO8 transistor, respectively;
4 and? Regions 106 are the base and emitter of an NPN bipolar transistor, respectively. That is, p region 104 serves both as the source of the p-channel MO8 transistor and as the base of the NPN transistor.

An oxide film 107 is formed on the n-region 103 in which each region is formed in this way, and a dirt electrode 108 of the p-channel MO8 transistor and a MOS capacitor electrode 109 are formed on the oxide film 107. . MOS capacitor electrode 109 is connected to p region 104 with oxide film 107 in between.
Facing them, they form a canon.

Other emitter electrodes 1 connected to the vcn+ region 106
10. Electrodes 111 connected to p-region 105 are respectively formed.

The light is transmitted to the p region 10 which is the base of the bipolar transistor.
4, and charges corresponding to the amount of light are accumulated in the p region 104 (accumulation operation). The pace potential changes depending on the accumulated charge, and by reading out the potential change from the emitter electrode 110, an electric signal corresponding to the amount of incident light can be obtained (reading operation). Furthermore, in order to reset the p-region 104 to a predetermined potential (here, a negative potential), a predetermined voltage is applied to the electrode 111, and a voltage is applied to the dirt electrode 108 to make the p-channel MO8 transistor conductive. Good (refreshing, working). This refresh. By this operation, the p-region 104, which is the base, has been completely initialized, and the above-described operations of storage, readout, and retrieval are repeated thereafter.

In this way, by fixing the base p-region 104 to a predetermined negative voltage during the refresh operation, optical information can be completely and quickly erased regardless of the intensity of light.

[Problem that the invention seeks to solve]

However, especially in photoelectric conversion devices, it is desirable to effectively utilize the element surface due to demands for improved sensitivity and higher resolution.

In this respect, conventional photoelectric conversion devices were not sufficient. That is, as shown in FIG. 1, since it has a VC, an element isolation region 102 made of an insulating material, and a p region 105,
The element becomes larger by this area, and the refresh
It is necessary to provide a special wiring for applying a predetermined negative voltage to one main electrode region 105 of the p-channel MOS transistor, which sometimes becomes conductive.

On the other hand, in the case of element isolation regions made of semiconductors, the thickness is 2 to 4 μm.
If the wire is routed around the inside of the chip with a width of 2,500 to 5,000 times the sheet resistance, a problem arises in which potential distribution occurs.

Furthermore, if an attempt is made to form a deep element isolation region, the width will be similarly wide (C), and the waste of the element surface will become large.

The present invention has been made in view of the above-mentioned conventional problems.
The purpose is to provide a method for manufacturing a semiconductor device that can realize complete element isolation, have a low resistance value in the element isolation region, and make effective use of the element surface.

[Summary of the invention]

A method for manufacturing a semiconductor device according to the present invention includes a method for manufacturing a semiconductor device in which each element formed in a semiconductor layer of one conductivity type is electrically isolated by an element isolation region of a semiconductor of an opposite conductivity type. a first step of forming a groove of a desired depth at a position in the layer where an element isolation region is to be formed; a second step of forming a polycrystalline semiconductor of an opposite conductivity type in the groove;
The element isolation region is formed by the following steps.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a manufacturing process diagram of an embodiment of the method for manufacturing a semiconductor device according to the present invention.

First, as shown in FIG. 1(a), the impurity concentration I
On the back surface of the NFI silicon substrate 1 with an impurity concentration of I
The n+ layer 2 for the Omitsuko/Tact of X1020 Tan-3 is formed by diffusion of P, As, or sb. Subsequently, an oxide film 3 (for example, a 5to2 film) having a thickness of 3000 to 7000× is formed on the n+ layer by the method (3).

The oxide film 3 is called a back coat and is used to prevent impurity vapor from being generated when the substrate 1 is heat treated.

Next, the surface of the substrate 10 was heated to a temperature of 1000°C and 2 HcA.
1/min, N2 at 60 J/mln.
After etching for 5 minutes, source gas 5ta2cz2
(100chi) to 1.21/mkn, dosing fs(
N2 dilution P)13.

20PPM) was flowed at 100CC, and the growth temperature was 1000℃.

An n-1 pitaxial layer 4 (hereinafter referred to as n-layer 4) is formed under a reduced pressure of 120 to 180 Torr. At this time, the single crystal growth rate was 0.5 μm/mm, the thickness was 2-10 μm1, and the impurity concentration was I x 1012 ~
1016 saw-3, preferably 10-10 tan [
Figure 1(b)].

In order to improve the quality of the n'''' layer 4, the substrate is first treated at a high temperature of about 1,150 to 1,250°C to remove oxygen from the vicinity of the surface, and then heat-treated for a long time at about 800°C to remove the inside of the substrate. causes many micro-defects,
It is also very effective to use a substrate that can perform intrinsic bittering with denudetzo.

Subsequently, an oxide film 5 with a thickness of 8,000 to 12,000 mm is formed on the n-layer 4 by pyrogenation, oxidation (N2+02), wet oxidation (02+N20), or steam oxidation (N2).
2 + N20). Furthermore, high-pressure oxidation at a temperature of 800 to 1000° C. is suitable for obtaining a good oxide film free of stacking defects and the like.

Then, in order to form an element isolation region, a part of the oxide film 5 is selectively removed by photolithography.
Figure 1 (C)].

Next, using the oxide film 5 as a mask, selective etching is performed using the n'''' layer 4IB (reactive ion etching apparatus) to form a groove G for forming an element isolation region (see Fig. 1). (d)] This etching type gas [is SF6 or tiCF+ + 02 or sp6 +
Mourning using CCl4.

Once the grooves G are formed, cleaning is performed using a combination of strong acid such as heptonic acid and ultrasonic cleaning to remove impurities and residues generated during the etching process using RIB and to clean the surface. In addition, good results were obtained when the drying process used a commonly used dryer using a rinser dryer and a drying method that combined Lang heating.

Subsequently, the groove GKf! is formed using the low pressure CVD method. Embed Syricon 6 [Figure 1 (・)].

The deposition conditions for polysilicon 6 are a temperature of 560 to 700°C;
Deposition rate: 40-12017 m1n, pressure: 0, 2-1.
0 Torr, seed gas amount (sta4zoo*) is 20
~200087m111.

After embedding the polysilicon 6 in this manner, zolon is diffused into the polysilicon as a p-type impurity.

First, a wafer-shaped ronitride (hereinafter referred to as BN) was placed in a diffusion furnace facing the wafer shown in FIG.
A heat treatment is performed at 0° C. to deposit glass containing impurity B on the polysilicon.

Subsequently, heat treatment is performed at 1050 to 1150° C. for 2 to 6 hours in an N2 atmosphere to push the attached impurity B into the polysilicon layer. At that time, impurity diffusion into polysilicon is n
Since the 11'' layer 4 is covered with the oxide film 5, the zolon diffusion in the n'' layer 4 is substantially caused by the polysilicon in the groove G. It is carried out only in Hereinafter, the p-polysilicon diffused in the groove G will be used as the element isolation region 6.

Next, RIE using gas 8F4+02t- was performed.

Depacking (a method of etching from the convex portion) is performed to sequentially etch the polysilicon and oxide film 5 on the surface and flatten it [FIG. 1(f)].

Note that the step of forming the element isolation region 6 is shown in FIG.
s) Can you put K? If polysilicon containing impurities is deposited by mixing a gas such as B2H6 (digerane) when depositing resilin, the zolon diffusion step can be omitted.

After the element isolation region 6 of plJ is formed in this way, 7. Partial surface cleaning is performed using chemicals such as acids.

Next, a space region for the bipolar transistor is formed.

First, a buffer oxide film 7 is formed on the surface, and a resist 8 is applied thereon to pattern a region to become a base [FIG. 1(g)].

The oxide film is provided to prevent channeling and surface defects when forming the pace region by ion implantation, and has a thickness of 500 to 1500×.

Subsequently, B+ ions or BF2 ions generated using BF3 as a material gas are implanted into the wafer. At this time, the resist 8 is used as a mask, and B+ ions are implanted only in the areas where the resist 8 is removed. This surface concentration is 1×10
~5 X 10 tyn% preferably 1~20X
10 cm thick, ion implantation amount is 7×10~1
×10, preferably IX1012 to lXl0
cm.

After the ions are implanted in this manner, the resist 8 is removed and heat treatment is performed at 1000 to 1100° C. in an N2 atmosphere. Through this heat treatment, the implanted ions are electrically activated, crystal defects are removed, and a p region 9 (hereinafter referred to as base region 9) serving as a base is formed. Furthermore, a pace region 9 is formed by pyrogenation and oxidation (H2+ 02 ) by diffusion to a predetermined depth, and an oxide film 1O is formed [FIG. 1(h)].

The depth of the pace region 9 is, for example, about 0.6 to 1 μm.

The thickness and impurity concentration of the pace region 9 are determined based on the following considerations. In order to increase the sensitivity, it is desirable to lower the impurity concentration in the pace region 9 to reduce the base-emitter capacitance Cbe. Cbe is given approximately as follows.

However, vbt is the ivy-to-pace diffusion potential, which is given by: Here, C is the dielectric constant of silicon crystal, N
D is the impurity concentration of the emitter, N is the impurity density n1 of the base adjacent to the emitter, and is the intrinsic carrier concentration As.
is the area of the pace region, and is k? Lutmann constant, T is temperature,
q is a unit charge amount. As Nmu becomes smaller, Cbe becomes smaller and the sensitivity increases, but if Nmu is made too small, the pace region will be completely depleted in the operating state and a punching-through state will occur, so the sensitivity will be low. I can't.

The pace region is set to such an extent that it does not become completely depleted (4 inches through).

Note that as a method of forming the pace region 9, there is also a method of depositing BSG on a wafer and diffusing impurity B to a predetermined depth by thermal diffusion at 1100 to 1200°C.

After the element isolation region 6 and the space region 9 are formed in this manner, the oxide film 10 is selectively removed, and oxide films 11 and 12 with a thickness of several tens to hundreds of layers are formed thereon (see FIG. 1).
i)]. Here, HCt (100-200 al, /
Good results were obtained by oxidizing with (02+ HCt + N2) gas containing (min).

Note that instead of the oxide films 11 and 12, a nitride film (5i3N4) using a reduced pressure method may be used. The dielectric constant of the nitride film is approximately twice that of 8102, and a large capacitor capacity can be obtained. Further, the oxide film (5to2 film) has the advantage that the interface between 81 and 8102 is stable, and thermal stress and interface states are small.

When oxide films 11 and 12 are formed, p+ ions are
Implant 10-1×10 cm ions.

This ion implantation is performed to determine the threshold voltage vth when the p-channel MO8 transistor formed between the pace region 9 and the element isolation region 6 performs a switching operation. In this example, the threshold voltage is 0.5 to 2
It was set to v.

Subsequently, a portion of the oxide film 11 is removed using photolithography in order to form an emitter, an electrode, and an emitter region. And (N2 + SiH4 + AlR1
1) or (He + 81H4+ AsH3) or (H
a +81H4+ PH,) ; Using gas, CVD
As or P dope polysilicon is deposited by a method. The deposition temperature at this time is about 550°C to 900°C, and the thickness is 2000 to 7000X. Of course, non-doped polysilicon is deposited by the method, and then As
Alternatively, P may be diffused.

Then, the deposited silicon film is removed by etching after a mask alignment photolithography process to form polycrystalline silicon 13 and 14 [FIG. 1(j)]. However, the etching of the deposited polysilicon is C2CL2F4
a (CBrF3 + C22) or other gas system.

Subsequently, a complete heat treatment is performed to diffuse the impurity (Am) from the polysilicon 13 into the base region 9, forming an n+ emitter region 15 (FIG. 1(k)).

Next, a 5io2 film 16 with a thickness of 3000 to 7000X is deposited by the above-mentioned gas-based method, and then a contact hole is formed on the υ polysilicon 14 by a mask alignment process and an etching process. Electrode 1 is inserted into this contact hole.
7 (metal such as At, At-81, At-Cu-81, etc.) is deposited by vacuum evaporation or sputtering [
Figure 1 (4).

Subsequently, a glabellar insulating film 18 such as a PSG film or a 5102 film is deposited to a thickness of 3000 to 6000× by CVD.

Then, through mask alignment, machining, and chiming processes, /
A contact hole is made on the silicon 13 and the electrode 19 is
(Metals such as At, At-81, At-Cu-81, etc.)
[Figure 1 (e)].

Finally, a carbon film 20 (PSG film or 815N4 film, etc.) is formed by the CVD method, and an electrode 21 (metal such as HT, HT-SL, Au, etc.) is formed on the back surface of the wafer to complete the process. Figure 1 (→).

Note that in this embodiment, the depth of the groove G is equal to n'''' layer 4, but is not limited to this, and
A depth that can separate the depletion layer that spreads between elements is sufficient.

Figure 2 is a plan view of a photoelectric conversion device in which the optical sensor cells shown in Figure 1 (,) are arranged two-dimensionally.
-B' line cross section corresponds to FIG. 1 (, ).

Next, the configuration and operation of the photoelectric conversion device manufactured according to this example will be explained with reference to FIGS. 1(,) and 2.

In both figures, an n'''' layer 4 is formed on a TL type silicon substrate 1, and a photosensor cell is formed in the n'''' layer 4, which is electrically insulated from each other by an element isolation region 6.

Each optical sensor cell includes a p space region 9 of a bipolar transistor on an n layer 4, an n+ emitter region 15, an oxide film 1
0, a capacitor COX for applying a pulse to the dirt of the p-MOS) transistor and the p-space area 9.
I-resilicon 14 for electrodes, which also serves as an electrode for ? It consists of polysilicon/13 for the electrode connected to the emitter region 15, an electrode 19 connected to the polysilicon 13, an electrode 17 connected to the polysilicon 14, etc.
There is.

The basic operation of the optical sensor cell having such a configuration will be explained below.

First, the charge storage operation is performed after applying a reverse bias potential to the n+ emitter to the p space region 9 and the reverse bias potential to the ri region 15. The potential of the silicon 14 is maintained at a positive potential higher than the threshold voltage of the p-MOS transistor, the p-MOS transistor is turned off, and holes generated by light are accumulated in the p-space region 9.

The potential of the p-pace region 9 changes in the positive direction due to the accumulation of holes, but the potential of the p-pace region 9 of each sensor cell differs depending on the intensity of light.

In this state, a positive read pulse voltage vR is applied from electrode 17 to polysilicon 14 . Since the voltage V, is positive, the p-MOS transistor remains off.

When the read pulse voltage vR is applied to the polysilicon 14, the p base region 9 becomes forward biased with respect to the n+ emitter region 15. Electrons are injected into the p-pace region 9 from the irradiation region 15, and the n+ emitter region 1
The potential of 5 gradually changes in the positive potential direction. That is, p
The information accumulated in the base area 9 is read out to the rear side.

After a read pulse voltage V is applied for a certain period of time, when the polysilicon 14 is brought to the ground potential, the p pace region 9 becomes reverse biased with respect to the n+ emitter region 15,
The potential change in the n+ emitter region 15 stops.

In this state, information on the emitter and rear sides is read out through polysilicon 13 and electrode 19.

When this readout is completed, the electrode 19 is grounded and the ? Emitter region 15 is at ground potential. However, in this state, a potential corresponding to the intensity of light, that is, optical information, remains accumulated in p base region 9, and therefore, it is necessary to remove this optical information.

Therefore, p −
A negative Noculus voltage VILH exceeding the threshold voltage Vth of the MOS transistor is applied. This allows p-
'The MOS transistor is in a conductive state, the holes accumulated in the p-space region 9 are removed, and the potential of the p-space region 9 is fixed at the predetermined negative voltage applied to the element isolation region 6.

This refresh operation brings the p-pace area 9 into a complete initial state, and thereafter the above-described storage, read, and refresh operations are repeated.

In this way, during reading, a positive pulse is applied to the polysilicon 14, and during refreshing, a negative pulse is applied to turn on the p-MOS transistor, so that the above operations do not interfere. By the way, when strong light hits a part of the photoelectric conversion device in which photosensor cells are arranged as shown in FIG. A directional bias state occurs, and a signal is read out to the left, right, and left sides, and a pluming phenomenon occurs.

In order to prevent this, during the storage operation, the potential of the /17 silicon 14 is set to 1c, p- with the potential of the p base region 9 approaching zero potential, that is, before the signal is read out on the emitter side. It is also possible to set the MOS transistor to be conductive.

By setting the potential of polysilicon 14 in this way,
Before the p base region 9 and the n+ emitter region 15 are put into a forward bias state, the p-MOS transistor becomes conductive (), excess charge flows to the element isolation region 6 side, and the pluming phenomenon is prevented.

FIG. 3 is a circuit diagram of this embodiment. However, although the case where the number of pixels is 2X2=4 will be taken as an example here, a circuit with an arbitrary number of pixels nXn can be easily constructed from the circuit shown in the figure.

In the figure, each optical sensor cell Ell~E2! has the configuration shown in FIGS. 1(,) and 2.

That is, a capacitor COx 302 is formed by the p-space region 9 of the bipolar transistor 301 and the polysilicon 14 facing each other with the oxide film 10 in between.
Base region 9, element isolation region 6, and pre-silicon 1
4, a p-MOS transistor 303 is formed. In this embodiment, the polysilicon 14 serves as one electrode of the capacitor C0X302 and the dirt of the p-MOS transistor 303, but in the conventional example (FIG. 4)
It can also be configured separately like this.

Each electrode 17 of the photosensor cells F'll and E12 is a switching transistor (hereinafter referred to as SWT) 304
is connected to the first parallel output terminal of shift register A through SWT 305 and to terminal T3 through SWT 305.

Each electrode 17 of the optical sensor cell) 11 and E22 is SW
T 306 to the second parallel output terminal of shift register A, and SWT 307 to terminal T
Connected to 3.

Further, each dart terminal of SWTs 304 and 306 is connected to terminal T1, and each dart terminal of SWTs 305 and 307(7) is connected to terminal T2.

The emitter electrode 19 of each bipolar transistor 301 of the optical sensor cells Elf and E21 is connected to the output terminal via a 5WT 308, and further grounded via a 5WT 309.

Each emitter electrode 19 of the optical sensor cell gtz and E2m
is connected to the output terminal via the 5WT 310 and further grounded via the SWT 311.

In addition, each dart terminal of SWT 308 and 310 is
They are connected to the first and second parallel output terminals of shift register B, respectively, and the dart terminals of 5WTs 309 and 311 are connected to terminal T4.

A predetermined negative voltage vBB is applied to the source region of the p-MOS transistor 303 of each photosensor cell, that is, the element isolation region 6, and a predetermined positive voltage VCC is applied to the collector voltage 21 of the bipolar transistor 301 of each sensor cell. has been done.

Further, a voltage is applied to each terminal T1 to T4 at a predetermined timing to turn on the corresponding SWT.

Shift pulses are input to shift registers A and B at predetermined timing, and a high level (positive voltage VB) is sequentially output from each parallel output terminal.

The operation of the circuit of this embodiment having such a configuration will be briefly described.

First, 5WT304.306.308, set 310
in the off state, 5WT305.307.309° and 3
11 is turned on, and a negative voltage pulse for refreshing is applied to the terminal T3. As a result, all optical sensor cells Ell""E2! A refresh operation is performed.

Next, turn 5WT305 and 307 off,
Performs charge accumulation operation. This allows each p pace area 9
The optical information at that location is accumulated.

Next, SWT 309 and 311 are turned off, SFr
304 and 306 are turned on, and the stored information is sequentially read out.

First, by setting the first parallel output terminal of shift register A to high level, optical sensor cells "11" and "E12"
A positive voltage vR is applied to each electrode 17, and the information stored in the p pace region 9 is read out to the emitter side. Subsequently, the first and second parallel output terminals of shift register B are sequentially set to high level, and the 5WT 308 and the SWT 31
0 are turned on one after another. By this operation, the information accumulated in the optical sensor cells Ell and E12 is sequentially output to the outside.

Next, by setting the second parallel output terminal of shift register A to a high level and operating shift register B as described above, the information accumulated in optical sensor cells E21 and E2jl is sequentially output to the outside in the same way. .

When the reading is completed in this way, the above-mentioned refresh operation is performed, and thereafter the storage, read, and refresh operations are repeated.

〔Effect of the invention〕

As described above in detail, the method for manufacturing a semiconductor device according to the present invention suppresses the lateral expansion of the element isolation region, so that the width can be reduced, and the element isolation region with a desired depth can be easily formed. be able to. Therefore, since the elements can be reliably separated and the element surface can be used effectively, the elements can be made smaller.

Furthermore, when applied to the manufacture of a photoelectric conversion device having a pace region that needs to be returned to a predetermined potential at the time of refreshing, it is possible to obtain a photoelectric conversion device that can refresh and operate quickly and reliably with a simple configuration. I can do it.

In addition, miniaturization of each optical sensor cell, that is, higher resolution,
Moreover, high sensitivity can be achieved.

Although the manufacturing method according to the present invention is described in Japanese Patent Application No. 58-120755 as an example of a conventional photoelectric conversion device, it is clear that it is applicable to other photoelectric conversion devices. .

[Brief explanation of the drawing]

1(&) to (n) are manufacturing process diagrams of an embodiment of the method for manufacturing a semiconductor device according to the present invention; FIG. 2 is a plan view of a photoelectric conversion device manufactured according to this embodiment; The figure is a circuit diagram of the photoelectric conversion device, FIG. 4(a) is a plan view of a conventional photoelectric conversion device, and FIG.
b) is a sectional view taken along the line A-A'. 1... Substrate, 4... Epitaxial layer, 6... Element isolation region, 9... Space region, lO... Oxide film,
13゜14...Polysilicon (for electrode), 15...
Emi, Ri area. Agent Patent Attorney Minoru Yamashita Figure 1 (a) Figure 1 (b) Figure 1 (C) Figure 1 (d) Figure 1 (h) Figure 1 (1) Figure 1 (j) Figure 1 (k) Figure 1 (1) Figure 1 (n) Figure 2 Figure 3 Figure 4 (0)

Claims (3)

[Claims] (1) In a method for manufacturing a semiconductor device in which each element formed in a semiconductor layer of one conductivity type is electrically isolated by an element isolation region of a semiconductor of an opposite conductivity type, forming an element isolation region in the semiconductor layer of one conductivity type. A semiconductor device characterized in that the element isolation region is formed by: a first step of forming a groove with a desired depth at a desired position; and a second step of forming a polycrystalline semiconductor of an opposite conductivity type in the groove. manufacturing method. (2) The second step is characterized in that a polycrystalline semiconductor is buried in the groove and an impurity of an opposite conductivity type is diffused into the buried polycrystalline semiconductor.
A method for manufacturing a semiconductor device according to section 1. (3) The method of manufacturing a semiconductor device according to claim 1, wherein in the second step, an impurity of an opposite conductivity type is mixed when burying the polycrystalline semiconductor in the groove.