JPS5919370A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5919370A
JPS5919370A JP57128540A JP12854082A JPS5919370A JP S5919370 A JPS5919370 A JP S5919370A JP 57128540 A JP57128540 A JP 57128540A JP 12854082 A JP12854082 A JP 12854082A JP S5919370 A JPS5919370 A JP S5919370A
Authority
JP
Japan
Prior art keywords
film
substrate
voltage
region
optical information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57128540A
Other languages
Japanese (ja)
Inventor
Yasuteru Ichida
市田 安照
Hidemasa Mizutani
英正 水谷
Nobuyoshi Tanaka
田中 信義
Takao Kinoshita
貴雄 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP57128540A priority Critical patent/JPS5919370A/en
Publication of JPS5919370A publication Critical patent/JPS5919370A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/1443Devices controlled by radiation with at least one potential jump or surface barrier

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To nondestructively read out optical information by associating a P-N junction formed on a silicon substrate for detecting the information and a transistor formed on an insulating film which covers the surface of the substrate. CONSTITUTION:When the voltage of a substrate 1 is raised from a negative voltage to a positive voltage, a depletion layer is expanded between P type regions 11a, 11b of floating state and the substrate 1. When a light is incident via windows 3a, 3b, electron-hole pairs are generated, the holes flow to the region 11a, and the electrons flow to the substrate 1. Accordingly, a metal film 6 which is electrically connected to the regions 11a, 11b to form the gate of a transistor becomes positive voltage. Then, the surface potential of the silicon film under the metal film is varied by the voltage of the film 6, and when the prescribed voltage is applied to source, drain 4, 5, the current in response to the voltage of the film 6 is flowed, and the optical information can be nondestructively read out.

Description

【発明の詳細な説明】 本発明は光電変換素子を含む半導体装置の改良に係わる
。従来固体デバイスによるイメージセンサ−はCCD型
、 MOS型の2種類が存在する。CCD型では、光情
報はMOSキャパシタ電極下の半導体領域に生じたポテ
ンシャル井戸の中に蓄積され、読み出しは蓄積された電
荷がCCDシフトレジスタによって転送される事によっ
て行われる。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvement of a semiconductor device including a photoelectric conversion element. Conventionally, there are two types of image sensors using solid-state devices: CCD type and MOS type. In the CCD type, optical information is accumulated in a potential well generated in a semiconductor region under a MOS capacitor electrode, and readout is performed by transferring the accumulated charge by a CCD shift register.

一方、MOS型においては、元情報はホトダイオードに
蓄積され、読み出しはマトリックス状に配列されたMO
Sトランジスタをスイッチングする事によって行われる
On the other hand, in the MOS type, the original information is stored in a photodiode, and the readout is performed by the MOS array arranged in a matrix.
This is done by switching the S transistor.

これらのいずれの場合もそれまでに蓄積されていた光情
報は、読み出しによって破壊されてしまう。
In any of these cases, the optical information that has been stored up to that point is destroyed by reading.

光情報を非破壊に読み出す方法として例えば、フォトト
ランジスタとスイッチングトランジスタを組み合わせた
半導体装置が提案されているが、かかる構造はシリコン
基板の中に数回にわたって不純物濃度の異なるP領域あ
るいはN領域を作り込む必要があり、結晶欠陥などを極
力少なくする必要があり、且つ基本素子を小さくする必
要のあるイメージセンサ−用の固体デバイスとしては好
適とはいえない。
For example, a semiconductor device combining a phototransistor and a switching transistor has been proposed as a method for non-destructively reading optical information, but such a structure involves creating P or N regions with different impurity concentrations several times in a silicon substrate. It is not suitable for use as a solid-state device for an image sensor, which requires a large number of crystals, a need to minimize crystal defects, and a need to reduce the size of the basic element.

本発明は、この様な従来技術の欠点を解消し得る、而も
例えば光情報を非破壊に読み出すことが可能であって構
造的にも簡単な、固体撮像装置を提供する事を目的とし
たものであり、その為に本発明の実施例によれば例えば
、シリコン基板内に形成された光情報検出用のPN接合
とシリコン基板表面を被覆する、例えば8i02膜など
の絶縁膜上に形也 成されたトランジスタとを組み合わ桜ている。 。
An object of the present invention is to provide a solid-state imaging device that can eliminate the drawbacks of the prior art, and that is also capable of non-destructively reading out optical information and has a simple structure. Therefore, according to the embodiment of the present invention, for example, a shape is formed on a PN junction for detecting optical information formed in a silicon substrate and an insulating film such as an 8i02 film that covers the surface of the silicon substrate. It is a cherry blossom combination with a transistor that has been made. .

第1図(a)〜(d)は、本発明の1つの実施例を示す
図であり、光情報を検出する為にシリコン基板の中に形
成したPN接合を用い、蓄積された光情報を読み出す為
に8i02膜上に堆積させたシリコン膜上に作られたM
OS −FBTを用いたものである。このシリコン膜は
必要に応じてブリッジングφエピタキシー、グラフオ・
エピタキシー等の技術を用いて結晶化されている。以下
各部分を説明する。
FIGS. 1(a) to 1(d) are diagrams showing one embodiment of the present invention, in which a PN junction formed in a silicon substrate is used to detect optical information, and accumulated optical information is detected. M fabricated on silicon film deposited on 8i02 film for readout
This uses OS-FBT. This silicon film is coated with bridging φ epitaxy, graphite
It is crystallized using techniques such as epitaxy. Each part will be explained below.

1は例えばNuシリコン基体であり、2は表面を被覆す
る例えばS io2膜である。3a、3bは光を入射さ
せる窓である。
1 is, for example, a Nu silicon substrate, and 2 is, for example, a Sio2 film covering the surface. 3a and 3b are windows through which light enters.

窓の下はP属領域であり、基体1との間にPN接合を形
成している。領域3a、3bの部分は例えば、所定の部
分のS i02膜をエツチングによって取り除いた後に
、例えばボロンを熱拡散法あるいはイオン打ち込み法に
よって導入する事によって形成する事が可能である。
Below the window is a P region, which forms a PN junction with the substrate 1. The regions 3a and 3b can be formed, for example, by removing a predetermined portion of the Si02 film by etching and then introducing boron, for example, by thermal diffusion or ion implantation.

4.5.6はS iOz膜上に堆積させられたシリコン
膜に形成されたMOS−PETの各部分を示す。即ち6
はゲート部分を形成する例えばAIなどの金属膜である
。4と5の領域はソース会ドレインとなり、例えばN型
領域である。金属膜乙の下のポリOシリコン膜はP属領
域である。第1図falをη−P′方向に切断した断面
図を第1図(C)に示す。金属膜6はS i02膜9を
介してシリコン膜のP領域100表固型位を制御する。
4.5.6 shows parts of a MOS-PET formed in a silicon film deposited on a SiOz film. That is 6
is a metal film such as AI that forms the gate portion. Regions 4 and 5 become source/drain regions, and are, for example, N-type regions. The polyO silicon film under the metal film B is a P region. FIG. 1(C) is a cross-sectional view of FIG. 1 fal taken in the η-P' direction. The metal film 6 controls the solid state of the P region 100 of the silicon film via the Si02 film 9.

第1図(1))は第1図(a)を八−へ′方向に切断し
た断面図を示す。(b)図に示したように金属膜6は、
シリコン基体1の中に形成されたP1領域11 a 、
11bと電気的につながっている。
FIG. 1(1)) shows a sectional view of FIG. 1(a) taken in the 8-' direction. (b) As shown in the figure, the metal film 6 is
P1 region 11a formed in silicon substrate 1,
11b.

第1図(a)の7,8はソース・ドレインの金属配線用
コンタクトである12はシリコン基体1の電位を制御し
、且つリフレッシュを行う電気配線端子を意味する。
In FIG. 1(a), 7 and 8 are source/drain metal wiring contacts, and 12 is an electrical wiring terminal for controlling the potential of the silicon substrate 1 and refreshing it.

第1図(d)は第1図(a)の等価回路図である。FIG. 1(d) is an equivalent circuit diagram of FIG. 1(a).

尚Ju上の構成において、NとPu入れ替えても同様な
機能を有する事は勿論である。
Note that in the configuration on Ju, it goes without saying that even if N and Pu are replaced, the same function can be obtained.

次に動作を説明する。Next, the operation will be explained.

基体1の電位を例えば、負電圧例えば−1■から急激に
正電位例えば+5■に上げると、フローティング状態に
あるP領域11a、11bは基体1との間で逆バイアス
状態になり、P領域11a。
When the potential of the substrate 1 is suddenly raised from a negative voltage, for example, -1■ to a positive potential, for example, +5■, the P regions 11a and 11b in the floating state become reverse biased with the substrate 1, and the P region 11a .

11bと基体1の間には空乏層が広がる。A depletion layer spreads between 11b and the substrate 1.

窓3a、3bより光が入射すると電子−正孔対が発生し
電子は基体1の方へ、正孔はP領域11a。
When light enters through the windows 3a and 3b, electron-hole pairs are generated, the electrons are directed toward the substrate 1, and the holes are directed toward the P region 11a.

11bの方に流れる。したがってP領域6は蓄積された
正孔の量に応じた正電位となる。
11b. Therefore, P region 6 has a positive potential depending on the amount of accumulated holes.

P領域11a、11bと電気的に結合された金属膜6も
当然正電位になる。
Naturally, the metal film 6 electrically coupled to the P regions 11a and 11b also has a positive potential.

金属膜乙の電圧によって金属膜下のシリコン膜の表面ポ
テンシャルが変化し、ソース参ドレイン4゜5に所定の
電圧を印加すれば、金属膜6の電圧に応じた電流が流れ
元情報が非破壊に読み出される。
The surface potential of the silicon film under the metal film changes depending on the voltage of the metal film B, and if a predetermined voltage is applied to the source-drain 4°5, a current according to the voltage of the metal film 6 flows, and the source information is not destroyed. is read out.

尚フローティング状態KP領域1ia、11bをリフレ
ッシュするには基体1の電位を負電位にすればよい。
Incidentally, in order to refresh the floating state KP regions 1ia and 11b, the potential of the substrate 1 may be set to a negative potential.

第2図(al〜(d)は、本発明の他の実施例である。Figures 2 (al to d) show other embodiments of the present invention.

各部分を説明する。Explain each part.

13はN型シリコン基体であり、14は表面を被覆する
8i02膜である。15a、15bは光を入射させる為
の窓である。
13 is an N-type silicon substrate, and 14 is an 8i02 film covering the surface. 15a and 15b are windows for allowing light to enter.

第2図山)は第2図(a)を八−N方向に切断した断面
構造を示す。一方、第2図(C)は第2図(a)をバー
μ′方向に切断した断面構造を示す。第2図(d)は第
2図(a)の等価回路図である。
2(a) shows a cross-sectional structure obtained by cutting FIG. 2(a) in the 8-N direction. On the other hand, FIG. 2(C) shows a cross-sectional structure obtained by cutting FIG. 2(a) in the bar μ' direction. FIG. 2(d) is an equivalent circuit diagram of FIG. 2(a).

第2図(b)に示すように窓15a、15bの下のシリ
コン基体はP型不純物が導入されており、P型頭域21
となっている。
As shown in FIG. 2(b), P-type impurities are introduced into the silicon substrate under the windows 15a and 15b, and the P-type head region 21
It becomes.

1(S、17.18は5i02膜上に堆積させられたシ
リコン膜の各部分を示す。この例では16.18はN型
領域となっており、17はP属領域となっている。
1(S, 17.18 indicates each part of the silicon film deposited on the 5i02 film. In this example, 16.18 is an N-type region, and 17 is a P-type region.

シリコン膜のP型頭域17は、第2図(b)に示したよ
うに酸化膜22を介して、シリコン基体中のP領域21
と容量的に結合されている。
The P-type head region 17 of the silicon film is connected to the P region 21 in the silicon substrate via the oxide film 22, as shown in FIG. 2(b).
and are capacitively coupled.

すなわちP領域21の電位によって、シリコン膜のP領
域17の表面電位が変化する。
That is, depending on the potential of P region 21, the surface potential of P region 17 of the silicon film changes.

換言すれば16,17.18及び22.21によってM
OS −FETが形成されていることになる。
In other words, M by 16, 17.18 and 22.21
This means that an OS-FET is formed.

16.18はソース・ドレインであり、19.20はそ
の金属端子をあられす。
16.18 is the source/drain, and 19.20 is the metal terminal thereof.

端子26はシリコン基体の電位を制御する為のものであ
る。
The terminal 26 is for controlling the potential of the silicon substrate.

動作はおおむね第1図に示した例と同じであるが、シリ
コン基体中のP領域21の電位によって、シリコン膜の
P領域の表面電位が直接S i02膜22を介して変化
させられる点が異なる。
The operation is roughly the same as the example shown in FIG. 1, except that the surface potential of the P region of the silicon film is changed directly via the Si02 film 22 depending on the potential of the P region 21 in the silicon substrate. .

以上説明した如く本発明の撮像装置によれば、(1)光
電変換部と増巾部とを同一基板に形成しようとした場合
構造が簡単である。
As explained above, according to the imaging device of the present invention, (1) the structure is simple when the photoelectric conversion section and the widening section are formed on the same substrate.

(2)リフレッシュも容易である。(2) Refreshing is also easy.

(3) 5i02膜上に形成されたシリコン膜の質が多
少悪くても、元情報によって変化するP領域の電位が読
み出し用MO8−FIBTのゲートに入力される為K、
リークなどKより光情報が損なわれることがない。
(3) Even if the quality of the silicon film formed on the 5i02 film is somewhat poor, the potential of the P region, which changes depending on the original information, is input to the gate of the read MO8-FIBT, so K,
Compared to K, optical information is less likely to be damaged due to leaks.

(4)而も読み出し用MO8−FETがシリコン基体と
S i02膜によって分離されている為に、読み出し用
MO8@FETのソース彎ドレインに印加する電圧に自
由度がある。
(4) Since the readout MO8-FET is separated from the silicon substrate by the Si02 film, there is a degree of freedom in the voltage applied to the source and drain of the readout MO8@FET.

(5)更罠平面型である為に微細化に適する。(5) It is suitable for miniaturization because it is a flat planar type.

(6)非破壊読み出しが可能となる。(6) Non-destructive reading becomes possible.

(ハ微細化しても容量もそれに伴って低下するので、光
感度が低下することがない、 等多くの効果をもたらすものである。
(C) Even with miniaturization, the capacitance also decreases, so the photosensitivity does not decrease.

第3図は本発明に係る半導体装置を適用した固体撮像装
置の一例を示す図であって、X−Yアドレスタイプのイ
メージセンサを構成しており、60゜61は夫々X位置
、Y位置選択用レジスタ、62゜66は夫々レジスタ3
0.31により選択的に駆動される読み出し用(4)S
スイッチ、34は出力アンプ、35は本発明の半導体装
置である。読み出し用MOSスイッチ32.33は、各
々シフトレジスタ30.31によって走査され、光情報
がソース拳フォローの形でアンプ64から出力される。
FIG. 3 is a diagram showing an example of a solid-state imaging device to which the semiconductor device according to the present invention is applied, and constitutes an X-Y address type image sensor, where 60° and 61 are X-position and Y-position selection points, respectively. registers, 62° and 66 are register 3 respectively.
(4)S for reading selectively driven by 0.31
34 is an output amplifier, and 35 is a semiconductor device of the present invention. The readout MOS switches 32 and 33 are each scanned by a shift register 30 and 31, and optical information is outputted from the amplifier 64 in the form of a source follow.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al〜(d)は本発明の半導体装置の第1の実
施例を示す図で、同図(a)は斜視図、同図(b)は同
図(alのA −A’断、面図、同図(c)は同図(a
)のB −B’断面図、同図(d)は等何回路である。 第2図(a)〜(d)は本発明の半導体装置の第2の実
施    −例を示す図で、同図(a)は斜視図、同図
(b)は同図(a)のA −A’断面図、同図(C)は
同図(alのB −B’断面図、同図(dlは尋価回路
である。 第3図は本発明の半導体装置を適用した撮像装置の一例
を示す図である。 1・・・半導体基板、2・・中絶縁膜、3a、3bs・
・・光入射窓、61」ゲート、4 、5 ++ +1 
@ソース(ドレイン)。 特許出願人 キャノン株式会社
1(al) to (d) are diagrams showing a first embodiment of the semiconductor device of the present invention, in which FIG. 1(a) is a perspective view and FIG. 1(b) is a Cross section, side view, the same figure (c) is the same figure (a
) is a cross-sectional view taken along line B-B' of (d) of the same figure. FIGS. 2(a) to 2(d) are diagrams showing a second embodiment of the semiconductor device of the present invention, in which FIG. 2(a) is a perspective view and FIG. 2(b) is an A of FIG. -A' sectional view, the same figure (C) is a B-B' sectional view of the same figure (al), the same figure (dl is a circuit). It is a figure showing an example. 1... Semiconductor substrate, 2... Middle insulating film, 3a, 3bs.
...Light entrance window, 61'' gate, 4, 5 ++ +1
@Source (Drain). Patent applicant Canon Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板内に形成した光電変換部と、前記基板表面を
被覆する絶縁膜上に形成した増中部とから成る半導体装
置。
A semiconductor device comprising a photoelectric conversion section formed within a semiconductor substrate, and an enhancement section formed on an insulating film covering the surface of the substrate.
JP57128540A 1982-07-23 1982-07-23 Semiconductor device Pending JPS5919370A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57128540A JPS5919370A (en) 1982-07-23 1982-07-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57128540A JPS5919370A (en) 1982-07-23 1982-07-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5919370A true JPS5919370A (en) 1984-01-31

Family

ID=14987278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57128540A Pending JPS5919370A (en) 1982-07-23 1982-07-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5919370A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198858A (en) * 1984-03-23 1985-10-08 Mitsubishi Electric Corp Solid-state image-pickup element

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56162875A (en) * 1980-05-19 1981-12-15 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS56162886A (en) * 1980-05-20 1981-12-15 Matsushita Electric Ind Co Ltd Solid state image pickup device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56162875A (en) * 1980-05-19 1981-12-15 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS56162886A (en) * 1980-05-20 1981-12-15 Matsushita Electric Ind Co Ltd Solid state image pickup device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198858A (en) * 1984-03-23 1985-10-08 Mitsubishi Electric Corp Solid-state image-pickup element

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