JPH0650771B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

The present invention relates to a solid-state image pickup device and a method for manufacturing the same, and the solid-state image pickup device according to the present invention has high sensitivity, low noise, and a small size, and is a home movie camera. Can be applied to TV cameras for broadcasting, and video cameras for astronomical observation that utilize its high sensitivity.

[Conventional technology]

Among conventional solid-state image pickup devices, the SIT type image sensor is mainly configured by using an n ⁺ substrate.

[Problems to be solved by the invention]

In a solid-state imaging device configured by arranging vertical electrostatic induction transistors (hereinafter referred to as SITs) in an array, each pixel is separated even though it has features such as high sensitivity, low noise, high speed, and high integration. It wasn't enough. Furthermore, the read circuit of the solid-state image pickup device is different from the SIT in M
It takes a very long process to form the readout circuit on the same substrate by using the OS transistor.

[Means for solving problems]

The SIT that constitutes each pixel is surrounded by an n ⁺ separation region for pixel-to-pixel separation, and by manufacturing an n-channel SIT on a p substrate, sensitivity to long-wavelength light that generates carriers deep in the substrate is obtained. Can be lowered.

The inventor has invented a process of forming a portion of the read circuit which can be commonly formed in the same process as the SIT by using a common mask.

[Action]

By separating the SIT forming each pixel by n ^{+, the} separation between pixels becomes sufficient, and higher integration can be achieved. By cutting off the sensitivity to long-wavelength light, phenomena such as blooming can be suppressed.

By performing the SIT and the MOS transistor at the same time, the number of masking steps can be reduced to 15 times.

〔Example〕

FIG. 1 is a schematic cross-sectional view of a SIT for one pixel which constitutes an embodiment of the solid-state image pickup device of the present invention, and a MOS transistor which constitutes a readout circuit of a photodetection section formed by the SIT
It is one schematic sectional drawing.

In the SIT of FIG. 1, SI is formed on the p-type semiconductor substrate 1.
It becomes the drain or source of T. Common to all SITs
An n ⁺ buried layer 2 is formed, and an n ⁻ type epitaxial layer 6 having a low impurity density is further formed thereon,
The n ^- type epitaxial layer 6 than the n ⁺ region 5 toward the n ⁺ region 5 serving as a drain or source p ⁺ gate region 4 between p ⁺ gate region 4 and p ⁺ gate region 4 in the surface portion It is formed to be deep. Here, the vertical structure SIT of the present invention can be operated by using either the n ⁺ region 5 or the n ⁺ buried layer 2 as a source, which is determined by the difference in the reading method.

Further, the SITs constituting one pixel are separated by the n ⁺ separation region 3. p ^{2 +} SiO ₂ on the gate region 4
The polysilicon gate electrode 4'isolated by
It is formed so as to form a capacitance with the p ⁺ gate region 4. The n ⁺ region 5 is electroded by the polysilicon electrode 5 ′, and Al is formed on a part of the polysilicon 5 ′.
An electrode 5 ″ is formed.

The n ⁺ isolation region 3 is connected to the n ⁺ buried layer 2 and a part of the n ⁺ isolation region 3 has an electrode 3 ″ formed of Al. The above is the light detection of the solid-state imaging device of the present invention. This is a structural feature of the SIT that constitutes one pixel of the part.

The first figure, further made by SIT simultaneously process described above, although there is shown one schematic cross-sectional view of a MOS transistor constituting a reading circuit, which is a normal MOS transistor, n ^- -type A p-well region 7 is formed on the epitaxial layer 6 so that its lower surface is in contact with the p-type substrate 1, and n ⁺ regions 9 and 10 serving as a source or a drain therein and a gate oxide film on the upper surface of the p well. SiO ₂ 12 is formed with a polysilicon gate 13 and the like serving as an insulating gate on the SiO ₂ 12.

An Al electrode 1 ″ is formed on the entire surface of the p-type semiconductor substrate 1 so that the n ⁺ buried layer 2 can be biased.

A MOS transistor manufactured on the p-type semiconductor substrate shown in FIG. 1 and having an n ⁺ separated SIT as one pixel, and a readout circuit of a photodetection section formed of the SIT on the same substrate as the photodetection section. The semi-solid-state image pickup device constituted by can be obtained by the embodiment of the manufacturing method of the present invention described below with reference to FIG.

First, a p-type (100) Si1 substrate having a specific resistance of 4 to 6 Ω · cm is prepared. SiO ₂ 16 with a film thickness of about 2000 Å is formed by wet oxidation, and As is used as a mask with SiO ₂ 16 through the masking process of n ⁺ buried layer, As is at an impurity dose amount of 1 × 10 ¹⁶ cm ^-2 and an acceleration voltage of 80 keV Ion implantation (Fig. 2 (a)), annealing and n ⁺
The buried layer 2 is formed, but the thermal diffusion depth of As is thinner than the desired n ⁺ buried layer in consideration of the subsequent steps.
The SiO ₂ on the surface is removed by etching, and further SiO ₂ 18 with a film thickness of about 600 Å is formed by wet oxidation (Fig. 2).
(b)). Before n ^- type epitaxial layer 6 is grown, its n
^In order to prevent p inversion of the -type epitaxial layer 6 from the p substrate due to autodoping, the p we of the MOS transistor is
11 except for the top surface of the area where
Using as a mask, P is ion-implanted through SiO ₂ 18 with an impurity dose amount of 5 × 10 ¹¹ cm ^-2 and an acceleration voltage of 100 keV (Fig. 2).
(c)), and an n-type layer 20 is formed by annealing. Further, the surface is oxidized and the thickness of SiO ₂ 18 is set to about 1500Å. At this time, the back surface is provided with polysilicon 21 for protection, for example, L
It is formed by the PCVD method or the like (FIG. 2 (d)).

Next, the SiO ₂ 18 on the surface is completely removed by etching,
An n ⁻ type epitaxial layer 6 having a low impurity density of about 5 to 6 μm is formed. The thickness of the n ⁻ type epitaxial layer 6 is determined in consideration of the electrical characteristics and the spectral sensitivity characteristics of the SIT that serves as a photodetector (FIG. 2 (e)).

The polysilicon 21 on the back surface is removed by etching. p well
By the mask process of the mask, B (boron) is doped at an impurity dose of 2 × 10 ¹³ cm ^-2 through the SiO ₂ 23 having a thickness of about 600 Å with the resist 22 covering the portion other than p well as the mask.
Ions are implanted at an accelerating voltage of 0 keV (Fig. 2 (f)) and annealed to form p well 7, but in consideration of the subsequent steps, B
The thermal diffusion depth of is less than the desired p well 7. Furthermore, the film thickness of SiO ₂ 23 is set to about 5000Å by wet oxidation. Next, by the mask process of the n ⁺ separation mask,
Si with the upper surface of the part to be the n ⁺ isolation region removed by etching
Using O ₂ 23 as a mask, P is deposited and P is diffused by a thermal diffusion method to form an n ⁺ isolation region 3. However, the thermal diffusion depth of P is a desired n ⁺ isolation region in consideration of the subsequent steps. It is shallower than 3 (Fig. 2 (g)).

PSC24, after a SiO ₂ 23 is removed by etching, the film thickness 600Å
SiO ₂ 26 is formed to a certain extent, and a resist 28 and Si ₃ N ₄ 27 are removed from the surface of the p ⁺ channel stopper region 9 of the MOS transistor through a mask process to remove the upper surface of the p ⁺ channel stopper region 9. As a mask, B is ion-implanted with an impurity dose amount of 5 × 10 ¹³ cm ⁻² and an acceleration voltage of 100 keV. Si ₃ N ₄ is formed by, for example, the CVD method (FIG. 2 (h)).

Si ₃ N ₄ 27 is removed by plasma etching except where a MOS transistor is formed through a mask process (FIG. 2 (i)).

SiO ₂ 29 is formed by LOCOS using Si ₃ N ₄ 27 as a mask, Si ₃ N ₄ 27 is removed by plasma etching, and a p ⁺ gate 4 and an n ⁺ drain or source 5 of SIT are formed through a mask process. The SiO ₂ on the upper surface of the region is removed by etching. Further, by the LOCOS and the subsequent annealing, the n ⁺ isolation region 3, p well 7 and p ⁺ channel stopper region 9 are formed to a desired depth by thermal diffusion. (Fig. 2 (j)).

SiO ₂ having a thickness of about 600 Å is formed by wet oxidation on the portion of SiO ₂ 29 (the upper surface of each of the p ⁺ and n ⁺ drain or source regions of SIT) which has been removed by etching. Next, Al is vapor-deposited on the entire surface, and is removed by etching through a mask process except the MOS transistor region and the upper surface 31 of each region serving as the n ⁺ drain or source of the SIT.

Using Al 31 and SiO ₂ 29 as a mask, B is an impurity dose amount of 5
Ions are implanted at an acceleration voltage of 50 keV at × 10 ¹⁵ cm ^-2 , Al 31 is removed by etching, and then annealing is performed to form a p ⁺ gate 4 of SIT with a depth of about 3 μm. The interval and the depth of the p ⁺ gate 4 are one of the things that most determine the characteristics of the SIT, and they are determined in advance so as to be the optimum SIT as a photodetector (FIG. 2 (k)).

SiO ₂ 30 is removed by slight etching (Fig. 2)
(l)).

The oxide film 4 on the p ⁺ gate 4 of the SIT and the gate oxide film 12 of the MOS transistor are formed.
This is a SiO ₂ film with a thickness of about 700 Å obtained by oxidizing in an atmosphere of O ₂ + HCl at ℃ for about 13 minutes (Fig. 2).
(m)).

Next, channel doping is performed by ion implantation through a mask process depending on whether the MOS transistor is of depletion type or enhancement type.

FIG. 2 (m) shows the case of forming a depletion type MOS transistor which becomes a load transistor of the E / D MOS inverter. At this time, P is ion-implanted with an impurity dose amount of 2.0 × 10 ¹² cm ⁻² and an acceleration voltage of 120 keV. When the enhancement type is used, B is ion-implanted at an acceleration voltage of 60 keV with an impurity dose amount, for example.

After the mask process, using the resist 34 as a mask, the SIT
A contact hole for taking the electrode of the n ⁺ drain or source 5 and a contact hole for taking the electrode of the MOS transistor are formed by removing SiO ₂ by etching (FIG. 2 (n)).

P-doped n-type polysilicon (DOPOS) is used as C
Formed on the surface by the VD method, the polysilicon electrode 4'on the p ⁺ gate 4 of the SIT, the polysilicon electrode 5'of the drain or source of the SIT, the polysilicon electrode 13 of the MOS transistor, the drain electrode 10 'of the MOS transistor, and Although not shown in the figure, except for polysilicon used as wiring, DOPOS is removed by plasma etching using a resist as a mask through a mask process (FIG. 2 (o)).

Using SiO ₂ 14 and DOPOS as a mask, P is ion-implanted through SiO ₂ 12 with an impurity dose amount of 3 × 10 ¹⁵ cm ^-2 at an acceleration voltage of 110 keV, and PSG is formed to a thickness of about 4000 Å by CVD, and then annealed to form MOS transistors N ⁺ source 9 and n ⁺ drain 10 of the SIT n ⁺
The drain or source 5 is formed to a depth of about 1 μm (second
(Figure (p)).

A contact hole is formed to form the Al electrode, but 2
It is formed by etching PSG and SiO ₂ in this order through a masking process (FIG. 2 (q)).

SiO ₂ on the back surface is removed by etching, Al is deposited on the front surface and the back surface, and unnecessary Al is removed by etching through a mask process (FIG. 2 (r)).

As described above, the manufacturing method of the present invention described with reference to FIG.
N-channel SIT that becomes a photodetector on the substrate
With a manufacturing method suitable for simultaneously manufacturing the n-channel MOS transistors forming the read circuit on the same semiconductor substrate, the number of masks to be used can be as small as 15.
In particular, by introducing a step of preventing p inversion of the n ⁻ type epitaxial layer in the step of FIG. 2 (c), a good n ⁻ type epitaxial layer can be formed, and the steps of FIG. 2 (j) to (r) At S
The step of forming the IT gate and drain or source by self-alignment can be performed so that the distance between the gate and drain or source is constant.

Next, S which is a photodetector that constitutes the solid-state imaging device of the present invention
The operation of the solid-state imaging device of the present invention will be briefly described with reference to the IT matrix configuration method, the photodetection section readout method, and circuit example.

FIG. 3 (a) shows the configuration of the solid-state image pickup device of the present invention and a readout circuit, and FIG. 3 (b) shows a timing chart of readout pulses.

The SIT50 which is the photodetector according to the present invention shown in FIG.
The source is the n ⁺ buried layer 2 and the n ⁺ region 5 provided on the surface of the n ⁻ epitaxial layer 6 is the drain.
At 80, the drain is connected to the horizontal output line 81. Third
When the transfer MOS transistor 53 is in the ON state by φ _T according to the pulse timing in the figure (b), φ _P
Causes the horizontal output line 81 to be charged to a certain potential (determined by the operating point of SIT) by the precharge power supply 57, and then connected to one of the vertical address lines 80 by applying a pulse φG to the vertical address line. One row of SITs is that electrons generated from the source flowing through the channel are stored in the p ⁺ gate because holes generated in the depletion layer in the channel due to the light incident on the SIT for a certain period are accumulated in the p ⁺ gate. Is a normally-off type SIT in which the current due to is not large enough to be detected, and when a pulse of φ _G is applied, the change in the gate potential due to the holes generated by the pulse through the capacitor 51 corresponding to the amount of incident light. In addition, a discharge corresponding to the amount of incident light is generated. At this time, the holes accumulated in the p ⁺ gate are exposed to the source and the gate is refreshed.

By turning off the transfer MOS transistor 53 at the fall of φ _G , the discharge charge amount of SIT is stored in the transfer capacitor 55 as the discharge amount of the transfer capacitor 55. The phi _S comprising pulses from the horizontal shift register is generated by the timing of FIG. 3 (b), the phi _S by light information transfer capacitor which has been stored in the transfer capacitors 55 by sequentially ON state switching MOS transistor 54 By charging 55 of the video power supply 58, electric signals are sequentially output to the output terminal 60. After that, the vertical address lines are sequentially selected.

Precharge MOS transistor 52, transfer M
The MO transistor in which the OS transistor 53, the switch MOS transistor 54, the vertical shift register 70, and the horizontal shift register 71 are formed on the same substrate as the SIT by the simultaneous process.
It is made up of S-transistors.

Although the output can be increased by enlarging the transfer capacitor 55, this transfer capacitor uses the p ⁺ region 9 in the p well 7 of the MOS transistor to form an insulating polysilicon gate on the p ⁺ gate of the SIT. It can be made larger by manufacturing capacitors in exactly the same process.

The vertical shift register 70 and the horizontal shift register 71 can be configured by, for example, a shift register using an E / D MOS inverter and a super buffer.

FIG. 3 (c) shows a configuration of the solid-state imaging device of the present invention and an example of a read circuit, and FIG. 3 (d) shows a timing chart of the read pulse.

In this read example, the SIT50, which is the photodetector according to the present invention shown in FIG. 1, operates upright. That is, the n ⁺ buried layer 2 is used as a drain, and the n ⁺ region 5 provided on the surface of the n ⁻ epitaxial layer 6 is used as a source. Therefore, the drains are common, the gate is connected to the vertical address line 80, and the source is connected to the horizontal output line 81.

Vertical address line 8 according to the pulse timing in Fig. 3 (d)
When one of 0 is selected by a pulse of φ _G, the SIT connected to the vertical address line 80 is SIT for a certain period.
Holes generated in the depletion layer in the channel due to the light incident on IT are accumulated in the p ⁺ gate and the potential of the gate is lowered, but the current due to electrons from the source flowing in the channel is not large enough to be detected. When a pulse of φ _G is applied in such a normally-off type SIT, the pulse adds to the change in the gate potential due to the holes generated corresponding to the amount of incident light, and discharges according to the amount of incident light. Each potential of the horizontal output line 81 is determined. Within the high level period of φ _G , the horizontal shift register 71
Switch M by generating phi _S comprising pulses from a
By sequentially turning on the OS transistor 54, the optical information incident on the SIT on the vertical address line can be taken out to the output terminal 60 as an electric signal. After the end of the horizontal address, the φ _G pulse is set to a certain refresh level at the same time as the φ _R pulse, and the refresh MOS transistor 52 ′ is turned on by the φ _R pulse for refreshing the SIT and the horizontal output line. And do it at the same time. After that, the vertical address lines are sequentially selected.

MOS transistors 52 'and 54, vertical shift register 7
0, the horizontal shift register 71 is SI
It is similar to the example of the reading method described above in that it is composed of a MOS transistor formed on the same substrate as T.

[Effects of the Invention] The SIT that constitutes the SIT image pickup device of the present invention is on a p substrate
The n ⁺ buried layer is used as one of the main electrodes of the SIT, and the sensitivity of long-wavelength light that penetrates deep into the substrate to generate carriers is cut, and the sensitivity of short-wavelength light is relatively increased. In other words, the holes generated inside the p substrate are SI
It does not diffuse to the p ⁺ gate of T and does not become an effective carrier accumulated in the gate of SIT.

4 and 5 show drawings for explaining the effect of the present invention.

FIG. 4 is a graph showing an example of comparison of the spectral sensitivities of the SIT image pickup device of the present invention and the conventional SIT image pickup device formed on the n ⁺ substrate. It can be seen that the peak of the wavelength sensitivity is around 720 nm in the conventional SIT image pickup device, while it shifts to a short wavelength of 670 nm in the present invention. Furthermore, the sensitivity for long-wavelength light of 700 nm or more is kept low, and the sensitivity for short-wavelength of 600 nm or less is high.

FIG. 5 shows an example of photoelectric conversion characteristics of the present invention. Fig. 3
In the photoelectric conversion example by the reading method according to (c), three examples of prototype devices are shown. Optical integration time 11 msec, input wavelength λ = 655 nm, optical gain 10 ⁴ to 10
^It can be seen that the sensitivity is very high as ⁵ .

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an SIT and a MOS transistor, FIG. 2 is a schematic sectional view for explaining a simultaneous process of the SIT and a MOS transistor, and FIG. 3 is an explanatory view of the operation of the solid-state imaging device of the present invention. 4 and 5 are drawings for explaining the effect of the present invention, showing the spectral sensitivity characteristic and the photoelectric conversion characteristic, respectively. 1 ... p-type Si substrate, 2 ... n ⁺ buried layer, 3 ... n ⁺ isolation region, 4 ... SIT p ⁺ gate, 4 '... SIT p ⁺
Insulated polysilicon electrode of gate 4, 4 ... p ^{+ of} SIT
Oxide film of MOS capacitor on the gate, 5 ... of SIT
n ⁺ drain or source, 5 '...... SIT of n ⁺ drain or polysilicon electrode of the source 5, 6 ...... low impurity concentration n ^-
Area, 7 …… p well, 8 …… p ⁺ channel stopper,
9, 10 ... n ⁺ drain or source of MOS transistor, 10 '... polysilicon electrode of n ⁺ drain or source 10 of MOS transistor, 11 ... channel of MOS transistor, 12 ... gate oxide film of MOS transistor, 13: Polysilicon gate of MOS transistor,
14 …… field oxide film, 20 …… p inversion prevention n layer, 25…
… N ⁺ separation, 29 …… field SiO ₂ , 50 …… SIT, 51…
... MOS capacitor, 52 ... precharge MOS transistor, 52 '... refresh MOS transistor, 53
...... Transfer MOS transistor, 54 …… Switch MOS transistor, 70 …… Vertical shift register, 71
...... Horizontal shift register

Claims (3)

[Claims] 1. A solid-state imaging device using a vertical electrostatic induction transistor as a photodetector for one pixel, wherein the vertical electrostatic induction transistor has a low impurity density first layer and the first layer. At least one formed on the surface of the first layer of a silicon wafer composed of a second layer of different conductivity type and high impurity density
First main electrode region, a gate region formed so as to sandwich the first main electrode region, and a gate region and a capacitor are formed on at least a part of an upper surface of the gate region by being insulated by a first insulator. A first insulated gate region provided so that the second main electrode is
A third layer provided in a part between the first layer and the second layer so as to face the first main electrode having a conductivity type different from that of the second layer, and Enclosing the vertical static induction transistor in an isolation region that is of the same conductivity type as the third layer and is formed in contact with the third layer,
A solid-state imaging device, characterized in that the solid-state imaging device is separated from the adjacent vertical electrostatic induction transistor and is also a part of a main electrode together with the second main electrode. 2. A vertical type static induction transistor as a photodetector for one pixel, and a MOS transistor for scanning the photodetector and a shift register for generating a scanning pulse for reading. In the solid-state imaging device having a read circuit as a read circuit, the vertical electrostatic induction transistor includes a first layer having a low impurity density and a second layer having a high impurity density having a conductivity type different from that of the first layer. At least one first main electrode region formed on the surface of the first layer of a silicon wafer, a gate region formed so as to sandwich the first main electrode region, and at least a part thereof on the upper surface of the gate region A first insulated gate region insulated by a first insulator and provided to form a capacitor with the gate region, and a second main electrode having the first layer and the first layer. A third layer provided in a part between the second layer and the first main electrode having a conductivity type different from that of the second layer, and having the same conductivity as the third layer. The vertical electrostatic induction transistor is surrounded by an isolation region formed in contact with the third layer in the mold to separate the vertical electrostatic induction transistor from the adjacent vertical electrostatic induction transistor, and a main region is formed together with the second main electrode. The MOS transistor is a part of an electrode, and the MOS transistor includes a well formed in the first layer in contact with the second layer, and a third well formed on an upper surface of the well. A second electrode provided with a main electrode region and a fourth main electrode region, and provided on a surface between the third main electrode region and the fourth main electrode region and insulated from the second insulator. A solid-state imaging device comprising an insulated gate region. 3. A method of manufacturing a solid-state imaging device, wherein a vertical electrostatic induction transistor and a MOS transistor are simultaneously formed on a silicon substrate, wherein (i) a region to be a third layer on the silicon substrate to be a second layer. And forming a first layer epitaxially on the second layer so as to sandwich the third layer. (Ii) The M from the upper surface of the first layer in the first layer.
After sequentially performing a first impurity doping for forming a well of an OS transistor, a second impurity doping for forming an isolation region, and a third impurity doping for forming a channel stopper of the MOS transistor, Forming the well region, the isolation region, and the channel stopper region by heat treatment. (Iii) A field oxide film is formed by LOCOS on the upper surface of the first layer other than the portion where the MOS transistor is formed, and the gate region and the first main electrode region of the vertical static induction transistor are self-aligned. A step of simultaneously etching away the upper surface portion of the gate region of the field oxide film and the upper surface portion of the second main electrode region of the field oxide film to be formed. (Iv) After forming the gate region of the vertical static induction transistor, a second oxide film of the MOS transistor is formed on the gate region of the vertical static induction transistor to form a first capacitor. Formed at the same time as the oxide film,
Channel doping the MOS transistor. (V) a first insulated gate region for forming the capacitor and the gate region of the vertical electrostatic induction transistor, a first electrode region of the first main electrode, and the MO.
A step of simultaneously forming DOPOS as the second insulated gate region of the S transistor, the second electrode region of the third main electrode, and the third electrode region of the fourth main electrode. (Vi) A step of simultaneously forming the first main electrode region of the vertical static induction transistor and the third main electrode and the fourth main electrode of the MOS transistor. A method for manufacturing a solid-state imaging device, comprising: