JPH0455346B2 - - Google Patents
Info
- Publication number
- JPH0455346B2 JPH0455346B2 JP58234236A JP23423683A JPH0455346B2 JP H0455346 B2 JPH0455346 B2 JP H0455346B2 JP 58234236 A JP58234236 A JP 58234236A JP 23423683 A JP23423683 A JP 23423683A JP H0455346 B2 JPH0455346 B2 JP H0455346B2
- Authority
- JP
- Japan
- Prior art keywords
- impurity region
- solid
- state imaging
- imaging device
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 26
- 239000012535 impurity Substances 0.000 claims description 22
- 238000003384 imaging method Methods 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 8
- 239000010408 film Substances 0.000 description 17
- 230000000694 effects Effects 0.000 description 13
- 238000002955 isolation Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 206010034972 Photosensitivity reaction Diseases 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000036211 photosensitivity Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 239000003779 heat-resistant material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14654—Blooming suppression
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】
本発明は固体撮像装置（以下センサと略す）の
光擬似信号防止などの高性能化に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the performance of solid-state imaging devices (hereinafter abbreviated as sensors), such as preventing optical false signals.
第１図は従来から知られているMOS形センサ
の基本的な回路構成を示したものである。同図に
おいて、１は水平走査回路、２は垂直走査回路、
３はホトダイオード（受光素子）、４はホトゲー
ト、５は垂直信号線、６は水平スイツチ、７は水
平信号線、８はホトゲートの電極配線、９はセン
サの出力端子である。この素子の動作原理につい
てはすでに多くの解説がなされているのでここで
はふれない（たとえば泉田他“固体カメラ信号読
み出し回路の検討”昭和54年TV学会全国大会予
稿集２−10、p47−48などを参照されたい）。 FIG. 1 shows the basic circuit configuration of a conventionally known MOS type sensor. In the figure, 1 is a horizontal scanning circuit, 2 is a vertical scanning circuit,
3 is a photodiode (light receiving element), 4 is a photogate, 5 is a vertical signal line, 6 is a horizontal switch, 7 is a horizontal signal line, 8 is an electrode wiring of the photogate, and 9 is an output terminal of the sensor. Many explanations have already been given regarding the operating principle of this element, so I will not discuss it here (for example, Izumida et al., "Study of Solid-State Camera Signal Readout Circuit," Proceedings of the 1974 Television Society National Conference, 2-10, p. 47-48). Please refer to ).
さて第１図に示したようなMOS形センサでは
強い光が照射されたときに発生する擬似信号（ブ
ルーミング現象）や、ホトダイオードではなく直
接信号線近傍へ光信号が入射したようなときに発
生する擬似信号（以下簡単のために信号線の感光
と呼ぶ）を抑圧することが実用上極めて重要であ
る。 Now, with the MOS type sensor shown in Figure 1, a false signal (blooming phenomenon) occurs when strong light is irradiated, or when an optical signal enters directly near the signal line instead of the photodiode. Suppressing spurious signals (hereinafter referred to as signal line photosensitivity for simplicity) is extremely important in practice.
第２図は従来のセンサの受光部の断面図の１例
であつて、２１はｐ形Si基板、２２はホトダイオ
ードとなるn+層の不純物領域、２３は信号読み
出しドレインとなるn+層の不純物領域、２４は
フイールドアイソレーシヨン用p+層、２５は絶
縁層、２７はホトゲート、２８は垂直信号線とな
る配線である。 FIG. 2 is an example of a cross-sectional view of a light-receiving part of a conventional sensor, in which 21 is a p-type Si substrate, 22 is an impurity region of an n + layer that becomes a photodiode, and 23 is an impurity region of an n + layer that becomes a signal readout drain. 24 is an impurity region, 24 is a p + layer for field isolation, 25 is an insulating layer, 27 is a photogate, and 28 is a wiring serving as a vertical signal line.
第２図を用いて前記光擬似信号発生のメカニズ
ムを説明する。ホトダイオード２２に強い光が３
０のように入射すると、ダイオード２２は順方向
になつて、ラテラルバイポーラ効果でキヤリア３
１のようにドレイン側へ流れ出して擬似信号とな
る。これがブルーミング現象の主原因である。 The mechanism of optical pseudo signal generation will be explained using FIG. 2. Strong light 3 hits the photodiode 22
0, the diode 22 goes in the forward direction and becomes the carrier 3 due to the lateral bipolar effect.
1, it flows to the drain side and becomes a pseudo signal. This is the main cause of the blooming phenomenon.
一方３３のように基板深くで発生したキヤリア
の一部や、３２のようにホトダイオード以外の部
分から入射した光によるキヤリア３４の一部など
は直接ドレイン２３に流入し、やはり光擬似信号
になる。これが前記信号線の感光である。 On the other hand, a portion of carriers generated deep in the substrate as shown in 33, and a portion of carriers 34 due to light incident from a portion other than the photodiode as shown in 32, flow directly into the drain 23 and become optical pseudo signals. This is the exposure of the signal line.
本発明の目的は、上記問題点を解決した新しい
MOS形センサを提供することにある。 The object of the present invention is to create a new system that solves the above problems.
Our goal is to provide MOS type sensors.
第３図に本発明の１実施例を示す。第３図はセ
ンサの受光部の構造を示すものであつて１００は
ｎ形Si基板、１０１はｐ形Si基体、１０２はホト
ダイオードとなるn+層の不純物領域、１０３は
酸化膜、１０４はパツシベーシヨンのためのりん
ガラス、１０５は配線、１０６は素子の保護膜、
１０７はフイールド酸化膜、１０８はフイールド
アイソレーシヨンのためのp+層、１１０は信号
読み出しドレイン用のn+領域の不純物領域、１
１１はホトゲートである。 FIG. 3 shows one embodiment of the present invention. FIG. 3 shows the structure of the light-receiving part of the sensor, in which 100 is an n-type Si substrate, 101 is a p-type Si substrate, 102 is an impurity region of the n + layer which becomes a photodiode, 103 is an oxide film, and 104 is a passivation layer. 105 is the wiring, 106 is the protective film for the element,
107 is a field oxide film, 108 is a p + layer for field isolation, 110 is an impurity region of an n + region for a signal readout drain, 1
11 is a photogate.
第３図においてホトダイオード１０２は不純物
りんの拡散で形成されたn+層であり、ドレイン
１１０は不純物Asを用いたn+層である。りんの
拡散層は、センサに重要な短波長感度が高く、ホ
トダイオードに適しており、Asを用いたn+層は、
Ｐ形Si基体１０１との間に浅い接合を作り易く、
浅い接合でも低い層抵抗が得られるので、読み出
しドレインや周辺回路のMOSトランジスタのソ
ースおよびドレインに適している。 In FIG. 3, the photodiode 102 is an n + layer formed by diffusion of impurity phosphorus, and the drain 110 is an n + layer using impurity As. Phosphorous diffusion layers have high short wavelength sensitivity, which is important for sensors, and are suitable for photodiodes, and n + layers using As,
It is easy to create a shallow bond with the P-type Si substrate 101,
Low layer resistance can be obtained even with shallow junctions, making it suitable for read drains and sources and drains of MOS transistors in peripheral circuits.
さて第３図に示したドレイン１１０は、ｐ形基
体１０１の上部に形成されているので、第２図の
構造と比較すれば明らかなように、ラテラル・バ
イボーラ効果によるキヤリアがドレインに流入す
る確率は非常に低くなる。またｐ形基体１０１の
内部で発生したキヤリアも、ドレインに達する距
離が長くなるので、ドレインに流入する、確率は
下がる。第３図ではp+形層１１２がｐ形基体１
０１の表面に形成されているが、これは、これに
よつて上記擬似信号キヤリアに対するポテンシア
ル障壁を形成して擬似信号キヤリアを１０９のよ
うに防止するためのものであつて、その障壁を＞〜
3kT程度にすると、前記の効果と相乗して、ブル
ーミングや信号線の感光の抑圧効果は極めて大き
い。 Now, since the drain 110 shown in FIG. 3 is formed on the upper part of the p-type substrate 101, as is clear from the comparison with the structure shown in FIG. 2, there is a probability that carriers due to the lateral bibolar effect will flow into the drain. becomes very low. Furthermore, carriers generated inside the p-type substrate 101 have a longer distance to reach the drain, so the probability that they will flow into the drain decreases. In FIG. 3, the p + type layer 112 is the p type substrate 1.
This is formed on the surface of 01 to form a potential barrier against the above-mentioned false signal carrier and prevent the false signal carrier as shown in 109.
When the voltage is set to about 3 kT, the effect of suppressing blooming and photosensitivity of the signal line is extremely large, in combination with the above-mentioned effect.
第３図で、ドレイン１１０は基体１０１に接す
る面積が小さいので、集積密度が高く、また上記
擬似信号の混入も防止し易い。他方、その構造上
基体１０１より上部において基体に接する面積よ
り広く形成されているので、配線１０５とのコン
タクト部１１４は十分な広さがとれることは明ら
かである。 In FIG. 3, since the drain 110 has a small area in contact with the base 101, the integration density is high and it is easy to prevent the above-mentioned spurious signals from being mixed in. On the other hand, since the area above the base 101 is larger than the area in contact with the base due to its structure, it is clear that the contact portion 114 with the wiring 105 can have a sufficient width.
またドレイン部はフイールドアイソレーシヨン
のp+層と接する面積が非常に小さくなるので、
信号線１０５に付く寄生容量を小さくできる。 Also, since the area of the drain part in contact with the p + layer of the field isolation is very small,
The parasitic capacitance attached to the signal line 105 can be reduced.
第３図ではｎ基板を用いてn+−ｐ−ｎ層構造
とし、光擬似信号を基板側へ吸収するようにし
て、防止効果を高めているが、単にｐ基板を用い
てn+−ｐ層構造としても本発明の効果は得られ
る。 In Figure 3, an n + -p-n layer structure is created using an n-substrate to absorb optical pseudo signals to the substrate side, increasing the prevention effect . The effects of the present invention can also be obtained with a layered structure.
第３図に示した構造は、自己整合的に形成で
き、また製造上も作り易い特徴を有している。 The structure shown in FIG. 3 can be formed in a self-aligned manner and has the characteristics of being easy to manufacture.
第４図は、第３図に示した構造を自己整合的に
形成する、製造方法を示したものである。 FIG. 4 shows a manufacturing method for forming the structure shown in FIG. 3 in a self-aligned manner.
第４図ａは、ｎ形Si基板４０の上にｐ形Si基体
４１を形成し、従来技術によりフイールドSiO2
４２、アイソレーシヨンp+層４３、ゲート酸化
膜４４Polysiゲート電極４５を形成し、低温配化
により選択的に保護膜４６を形成した後、ゲート
電極の周囲を残して能動領域をエツチングにより
露出させた状態を示す。これにさらに多結晶Si４
７とSi3N4４８を形成する（同図ｂ）。 In FIG. 4a, a p-type Si substrate 41 is formed on an n-type Si substrate 40, and a field SiO 2
42. After forming an isolation p + layer 43, a gate oxide film 44, and a polysi gate electrode 45, and selectively forming a protective film 46 by low-temperature deposition, the active region is exposed by etching, leaving the area around the gate electrode. Indicates the condition. In addition to this, polycrystalline Si4
7 to form Si 3 N 4 48 (FIG. b).
通常のホトエツチング法で、コンタクト形成部
にSi3N4を残し５０、Si3N4でおおわれていない
多結晶Si５１を、りんの拡散によつてn+化する。
このときSi3N4の下には拡散層は形成されない。
（同図ｃ）
これを熱酸化すると、Si3N4のない部分５１は
酸化されない厚い酸化膜５２となり、同時にn+
化された多結晶Si層からりんが基板側へ拡散し
て、n+層５３が形成される。このときSi3N4の下
は以前のままの多結晶Si層である。（同図ｄ。）
Si3N4を除去し、ここにヒ素（As）を拡散やイ
オン打込みなどしてn+層５５を形成し、りんガ
ラス５７を形成した後、通常のホトエツチングで
コンタクト穴５６を形成し、Alなどの導電物質
で配線６０を形成する。（同図ｅ。）
第４図ｅに示した構造で明らかなように、本製
法によるセンサの受光部はその製法故に次のよう
な特徴を有する。 By the usual photo-etching method, Si 3 N 4 is left in the contact formation portion 50, and the polycrystalline Si 51 not covered with Si 3 N 4 is changed to n + by diffusion of phosphorus.
At this time, no diffusion layer is formed under the Si 3 N 4 .
(Figure c) When this is thermally oxidized, the part 51 without Si 3 N 4 becomes a thick oxide film 52 that is not oxidized, and at the same time
Phosphorus diffuses from the polycrystalline Si layer toward the substrate, forming an n + layer 53. At this time, under the Si 3 N 4 is the polycrystalline Si layer as before. (D in the same figure) After removing Si 3 N 4 and forming an n + layer 55 by diffusing arsenic (As) or implanting ions, and forming a phosphor glass 57, a contact hole is formed by normal photoetching. 56 is formed, and a wiring 60 is formed using a conductive material such as Al. (Fig. 4e) As is clear from the structure shown in Fig. 4e, the light receiving section of the sensor manufactured by this method has the following characteristics due to its manufacturing method.
(1) 多結晶Siの酸化による厚いSiO2膜５２を有
する。(1) It has a thick SiO 2 film 52 formed by oxidizing polycrystalline Si.
(2) コンタクト領域５６がゲート４５の上に形成
されたため、ゲート４５と配線６０のシヨート
の懸念がなくなつて、サイドエツチによるコン
タクト穴の広がりを問題としないので、りんガ
ラス５７の膜厚を厚くできる。(2) Since the contact region 56 is formed on the gate 45, there is no need to worry about shorting between the gate 45 and the wiring 60, and the widening of the contact hole due to side etching is not a problem, so the thickness of the phosphor glass 57 can be increased. can.
(3) 厚い酸化膜、基体上部のAsをドープしたド
レイン、りん拡散によるホトダイオードなどが
自己整合的に形成できる。(3) A thick oxide film, an As-doped drain on the top of the substrate, and a photodiode by phosphorus diffusion can be formed in a self-aligned manner.
上記(1)、(2)より本発明によるセンサの垂直信号
線の寄生容量Cvは従来に比べ極めて小さくでき
ることは明らかである。 From (1) and (2) above, it is clear that the parasitic capacitance Cv of the vertical signal line of the sensor according to the present invention can be made extremely smaller than that of the conventional sensor.
またセンサの周辺回路に用いるMOSトランジ
スタは、ソース、ドレイン共に読み出しドレイン
５５の構造を用いることができるので、ソースド
レインの接合深さが実効的に小さくシヨートチヤ
ネル効果の少ないMOSFETの集積回路とするこ
とができる。 In addition, since the MOS transistor used in the peripheral circuit of the sensor can use the structure of the readout drain 55 for both the source and drain, it is possible to create a MOSFET integrated circuit with an effective small source-drain junction depth and little short channel effect. can.
ここで第４図ａにおいて、フイールドSiO2４
２はSiO2でなく、他の絶縁物であつてもよく、
また構造上もLOCOS構造でなく、プレーナ構造
で、アイソレーシヨンp+層がそれに応じて変わ
つた構造のものであつても、本発明の効果に変わ
りはない。 Here, in FIG. 4a, the field SiO 2 4
2 may be other insulators instead of SiO2 ,
Further, even if the structure is not a LOCOS structure but a planar structure, and the isolation p + layer is changed accordingly, the effects of the present invention will not change.
センサにおいては、暗電流低減などの理由から
基板に接するSi層は、できるだけ単結晶である方
が良い。本発明になる製造方法において、多結晶
Si４７形成後（第４図ｂ）ないし、コンタクト部
形成後（第３図ｄでSi3N4除去後で、ドーピング
の前後）に、レーザー光によりアニーリングを
し、単結晶化することは、本発明の効果に支障が
ないばかりか、逆にセンサとして秀れた特性を有
するものとするに効果が大きい。 In sensors, it is preferable that the Si layer in contact with the substrate be as single crystal as possible for reasons such as reducing dark current. In the production method of the present invention, polycrystalline
After forming Si47 (Fig. 4b) or after forming the contact part (after removing Si 3 N 4 in Fig. 3d, before and after doping), it is not proper to perform annealing with laser light to form a single crystal. Not only does it not impede the effects of the invention, but it is also very effective in providing excellent characteristics as a sensor.
同様に第４図ｂにおいて、多結晶Si４７は、エ
ピタキシアル成長によつて形成すると、Si基板と
接する部分には多結晶ではなく単結晶が形成され
るので、基板とよく整合のとれた素子が得られ、
本発明の効果に変わりはない。またこれをレーザ
ーアニールと組合わせても良い。 Similarly, in FIG. 4b, when polycrystalline Si 47 is formed by epitaxial growth, a single crystal is formed instead of a polycrystal in the part in contact with the Si substrate, so that an element that is well matched with the substrate is formed. obtained,
There is no change in the effects of the present invention. Further, this may be combined with laser annealing.
また第４図ｂ，ｃ，ｄで示したSi3N4は、これ
に限らず、Si層５１を選択酸化するときの高温酸
化雰囲気に耐えるものであれば、他の薄膜であつ
てもよい。ホトゲートになる電極４５も、導電性
で耐熱性のある物質ならば、多結晶Si、Mo膜な
どどのような物質であつてもよい。 Furthermore, the Si 3 N 4 shown in FIG. 4 b, c, and d is not limited to this, and may be any other thin film as long as it can withstand the high-temperature oxidizing atmosphere when selectively oxidizing the Si layer 51. . The electrode 45 that becomes the photogate may be made of any conductive and heat-resistant material, such as polycrystalline Si or Mo film.
以上本発明の説明には、ｎチヤネル素子を例に
とつて説明したが、これは逆にｐチヤネル素子で
も、不純物の種類、電荷、電圧の極性を適当に変
えることで適用できる。 Although the present invention has been described above using an n-channel device as an example, it can also be applied to a p-channel device by appropriately changing the type of impurity, the charge, and the polarity of the voltage.
また第４図ｅにおいて、りんガラス膜５７を用
いたが、この膜は必ずしも必要でなく、これを形
成しないまま配線を形成してもよい。この場合、
コンタクト穴は以前のSi3N4のおおつていた領域
であるので、コンタクト穴も自己整合的に形成さ
れることになる。 Although the phosphor glass film 57 is used in FIG. 4e, this film is not necessarily necessary, and wiring may be formed without forming it. in this case,
Since the contact hole is a region previously covered with Si 3 N 4 , the contact hole is also formed in a self-aligned manner.
さらに同図ｅにおいてりんガラス膜のような保
護膜を最終工程で素子上に形成することは一般に
行なわれていることであるが、ここでこの工程を
入れても、本発明の本質には何らかかわることな
く、その効果が得られる。 Furthermore, although it is common practice to form a protective film such as a phosphor glass film on the device in the final step as shown in FIG. You can get the same effect without getting involved.
以上本発明の実施例は第１図に示すような
MOS形センサの基本的な構成を念頭において説
明したが、これはこれに限らず、ホトダイオード
と垂直信号線とをそなえたセンサであれば何であ
つても適用でき、たとえばホトダイオードアレー
部と垂直走査回路は第１図のようなMOS形セン
サと同様にし、水平レジスタに電荷移送素子
（CTD）を用いたような構成のセンサであつて
も、本発明の効果は大きい。また垂直信号線は第
１図のように１垂直方向の画素列について１本で
なくても、複数本たとえば２本そなえたような場
合（たとえばKoike etal 1979年 ISSCC
Dig0p192）でも本発明の効果が得られることは
自明である。 The embodiment of the present invention is as shown in FIG.
Although the explanation has been made with the basic configuration of a MOS type sensor in mind, this is not limited to this, and can be applied to any sensor equipped with a photodiode and a vertical signal line.For example, it can be applied to a photodiode array section and a vertical scanning circuit. The effect of the present invention is significant even in the case of a sensor having a structure similar to that of the MOS type sensor shown in FIG. 1 and using a charge transfer device (CTD) in the horizontal register. In addition, the number of vertical signal lines does not have to be one per one vertical pixel column as shown in Figure 1, but in cases where multiple, for example two, vertical signal lines are provided (for example, Koike et al. 1979 ISSCC
It is obvious that the effects of the present invention can also be obtained using the following methods.
また本発明はセンサに限らず、他のLSI、たと
えばMOSRAM（ランダムアクセスメモリ）など
においても、α線によるソフトエラー対策として
適用することにより、信号読み出し誤りのない、
動作マージンの広い素子を得ることができる。 Furthermore, the present invention can be applied not only to sensors but also to other LSIs, such as MOSRAM (random access memory), as a countermeasure against soft errors caused by alpha rays, thereby eliminating signal read errors.
A device with a wide operating margin can be obtained.
第１図は従来の固体撮像装置の概略を示す略回
路図、第２図は従来の固体撮像装置の受光部の構
成を示す断面図、第３図は本発明の固体撮像装置
の実施例に係わる受光部の構成を示す断面図、第
４図は、第３図の受光部の製造方法を工程順に示
す断面図である。
１００……ｎ形Si基板、１０１……ｐ形Si基
体、１０２……ホトダイオードn+層、１０３…
…酸化膜、１０４……リンガラス、１０５……配
線、１０６……保護膜、１０７……フイールド酸
化膜、１０８……フイールドアイソレーシヨン用
p+層、１１０……ドレイン用n+層、１１１……
ホトゲート、１１２……p+形層、１１３……ゲ
ート絶縁膜（SiO2等）。
FIG. 1 is a schematic circuit diagram showing an outline of a conventional solid-state imaging device, FIG. 2 is a sectional view showing the configuration of a light receiving section of a conventional solid-state imaging device, and FIG. 3 is an embodiment of a solid-state imaging device of the present invention. FIG. 4 is a sectional view showing the structure of the related light receiving section, and FIG. 4 is a sectional view showing the manufacturing method of the light receiving section of FIG. 3 in order of steps. 100...n-type Si substrate, 101...p-type Si substrate, 102...photodiode n + layer, 103...
... Oxide film, 104 ... Phosphorous glass, 105 ... Wiring, 106 ... Protective film, 107 ... Field oxide film, 108 ... For field isolation
p + layer, 110... n + layer for drain, 111...
Photogate, 112... p + type layer, 113... gate insulating film (SiO 2 etc.).
Claims (1)
成するための実質的に平坦な表面を有する第１不
純物領域と、上記受光素子に蓄積した電荷を読み
出す手段を形成するための第２不純物領域とから
なる複数の受光部と、周辺回路とを備えた固体撮
像装置において、上記第２不純物領域は、上記第
１不純物領域よりも浅く設けられ、かつ、上記第
１不純物領域の不純物は少なくともリンを含み、 上記周辺回路の少なくとも１つのMOSトラン
ジスタのソースおよびドレインは少なくともヒ素
（As）を含み、上記第１不純物領域よりも浅く設
けられてなり、かつ、上記半導体基体はn+−ｐ
−ｎ層構造となつていることを特徴とする固体撮
像装置。 ２ 特許請求の範囲第１項において、前記第１不
純物領域と第２不純物領域との間の前記半導体基
体表面に前記半導体基体と同じ導電型の高濃度領
域を有し、この高濃度領域と前記半導体基体との
電位差が3kT以上（ｋ：ボルツマン定数、Ｔ：絶
対温度）であることを特徴とする固体撮像装置。 ３ 特許請求の範囲第１項又は第２項記載の固体
撮像装置において、 上記第２不純物領域は、上記半導体基体上に設
けられた半導体層を有することを特徴とする固体
撮像装置。 ４ 特許請求の範囲第１項乃至第３項のいずれか
に記載の固体撮像装置において、 上記固体撮像装置は、電荷移送素子を含むこと
を特徴とする固体撮像装置。 ５ 特許請求の範囲第１項乃至第４項のいずれか
に記載の固体撮像装置において、 上記受光素子はMOS型センサであることを特
徴とする固体撮像装置。 ６ 特許請求の範囲第３項において、前記第２不
純物領域の上部側面積は、前記第２不純物領域が
前記半導体基体と接する面積よりも広いことを特
徴とする固体撮像装置。[Scope of Claims] 1. A first impurity region having a substantially flat surface for forming a light-receiving element, and a means for reading charges accumulated in the light-receiving element are formed in one main surface region of a semiconductor substrate. In the solid-state imaging device, the second impurity region is provided shallower than the first impurity region, and the second impurity region is provided shallower than the first impurity region, and the second impurity region is shallower than the first impurity region. The impurity of the region contains at least phosphorus, the source and drain of at least one MOS transistor of the peripheral circuit contains at least arsenic (As), and is provided shallower than the first impurity region, and the semiconductor substrate is n + −p
- A solid-state imaging device characterized by having an n-layer structure. 2. In claim 1, a high concentration region of the same conductivity type as the semiconductor substrate is provided on the surface of the semiconductor substrate between the first impurity region and the second impurity region, and the high concentration region and the A solid-state imaging device characterized in that a potential difference with a semiconductor substrate is 3 kT or more (k: Boltzmann constant, T: absolute temperature). 3. The solid-state imaging device according to claim 1 or 2, wherein the second impurity region includes a semiconductor layer provided on the semiconductor substrate. 4. The solid-state imaging device according to any one of claims 1 to 3, wherein the solid-state imaging device includes a charge transfer element. 5. The solid-state imaging device according to any one of claims 1 to 4, wherein the light receiving element is a MOS sensor. 6. The solid-state imaging device according to claim 3, wherein an upper side area of the second impurity region is larger than an area where the second impurity region contacts the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58234236A JPS59130468A (en) | 1983-12-14 | 1983-12-14 | Solid-state image pickup device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58234236A JPS59130468A (en) | 1983-12-14 | 1983-12-14 | Solid-state image pickup device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59130468A JPS59130468A (en) | 1984-07-27 |
| JPH0455346B2 true JPH0455346B2 (en) | 1992-09-03 |
Family
ID=16967820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58234236A Granted JPS59130468A (en) | 1983-12-14 | 1983-12-14 | Solid-state image pickup device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59130468A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4539176B2 (en) | 2004-05-31 | 2010-09-08 | ソニー株式会社 | Solid-state imaging device and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5234674A (en) * | 1975-09-12 | 1977-03-16 | Toshiba Corp | Semiconductor device |
| JPS52147017A (en) * | 1976-06-02 | 1977-12-07 | Hitachi Ltd | Solid image pick-up element |
| JPS5342567A (en) * | 1976-09-30 | 1978-04-18 | Oki Electric Ind Co Ltd | Semiconductor device and its production |
| JPS55110476A (en) * | 1979-02-19 | 1980-08-25 | Hitachi Ltd | Solidstate image sensor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54145078U (en) * | 1978-03-29 | 1979-10-08 | ||
| JPS5691462U (en) * | 1979-12-17 | 1981-07-21 |
-
1983
- 1983-12-14 JP JP58234236A patent/JPS59130468A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5234674A (en) * | 1975-09-12 | 1977-03-16 | Toshiba Corp | Semiconductor device |
| JPS52147017A (en) * | 1976-06-02 | 1977-12-07 | Hitachi Ltd | Solid image pick-up element |
| JPS5342567A (en) * | 1976-09-30 | 1978-04-18 | Oki Electric Ind Co Ltd | Semiconductor device and its production |
| JPS55110476A (en) * | 1979-02-19 | 1980-08-25 | Hitachi Ltd | Solidstate image sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59130468A (en) | 1984-07-27 |
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