JPH069236B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

The present invention relates to a solid-state image pickup device and a method for manufacturing the same, and the solid-state image pickup device according to the present invention is small in size with high sensitivity, low noise, and can be used for home movie cameras. It can be applied not only to TV cameras for broadcasting, but also to video cameras for astronomical observation using its high sensitivity, and also to still images such as still cameras.

[Conventional technology]

A conventional SIT (Static Induction Transistor (hereinafter abbreviated as SIT)) image sensor has a structure in which one of the main electrodes of the SIT formed on the n ⁺ substrate is common and has high sensitivity.
It had the features of low noise, high speed, and high integration.

[Problems to be solved by the invention]

The conventional SIT image sensor had the features of high sensitivity, low noise, and high speed, but in order to make it even more sensitive and excellent in the detection limit of weak light, SI that constitutes each pixel
It is necessary to make T close to normally-on, and in the conventional SIT image sensor, one of the main electrodes of the SIT that constitutes one pixel is common to all pixels. It has been difficult to configure pixels with a close SIT in that the separation between pixels deteriorates.

[Means for solving problems]

SIT with extremely excellent light sensitivity close to normally on 1
In order to construct a simple image sensor having one pixel and one transistor as a pixel, all electrodes of the SIT may be independent. In the present invention, SIT
By making all the electrodes independent of each other and performing the light separation of each pixel by the U groove, it is possible to completely perform the pixel separation while having high sensitivity. Further, a photo-detecting section composed of SIT having a very low sensitivity for detecting extremely weak light, which is close to the normally-on state, and a read-out circuit having a MOS transistor for scanning the photo-detecting section are manufactured on the same substrate by the simultaneous process. Provide a way.

[Action]

By separating the n ⁺ buried layer, which is one of the main electrodes of the SIT, on the p substrate, crosstalk between pixels in the signal readout line can be completely suppressed even if the SIT, which is close to the normally-on with high photosensitivity, is used as one pixel. be able to. Further, by separating each pixel into U-grooves, it is possible to improve the light separation, increase the aperture ratio, and achieve high integration. Further, the structure having the n ⁺ buried layer on the p substrate can increase the relative sensitivity to short wavelength light.

By using SIT and MOS transistors simultaneously, the number of masks used can be as small as 17 sheets.

Further, the γ characteristic of the photoelectric conversion characteristic can be made variable by changing the bias voltage of the substrate.

〔Example〕

FIG. 1 is a schematic cross-sectional view of an SIT for one pixel showing an embodiment of a solid-state image pickup device of the present invention, and one schematic cross-sectional view of a MOS transistor which constitutes a readout circuit of a photodetecting section formed of the SIT.

In the SIT of FIG. 1, on the p-type silicon substrate 1,
The n ⁺ buried drains 2 (here, tentatively drains), which are the drains or sources of the SITs, are separated so as to be common to each pixel or at least in one column direction. This separation is due to the U-groove 7 filled with polysilicon 7'and the p ⁺ buried region 6 provided on the lower surface of the U-groove.
A low impurity density n ⁻ type epitaxial layer 5 is formed on the n ⁺ buried drain 2, and a p ⁺ gate 4 and its p ⁺ gate 4 are formed on the surface of the n ⁻ type epitaxial layer 5.
In between, the n ⁺ source 3 is formed so that the p ⁺ gate region 4 is deeper than the n ⁺ region 3. Here, the vertical structure SIT of the present invention can operate by using either the n ⁺ region 3 or the n ⁺ buried layer 2 as a source, which is determined by the difference in the reading method.

A MOS capacitor having the gate oxide film 8 as an insulator and the polysilicon 4'as an electrode is formed on the p ⁺ gate 4. This capacitor stores carriers generated according to incident light. In order to increase the aperture ratio, the n ⁺ source 3 has an electrode made of polysilicon 3 ', and an Al electrode 3 "is formed on a part of the polysilicon.

Since the n ⁺ buried drain 2 serves as an electrode from the surface of the silicon substrate, the n ⁺ region 2'is formed from the surface of the silicon substrate.
It is formed so as to be in contact with the n ⁺ buried drain 2.

The above are the structural features of the SIT that constitutes one pixel of the photodetector of the solid-state imaging device of the present invention.

FIG. 1 shows a schematic cross-sectional view of one of the MOS transistors forming the read circuit, which is formed by the simultaneous process of SIT and the above-described SIT. This shows the p-well region on the n ⁻ type epitaxial layer 5. 9 is p on the bottom
N ⁺ main electrodes 10 and 11 are formed on the p well of the mold substrate 1, and a gate oxide film 13 and a polysilicon gate 12 'are formed on the upper surface of the p well.

An Al electrode 1 ″ is formed on the entire surface of the p-type silicon substrate 1 so that the n ⁺ buried drain 2 can be biased.

One SIT shown in FIG. 1 constitutes one pixel, and a photodetector composed of plural SITs and a MOS of the photodetector
The solid-state image pickup device of the present invention including the readout circuit formed of the transistors can be obtained by the embodiment of the method for manufacturing the solid-state image pickup device of the present invention described below with reference to FIG.

First, as shown in FIG. 2 (a), a p-type (100) Si substrate 1 having a specific resistance of 4 to 6 Ω · cm is prepared. SiO ₂ 21 is formed on the back surface and SiO ₂ 20 is formed on the front surface by wet oxidation to a film thickness of about 5000Å. After the mask process, the p ⁺ buried layer 6 is replaced with Si.
B (boron) impurity dose 1 with O ₂ 20 as a mask
It is formed by in-injecting at an acceleration voltage of 50 KeV at × 10 ¹⁵ cm ^-2 and annealing. Oxidation is performed by wet oxidation, and after passing through a mask process, the n ⁺ buried layer 2 is formed using As ₂ with As ₂ as a mask.
Is ion-implanted with an impurity dose amount of 1 × 10 ¹⁶ cm ^-2 at an acceleration voltage of 80 KeV and annealed.

Next, as shown in FIG. 2B, SiO ₂ on the surface is removed by etching, and SiO ₂ 22 having a film thickness of about 600 Å is formed by wet oxidation.

Next, as shown in FIG. 2 (c), before growing the n ⁻ type epitaxial layer 5, in order to prevent p inversion of the n ⁻ type epitaxial layer 6 from the p substrate 1 by autodoping, MO
Except for the p-well portion of the S transistor, P (phosphorus) is ion-implanted through the SiO ₂ 22 with an impurity dose amount of 5 × 10 ¹¹ cm ^-2 and an acceleration voltage of 100 KeV through the SiO ₂ 22 by a mask process. An n-type layer 24 is formed by annealing as shown in FIG. Further, the surface is oxidized and the thickness of SiO ₂ is set to about 1500 Å (SiO ₂ 25). At this time, the back surface is provided with polysilicon 26 for protection such as LPCV.
It is formed by the D method or the like.

Next, as shown in FIG. 2 (e), the SiO ₂ 25 on the surface is entirely removed by etching to form an n ⁻ type epitaxial layer 5 having a low impurity density of about 5 to 6 μm. The thickness of the n ⁻ type epitaxial layer 5 is determined in consideration of the electrical characteristics and the spectral sensitivity characteristics of the SIT that serves as a photodetector.

At this time, the p ⁺ buried layer 6 and the n ⁺ buried layer 2 also diffuse and spread in the n ⁻ type epitaxial layer.

Further, as shown in FIG. 2 (f), the polysilicon 26 on the back surface is removed by etching, and the front surface is wet-oxidized to a film thickness of 600.
Å SiO ₂ 27 is formed. Resist through mask process
28 is used as a mask and B is ion-implanted through SiO ₂ 27 with an impurity dose amount of 2 × 10 ¹³ cm ^-2 and an acceleration voltage of 100 KeV.
Although the p-well 9 is formed by annealing as shown in FIG. 6G, the thermal diffusion depth of B is shallower than the desired one in consideration of the subsequent steps.

Next, SIO ₂ 27 is further wet oxidized to a film thickness of 5500Å
The degree. (SiO ₂ 29) After the mask process, the resist 30 is used as a mask to etch SiO ₂ and Si to a depth of 4 to 5 μm.
A U groove 7 having a width of m and a width of about 3 μm is formed.

Further, as shown in Fig. 2 (h), Si is slightly etched, and the wall surface of the U groove is dry-oxidized to form a 1500 Å thick SiO ₂ film.
7 ″ is formed by, for example, LPCVD so that the polysilicon 31 is filled in the U groove 7. The polysilicon 31 and SiO ₂ 29 are removed by etching except the U groove 7.

Next, as shown in FIG. 2 (i), a film thickness of 5 is obtained by wet oxidation.
SiO ₂ 32 of about 000Å is formed.

The U-groove is filled with 7 polysilicon 7 '.

Further, as shown in FIG. 2 (j), through a mask process, the electrode region 2'of the n ⁺ buried layer is deposited by using the SiO ₂ 32 whose upper surface of the region 2'is etched off as a mask to deposit P. The n ⁺ electrode region 2 ′ is diffused by the thermal diffusion method, but the thermal diffusion depth of P is shallower than the desired depth in consideration of the subsequent steps.

Next, as shown in FIG. 2 (k), PSG 33 and SiO ₂ 32 are removed by etching, and then SiO ₂ 34 having a film thickness of about 600 Å is formed.
A region to be a p ⁺ channel stopper region 16 of the OS transistor, p ⁺ channel stopper region 16 through the mask process
With the resist 36 and Si ₃ N ₄ 35 removed from the upper surface of the portion to be B as an impurity dose amount of 5 × 10 ¹³ cm
Ion implantation with acceleration voltage of 100 KeV at ^-2 . Si ₃ N ₄ 35 is formed by, for example, the CVD method.

Further, as shown in FIG. 2 (1), Si ₃ N ₄ 35 is removed by plasma etching except where a MOS transistor is formed through a mask process.

Next, as shown in FIG. 2 (m), LO is used with Si ₃ N ₄ 35 as a mask.
A field oxide film 14 by COS but, Si ₃ N
₄ 35 After removal by plasma etching, SIT of the p ⁺ gate 4 and the n ⁺ source through a mask process or each of the upper surfaces of the drain 3 is etched away. Further, by the LOCOS and the subsequent annealing, the n ⁺ electrode region 2 ′, the p well 9, and the p ⁺ channel stopper region 10 are respectively formed to desired depths by thermal diffusion.

Next, as shown in Fig. 2 (n), 600 Å by wet oxidation.
SiO ₂ 37 having a certain thickness is formed on the portion of SiO ₂ 24 (the upper surface of each region of p ⁺ gate and n ⁺ source or drain of SIT which is removed by etching in the step of FIG. 2 (m)). . Al38 is vapor-deposited, but the area of MOS transistor and S
It is removed by etching through a mask process except for the upper surface of the IT n ⁺ source or drain region. Furthermore, Fig. 2 (o)
As shown in Fig. 3, B is ion-implanted at an accelerating voltage of 50 KeV with an impurity dose amount of 5 × 10 ¹⁵ cm ^{-2 using the} Al 38 and SiO ₂ 14 as a mask, and the Al 38 is etched away and then annealed.
The p ⁺ gate 4 of IT is formed to a depth of about 3 μm. This p ⁺
The interval and the depth of the gate 4 are one of the factors that most determine the characteristics of the SIT, and are determined in advance so as to be the optimum SIT for the photodetector. SiO ₂ 37 is removed by slight etching.

Next, as shown in FIG. 2 (p), MO on the p ⁺ gate of SIT
The SiO ₂ 8 constituting the S capacitor and the gate oxide film 13 of the MOS transistor are formed. For example, this is SiO ₂ having a thickness of about 700 Å obtained by oxidizing in an atmosphere of O ₂ + HCl at 1100 ° C. for about 13 minutes. It is ₂ membranes.

Next, channel doping is performed by ion implantation through a mask process depending on whether the MOS transistor is of depletion type or enhancement type. FIG. 2 (p) shows a case of forming a depletion type MOS transistor which becomes a load transistor of the E / DMOS inverter. At this time, P is ion-implanted with an impurity dose amount of 2.0 × 10 ¹² cm ^-2 and an acceleration voltage of 120 KeV using the resist 39 as a mask. In the case of the enhancement type, B is ion-implanted with an impurity dose amount of 5 × 10 ¹¹ cm ⁻² and an acceleration voltage of 60 KeV, for example.

Further, as shown in FIG. 2 (q), the resist 4 is processed through a mask process.
Using 0 as a mask, SiO ₂ is removed by etching to form a contact hole for forming an n ⁺ source or drain 3 electrode of SIT and a contact hole for forming an electrode of a MOS transistor.

Next, as shown in FIG. 2 (r), P-doped n-type polysilicon (DOPOS) is formed on the surface by the CVD method, and the polysilicon electrodes 4'and S on the p ⁺ gate 4 of the SIT are formed.
A polysilicon electrode 3'of the IT source or drain 3,
Except for the insulated gate electrode 12 'of the MOS transistor, the drain electrode 10' of the MOS transistor, and polysilicon (not shown in the figure) used as wiring, DOPOS is removed by plasma etching using a resist as a mask after a mask process. .

Next, as shown in FIG. 2 (s), P is added as an impurity dose amount of 3 × 10 ¹⁵ cm through SiO ₂ 13 using SiO ₂ 14 and DOPOS as a mask.
^-2 at an accelerating voltage of 110 KeV, PSG is formed by CVD to a thickness of about 4000 Å, and then the n ⁺ source 10 and the n ⁺ drain 11 of the MOS transistor are deepened to a depth of about 1.5 μm and the n ⁺ source of the SIT by annealing. Alternatively, the drain 3 is formed to a depth of about 1 μm.

Further, as shown in FIG. 2 (t), a contact hole 41 is formed to form an Al electrode, but after two mask steps,
It is formed by etching PSG and SiO ₂ in this order.

Next, as shown in FIG. 2 (u), SiO ₂ on the back surface is removed by etching, Al is deposited on the front surface and the back surface, and unnecessary Al is removed by etching through a mask process.

The manufacturing method of the present invention described above with reference to FIG. 2 constitutes the SIT of the structure of the present invention which is excellent in weak light detection sensitivity and is capable of complete pixel separation, and the readout circuit of the photodetection section including the SIT. A manufacturing method suitable for simultaneously manufacturing MOS transistors on the same silicon substrate,
The number of masks used is as small as 17 sheets.

Although the manufacturing method described above has been described a method of fabricating on a p substrate, a similar manufacturing process, impurity density of 10 ¹⁸
Impurity density is about 5β on a substrate with p ⁺ of cm ^-3 or more.
It may be fabricated on a substrate having a p ⁻ layer of 10 ¹² to 10 ¹⁴ cm ⁻³ . By using this substrate, the effect of the bias voltage of the P substrate can be improved.

Next, the SIT of the photodetector that constitutes the solid-state imaging device of the present invention
The matrix forming method and the photodetector reading method will be briefly described with reference to circuit examples together with the operation of the solid-state imaging device of the present invention.

FIG. 3 (a) shows an example of the configuration and read circuit of the solid-state imaging device of the present invention, and FIG. 3 (c) shows a timing chart of the read pulse.

In the configuration and readout circuit example of the solid-state imaging device of the present invention shown in FIG. 3 (a), the SIT50 serving as the photodetector of the present invention shown in FIG. 1 uses the n ⁺ buried layer 2 as the source and n ⁻ A MOS capacitor provided on the gate by an inverted operation using the n ⁺ region 3 provided on the surface of the epitaxial layer 5 as a drain.
One electrode 4'of 51 is connected to the vertical address line 80, the source is connected to the buried 82 parallel to the vertical address line 80, and the drain is connected to the horizontal output line 81. According to the pulse timing of FIG. 3 (c), when the transfer MOS transistor 53 is turned on by φ _T , the precharge MOS transistor 52 is turned on by φ _P , and the horizontal output line 81 is turned by the precharge wire 57. When it is charged to a certain potential (which is determined by the operating point of SIT50) and then a pulse of φ _G is applied to the vertical address line 80, the switch MOS transistor 59 connected to the embedded line 82 is turned on and A row of SITs connected to vertical address lines
It is added through a period of time T _LI to phi _G becomes pulse holes generated in the depletion layer in the channel by the light that enters is accumulated in the p ⁺ gate 4 thereto have biased the gate SIT50 the capacitor 51 Then, a discharge is generated according to the incident light. Therefore, the pulse potential of φ _G is set to an optimum value in terms of the characteristics of SIT.

At this time, the holes accumulated in the p ⁺ gate 4 are discharged to the source and refreshed to a constant potential.

SI on the vertical address line not selected by φ _G
T is the switch MOS transistor of the buried line is OFF
Since it is in the state, even if the potential of the channel is lowered according to the incident light, it does not contribute to the discharge of the horizontal output line.

Then, when the transfer MOS transistor 53 is turned off at the fall of φ _G , the discharge amount of SIT is stored in the transfer capacitor 55 as the discharge amount of the transfer capacitor 55. The phi _s composed pulses from the horizontal shift register 71 are generated in accordance with the pulse timing of FIG. 3 (c), the optical information stored in the transfer capacitors 55 by sequentially ON state switching MOS transistor 54 by the phi _s,
When the transfer capacitor 55 is charged by the video power source 58, it is sequentially output as an electric signal to the output terminal 60 as a voltage drop due to the load resistor 56.

Similarly, a pulse of φ _G is generated from the vertical shift register 70 to select the vertical address line.

Precharge MOS transistor 52, transition MOS transistor 53, switch MOS transistor 5
4, 59 and vertical shift register 70, horizontal shift register 7
1 consists of a MOS transistor made on the same substrate as the SIT by a simultaneous process.

The output can be increased by enlarging the transfer capacitor 55, but this transfer capacitor is exactly the same as the process of forming the insulating polysilicon gate on the p ⁺ gate 4 of the SIT on the p ⁺ channel stopper 16 of the MOS transistor. It can be manufactured by forming a polysilicon electrode in the process.

The vertical shift register 70 and the horizontal shift register 71 can be composed of, for example, a shift register using an E / D MOS inverter and a super buffer.

FIG. 3 (b) shows another example of the readout method of the solid-state imaging device of the present invention, and FIG. 3 (c) shows a timing chart of readout pulses.

In the example of the reading method shown in FIG. 3 (b), the SIT50 serving as the photodetector of the present invention shown in FIG. 1 is upright. That is, the n ⁺ buried layer 2 is used as a drain, and the n ⁺ region 3 on the surface of the n ⁻ epitaxial layer 5 is used as a source.

The circuit configuration is the same as in FIG. 3 (a).

According to the pulse timing of FIG. 3 (c), first, when the transfer MOS transistor 53 is in the NO state by φ _T , the precharge MOS transistor 52 is turned by φ _P.
When the pulse of φ _G is applied to the vertical address line 80 by setting the horizontal output line to 0 voltage by turning on the switch, the switch MOS transistor 59 connected to the embedded line 82 is turned on and the video power source is turned on. 57 'by S
A row of SITs that are connected to the vertical address lines while biasing IT discharges according to the amount of incident light and charges the horizontal output line 81.

Next, the transfer MOS transistor 53 is turned off at the fall of φ _G , and the discharge amount of SIT is stored as the charge amount charged in the transfer capacitor 55. A pulse of φ _{S is} generated from the horizontal shift register in accordance with the pulse timing of FIG.
By sequentially turning on the switch MOS transistor 54 by _S , the optical information stored in the transfer capacitor 55 is sequentially output as an electric signal to the output terminal 60 as discharge by the load resistor 56.

Similarly, a pulse of φ _G is generated from the vertical shift register 70 to select the vertical address line.

〔The invention's effect〕

In the solid-state imaging device of the present invention, one of the main electrodes is separated between adjacent pixels in the structure, so that not only a normally-off type device having a SIT characteristic but also a normally-on type device having a high current amplification factor is designed. Since it can be integrated and arranged, it is possible to provide a solid-state imaging device having extremely high photosensitivity.

FIG. 4 is a diagram showing a photoelectric conversion characteristic of the solid-state imaging device according to the present invention. The horizontal axis is the amount of incident light, and the wavelength of the incident light is 65
It is 5 nm. The vertical axis takes the output voltage difference from the dark state in the output voltage at the output terminal 60. The photoelectric conversion characteristic according to the present invention is obtained by the reading method shown in FIG. 3 (b).

It can be seen that the photosensitivity is extremely high as compared with the conventional SIT image sensor. S / N ratio 60 dB or more, dynamic range 80 dB or more, and minimum received power 5 × 10 ^-5 μw / cm ²
The following values are achieved.

Further, FIG. 5 is a diagram showing that the γ characteristic of the photoelectric conversion characteristic of the solid-state image pickup device of the present invention can be changed by changing the bias of the p substrate. The horizontal axis is the incident light amount, and the wavelength of the incident light is 655 nm. Is. The vertical axis takes the output voltage difference between the output voltage appearing at the output terminal 60 and the dark state. The reading method is shown in FIG. 3 (b). The γ value is changed from 0.42 to 5 by changing the bias to the source of the substrate from 0 to −5V.

FIG. 6 shows the spectral sensitivity characteristic. The wavelength was changed from 400 nm to 1010 nm while keeping the amount of incident light constant. It can be seen that the solid-state imaging device of the present invention has significantly improved short-wavelength sensitivity as compared with the conventional SIT image sensor.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of the SIT and the MOS transistor, the second.
FIG. 4 is a schematic cross-sectional view for explaining the simultaneous process of SIT and MOS transistor, FIG. 3 is a view for explaining the operation of the solid-state image pickup device of the present invention, FIG. 4, FIG. 5, and FIG. It is a figure for demonstrating the effect of invention, Comprising: It is a figure of photoelectric conversion characteristic comparison, (gamma) characteristic, and spectral sensitivity characteristic, respectively. 1 ... p-type Si substrate, 1 ″ ... substrate Al electrode, 2 ... n ⁺ buried layer,
2 '... buried layer electrode, 3 ... source or drain, 3' ... polysilicon electrode, 4 ... gate, 4 '... insulating polysilicon electrode, 5 ... n ^- epi layer, 6 ... p ⁺ buried layer, 7 ... U groove, 7 '...
U-groove polysilicon, 7 ... SiO ₂ 8 ... SiO ₂ on the gate,
9 ... pwell, 10 ... source of MOS transistor, 11 ... M
Drain of OS transistor, 11 '... polysilicon electrode, 12 ... Channel of MOS transistor, 12' ... Insulating polysilicon gate electrode, 13 ... Gate oxide film, 14 ... Field oxide film, 16 ... Channel stopper, 24 ... P inversion prevention n layer, 31 ... Polysilicon

Claims (3)

[Claims] 1. A surface of a first layer formed on a silicon wafer comprising a low impurity density first layer and a high impurity density second layer having a conductivity type different from that of the first layer. The formed at least one first main electrode region, and the first main electrode region sandwiches the first main electrode region from the surface of the first layer to the first main electrode region.
A gate region formed deeper than the main electrode, and a first insulated gate region which is provided on at least a part of an upper surface of the gate region and is insulated by a first insulator so as to form a capacitor with the gate region. A second main electrode is provided between the first layer and the second layer and has a conductivity type different from that of the second layer. The second main electrode is provided to face the first main electrode and has a high impurity density. The first region is formed so that the second region having the same conductivity type as the first region is in contact with the first region from the surface so that the electrode can be taken from the surface. The wall surface of the adjacent vertical static induction transistor is separated by a U-groove filled with a first polysilicon covered with a second insulator, and the first region also includes the U-groove and the U-groove. The first area provided on the lower surface A type different high impurity density third one pixel vertical static induction transistor are separated by regions of a solid-state image pickup device for an optical detector, and a switch MOS transistor for scanning of the solid-
A MOS transistor forming a shift register for generating a scan pulse for reading the solid-state image sensor is a second layer in which the well of the same conductivity type as the second layer is in the first layer of the solid-state image sensor. Is formed to contact the
The third main electrode and the fourth main electrode of the MOS transistor are formed on the upper surface of the well, and the second polysilicon is insulated by the third insulator to become the second insulated gate region of the MOS transistor. A solid-state image pickup device, which is manufactured as described above and serves as a readout circuit of the solid-state image pickup device. 2. The gamma characteristic of the photoelectric conversion characteristic of the photodetector including the vertical electrostatic induction transistor is controlled by changing the potentials of the second layer and the first region. The solid-state imaging device according to claim 1. 3. A method of manufacturing a solid-state imaging device, wherein a vertical electrostatic induction transistor and a MOS transistor are simultaneously manufactured on a silicon wafer which is a second layer, comprising: (i) a silicon substrate which is the second layer. First impurity doping for forming a third region is performed, and the third region is formed by annealing, and further, the second region is formed.
Second impurity doping for forming the first region on the silicon substrate to be a layer of the first region and forming the first region by annealing, so that the third region is more than the first region. The process of forming deeply on the silicon substrate. (Ii) The first layer is formed on the silicon substrate so as to sandwich the first region and the third region by epitaxial growth of silicon, and the first layer is formed by autodoping from the silicon substrate. A third layer of the same conductivity type as the first layer to prevent the portion of the vertical static induction transistor serving as the channel from having a desired conductivity type and a desired resistivity. A step of performing the epitaxial growth after forming on the same surface as the first region and the third region except the portion where the well is formed. (Iii) A step of forming a region shallower than the well by performing third impurity doping for forming a well of the MOS transistor from the upper surface of the first layer and annealing. (Iv) U-groove is etched to form U-groove.
A step of forming a groove to a depth reaching the third region, forming a first oxide film as a second insulator on the surface of the U groove, and filling the first oxide film with the first polysilicon. (V) After performing the third impurity doping for forming the second region and the fourth impurity doping for forming the channel stopper of the MOS transistor, annealing the well, the second region, Forming the channel stopper. (Vi) A field oxide film is formed by LOCOS on the upper surface of the first layer other than the portion where the MOS transistor is formed, and the gate region of the vertical static induction transistor and the first main electrode region are self-assembled. A step of simultaneously removing an upper surface portion of the gate region of the field oxide film and an upper surface portion of the first main electrode region of the field oxide film by the same mask in order to form by alignment. (Vii) After forming the gate region of the vertical static induction transistor, a step of simultaneously forming a second oxide film to be the second insulator and a third oxide film to be the first insulator . (Viii) After channel doping of the MOS transistor, the first insulated gate region and the first main electrode region for forming the gate region and the capacitor of the vertical electrostatic induction transistor, and the first main electrode region and the D as the first electrode region of the first main electrode, the second insulated gate region of the MOS transistor, the second electrode region of the third main electrode, and the third electrode region of the fourth main electrode.
Step of forming OPOS at the same time. (Ix) A step of simultaneously forming the first main electrode region of the vertical static induction transistor and the third main electrode and the fourth main electrode of the MOS transistor. A method for manufacturing a solid-state imaging device, comprising: