JPH069232B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having an element isolation region, and more particularly to a semiconductor device that effectively utilizes an element isolation region formed of a one conductivity type semiconductor. Manufacturing method.

INDUSTRIAL APPLICABILITY The present invention is applied to, for example, a photoelectric conversion device of a system in which carriers generated by photoexcitation are accumulated and a stored voltage generated by the accumulated carriers is read.

[Prior art]

FIG. 1 shows a photoelectric conversion device described in Japanese Patent Application No. 58-120755, and FIG. 1 (a) is a plan view of the photoelectric conversion device in which photosensor cells are two-dimensionally arranged. (b) is the sectional view on the AA 'line.

In FIGS. 1A and 1B, photosensor cells are arranged on an n ⁺ silicon substrate 101, and each photosensor cell is S
It is electrically insulated from an adjacent photosensor cell by an element isolation region 102 made of iO ₂ , Si ₃ N ₄ or polysilicon.

Each photosensor cell is an n ⁻ region 103 having a low impurity concentration formed by an epitaxial technique or the like, a base of a bipolar transistor doped with a P type impurity (for example, boron, etc.) and a P channel serving as a source of a P channel MOS transistor. Region 104, P region 105 serving as the drain of the P channel MOS transistor, n ⁺ region 106 serving as the emitter of the bipolar transistor, oxide film 107.
Gate electrode 10 of P-channel MOS transistor
8. MOS capacitor electrode 109 and emitter electrode 11 for applying a pulse to the P region 104 through the oxide film 107
0, and an electrode 111 that applies a predetermined potential to the P region 105
Etc.

The operation of the optical sensor cell having such a configuration will be described.

First, in the charge accumulation operation, the P region 104 which is the base is
The n ⁺ region 106 is biased to a negative voltage to accumulate holes generated by light. By accumulating holes, P
The potential of the region 104 changes in the positive direction, but the potential of the P region 104 of each photosensor cell varies depending on the intensity of light.

The read operation is performed in this state. That is, when the read pulse voltage V _R is applied to the MOS capacitor electrode 109,
P region 104 has a positive potential, and the information accumulated in P region 104 is read to the side of n ⁺ region 106 which is the emitter.
Then, the read pulse voltage V _R is set to the ground potential, and information is output from the n ⁺ region 106 to the outside through the emitter electrode 110.

Next, in a state where the potential of the P region 104 differs depending on the intensity of light, a negative pulse is ignited to the gate electrode 108 to perform a refresh operation. This negative pulse causes p
The channel MOS transistor becomes conductive, and P region 1
The holes accumulated in 04 are removed and the P region 104 is fixed at a predetermined negative voltage. That is, by this refresh operation, the base P region 104 is
Has been completely initialized, and thereafter, the above-mentioned accumulation, reading, and refreshing operations are repeated.

As described above, by fixing the P region 104, which is the base, to a predetermined negative voltage during the refresh operation, optical information can be erased completely and at high speed regardless of the intensity of light.

However, particularly in a photoelectric conversion device, it is desirable to effectively use the element surface in response to the demand for improved sensitivity and higher resolution.

In this respect, the conventional photoelectric conversion device is not sufficient. That is, as shown in FIG. 1, since the device isolation region 102 made of an insulating material is provided, the device becomes larger by this region, and the device becomes conductive when refreshed.
It is necessary to specially provide a wiring for applying a predetermined negative voltage to one main electrode region of the S transistor.

[Object of the Invention]

The present invention has been made in view of the above conventional problems,
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which the control voltage region (base region) is surely returned to a predetermined potential, the structure is simplified, and the element surface can be effectively used.

[Outline of the present invention]

In order to achieve the above-mentioned object, a method for manufacturing a semiconductor device according to the present invention, a control electrode region made of a semiconductor of a first conductivity type and capable of accumulating carriers by receiving light energy, and the first conductivity type are A first and a second main electrode regions made of different second conductivity type semiconductors, a phototransistor having the same, an element decomposition region made of a first conductivity type semiconductor, the control electrode region and the element isolation region A method of manufacturing a semiconductor device, comprising: an insulating gate type transistor for refreshing the phototransistor, which is provided as an electrode region, the method comprising: forming the control electrode region and the element isolation region in a common substrate; Is disposed between the control electrode region and the element isolation region, and the control electrode region and the element are used as a mask. The separation region of the same conductivity type semiconductor region formed in said substrate and determining the channel length of the insulated gate transistor.

Example of Invention

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a manufacturing process diagram of an embodiment of a method for manufacturing a semiconductor device according to the present invention. In this embodiment, the case of a photoelectric conversion device is taken up.

First, as shown in FIG. 2 (a), the impurity concentration is 1 × 1.
An n ⁺ layer 2 for ohmic contact having an impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ^-3 is diffused into the back surface of the n-type substrate 1 having a concentration of 0 ^{15 to} 5 × 10 ¹⁷ cm ^-3 by P, As or Sb diffusion. Formed by. Then, an oxide film 3 having a thickness of 3000 to 7000Å is formed on the n ⁺ layer 2.
(Tateto SiO ₂ film) is formed by the CVD method.

The oxide film 3 is called a back coat and prevents generation of impurity vapor when the substrate 1 is heat-treated.

Next, the surface of the substrate 1 is heated at a temperature of 1000 ° C. and HCl is adjusted to 2 / mi.
After etching for about 1.5 minutes under the conditions of n and H ₂ 60 / min, a source gas SiH ₂ Cl ₂ (100%) of 1.2 / min and a doping gas (H ₂ diluted PH ₃ , 20PPM) of 100 cc are flown at a growth temperature of 1000. The n ^- epitaxial layer 4 (hereinafter referred to as the n ^- layer 4) is formed under a reduced pressure of 120 to 180 Torr. At this time, the single crystal growth rate is 0.5 μm / min, the thickness is 2 to 10 μm, and the impurity concentration is 1 × 10 ¹² to 10 ¹⁶ cm.
^-3 , preferably 10 ¹² to 10 ¹⁴ cm ^-3 [Fig. 2
(b)].

In order to improve the quality of the n ⁻ layer 4, the substrate is first subjected to a high temperature treatment at about 1150 to 1250 ° C. to remove oxygen from the vicinity of the surface and then subjected to a long-term heat treatment at about 800 ° C. for microdefects inside the substrate. It is also extremely effective to generate a large number of GaN and to have a substrate capable of intrinsic gettering having a denuded zone.

Next, an oxide film 5 having a thickness of 4000 to 8000Å is formed on the n ⁻ layer 4 tatami by pyrogenec oxidation (H ₂ + O ₂ ), wet oxidation (O ₂
+ H ₂ O) or steam oxidation (N ₂ + H ₂ O). Furthermore, in order to obtain a good oxide film without stacking faults,
High pressure oxidation at temperatures of 800 to 1000 ° C. is suitable.

Then, in order to form the element isolation region, a part of the oxide film 5 is selectively removed by the photoringography method [FIG. 2 (c)].

Next, boron nitride (hereinafter referred to as BN) formed in a wafer shape is placed in a diffusion furnace so as to face the wafer shown in FIG. 2 (c), and the temperature is set to 800 ° C. in an H ₂ + O ₂ + N ₂ atmosphere.
Is heat-treated to deposit on the boron glass oxide film 5 containing the impurity B and the n ⁻ layer 4. Then, the adhered impurities B are shallowly diffused by applying heat treatment at 1100 ° C. for 5 to 15 minutes in an N ₂ atmosphere.

At that time, the boron glass which is formed on the surface and causes nonuniform diffusion is removed by hydrofluoric acid + HNO ₃ .

Further, oxidation is performed at 800 ° C. in an H ₂ + O ₂ atmosphere (30
~ 60 minutes). By this oxidation, it is possible to take defects in the vicinity of the surface generated in the step of adhering the boron glass and the impurities B that have not been completely removed into the oxide film.

The oxide film thus formed is removed with hydrofluoric acid to expose a clean and defect-free surface.

Then, in the atmosphere of H ₂ + O _{2 at} 950 to 1050 ° C., 30 to
Push-in (drive-in) is performed for 50 minutes to form the p ⁺ element isolation region 6 and the oxide film 7 [FIG. 2 (d)].

In this example, the sheet resistance was pushed for 60 minutes to obtain the sheet resistance.
An element isolation region 6 having a resistance of 20 Ω / □ and a depth of 1.7 μm was formed.

Further, as shown in FIG. 2 (c), after forming the oxide film 5, BSG (boron silicate glass; SiO ₂ film containing B as an impurity) as a diffusion source is formed by the CVD method and indentation is performed. As with the above diffusion, p ⁺ element isolation region 6
Can be formed.

When the p ⁺ element isolation region 6 is formed in this manner, the oxide film 7 (but not the oxide film 5) is formed to form a base region next.
Are selectively removed by etching, and an oxide film 8 for buffer is formed there [FIG. 2 (e)].

The oxide film 8 is provided for preventing channeling and surface defects when forming the base region by ion implantation, and has a thickness of 500 to 1500Å. Further, the oxide film 3 of the back coat is completely removed in this step.

Next, B ⁺ ions or B generated using BF ³ as a source gas.
Implant F ₂ ⁺ ions into the wafer. At this time, the oxide film 7 serves as a mask, and B ⁺ ions are implanted only under the oxide film 8.
This surface concentration is 1 × 10 ^{15 to} 5 × 10 ¹⁸ cm ^-3 , preferably 1
〜20 × 10 ¹⁶ cm ^-3 , the ion implantation amount is 7 × 10 ¹¹ 〜1 ×
10 ¹⁵ cm ^-2 , preferably 1 x 10 ¹² to 1 x 10 ¹⁴ cm ^-2 .

When the ions are implanted in this way, 1000 to 1100
° C., to form the p-type base region 9 to a predetermined depth by thermal diffusion in an N ₂ atmosphere [FIG. 2 (f)]. Base area 9
Has a depth of, for example, about 0.6 to 1 μm.

The thickness and impurity concentration of the base region 9 are determined by the following ideas. To increase the sensitivity, it is desirable to reduce the impurity concentration of the base region 9 to reduce the base-emitter capacitance Cbe. Cbe is roughly given as follows.

However, Vbi is the diffusion potential between the emitter and base, Given in. Where ε is the dielectric constant of the silicon crystal, N _D
Is the impurity concentration of the emitter, N _A is the impurity concentration of the portion adjacent to the emitter of the base, n _i is the intrinsic carrier concentration, A _e is the area of the base region, k is the Boltzian constant, T is the temperature, and q is the unit charge amount. is there. Cbe becomes smaller as N _A becomes smaller and the sensitivity increases, but if N _A is made too small, the base region will be completely depleted in the operating state and become a punching through state, so it cannot be made too low. . It is set to such an extent that the base region is not completely depleted and a punching through state does not occur.

As a method of forming the base region 9, there is also a method of depositing BSG on a wafer and diffusing the impurity B to a predetermined depth by thermal diffusion at 1100 to 1200 ° C.

Thus, when the element isolation region 6 and the base region 9 are formed, the oxide films 7 and 8 are removed, and the thickness of several 10
An oxide film 10 of several hundred Å is formed [Fig. 2 (g)].

Instead of the oxide film 10, a nitride film (Si
₃ N ₄ ) is also acceptable. The nitride film has a dielectric constant about twice that of SiO ₂ and can obtain a large capacitor capacity. Further, the oxide film (SiO ₂ film) has an advantage that the interface between Si and SiO ₂ is stable, and the thermal stress and the interface state are small.

When the oxide film 10 is formed, P ⁺ ions are added in an amount of 5 × 10 ¹⁰ to 1 ×.
^Implant 10 ¹³ cm ^-2 ions. This ion implantation is performed on the P channel formed between the base region 9 and the element isolation region 6.
This is done to determine the threshold voltage V _{th of the} MOS. In this embodiment, the threshold voltage is set to 0.5-2V.

Subsequently, a nitriding gap 11 (Si ₃ N ₄ ) is formed on the oxide film 10 to a thickness of 500 to 1500 Å [FIG. 2 (h)]. Forming temperature is 7
It is 00-900 degreeC.

Next, after further forming the PSG film 12 on the nitride film 11,
By the photolithography process including the two mask aligning processes, the oxide film 10, the nitride film 11 and the PSG film 12 are all removed from the portion to be the emitter, and the gate of the P-channel MOS transistor and the capacitor Cox are removed from the oxide film 1.
The nitride film 11 and the PSG film 12 are removed by etching leaving 0. Then, a resist R is applied thereon, and the resist R is patterned so that a predetermined channel length can be formed [FIG. 2 (i)]. The resist R arranged between the base region 9 and the element isolation region 6 serves as a mask material for forming a semiconductor region.

Then, as a mask of the resist R, B ⁺ ion implantation is performed. The ion implantation amount is 5 × 10 ¹³ to 1 × 10 ¹⁵ cm ^-2 .

Then, the resist R is removed and a heat treatment at 1000 ° C. is performed for 1
Impurities implanted on the surface of the substrate 1 after 0 to 30 minutes
By pressing (B), ap region a1 to be a semiconductor region is formed [FIG. 2 (j)].

That is, by this step, the distance l between the element isolation region 6 and the base region 9 is determined in a self-aligned manner by patterning the resist R. Distance l is P channel MOS
Since it is the channel length of the transistor, manufacturing the channel length uniformly makes the threshold voltage V _th uniform and P
This results in stabilizing the operation of the channel MOS transistor.

Then, the As-doped polysilicon is replaced with (N ₂ + SiH ₄ + As
H ₃ ) or (H ₂ + SiH ₄ + AsH ₃ ) gas is deposited by the CVD method. The deposition temperature is about 550 ° C to 900 ° C, and the thickness is 200.
It is 0-7000Å. Of course, non-doped polysilicon may be deposited by the CVD method and then As or P may be diffused.

Then, the deposited polysilicon film is removed by etching after the photolithography process with mask alignment, and PSG
By etching the film 12, the PSG can be lifted off.
The polysilicon deposited on the film 12 is removed in a self-aligned manner to form polysilicon 13 and 14 [FIG. 2 (k)].

However, the etching of the deposited polysilicon is performed using C ₂ Cl ₂
F ₄ and (CBrF ₃ + Cl ₂ ), etc., are used for the nitride film 11
Is etched with a gas such as CH ₂ F ₂ .

Then, heat treatment is performed to diffuse the impurities (As) from the polysilicon 13 into the base region 9 to form the n ₊ emitter region 15 [FIG. 2 (l)].

Next, a PSG film 16 having a thickness of 3000 to 7000 Å is deposited by the above-described gas-based CVD method, and subsequently, a contact hole is opened on the polysilicon 14 by a mask aligning process and an etching process. Electrode 17 (A
metal such as l, Al-Si, Al-Cu-Si) is deposited by vacuum evaporation or sputtering [Fig. 2 (m)].

Subsequently, an interlayer insulating film 18 such as a PSG film or a SiO ₂ film is deposited by a CVD method to a thickness of 3000 to 6000Å. Then, the polysilicon 13 is subjected to a mask alignment and an etching process.
A contact hole is opened on the top surface and the electrode 19 (Al, Al-Si, Al-
Cu-Si or the like) is formed [Fig. 2 (n)].

And finally, the passivation film 20 (PSG film or Si ₃
N ₄ film, etc.) is formed by the CVD method, and electrodes 2 are formed on the back surface of the wafer.
1 (metal such as Al, Al-Si, Au) is formed and completed [second
(Figure (o)].

FIG. 3 is a plan view of a photoelectric conversion device in which the photosensor cells shown in FIG. 2 (o) are two-dimensionally arranged.

Next, the configuration and operation of this embodiment will be described with reference to FIG. 2 (o) and FIG.

In FIG. 2 (o) and FIG. 3, n on the substrate 1 of n-type silicon _- epitaxial layer 4 is formed, it is electrically insulated by the photosensor cell to another by p ⁺ isolation region 6 therein Has been formed.

Each photosensor cell is sandwiched on the n ⁻ epitaxial layer 4 by insulating the p base region 9 serving as the control electrode of the bipolar transistor serving as the phototransistor, the emitter region 15 serving as the n ⁺ first main electrode region, and the oxide film 10. An electrode connected to the n ₊ emitter region 15 and a polysilicon 14 for an electrode which also serves as a gate of a p-MOS transistor serving as a gate type transistor and an electrode of a capacitor Cox for applying a pulse to the p base region 9. And the electrode 19 connected to the polysilicon 13, the electrode 17 connected to the polysilicon 14, and the like. A part of the n-type silicon substrate 1 and the n ⁻ epitaxial layer 4 becomes the second main electrode region of the phototransistor. Also,
The p ⁺ element isolation region 6 and the p base region 9 serve as a main electrode region (source / drain region) of the insulated gate transistor.

The basic operation of the optical sensor cell having such a configuration will be described below.

First, in the charge accumulation operation, after applying a reverse bias potential to the n ⁺ emitter region 15 in the p base region 9, the potential of the polysilicon 14 is maintained at a positive potential higher than the threshold voltage of the p-MOS transistor, The p-MOS transistor is turned off, and holes generated by light are accumulated in the p base region 9.

Due to the accumulation of holes, the electric field of the p base region 9 changes in the positive direction, but the electric potential of the p base region 9 of each photosensor cell varies depending on the intensity of light.

In this state, a positive read pulse voltage V _R is applied to the polysilicon 14 from the electrode 17. Since the voltage V _R is positive, the p-MOS transistor remains off.

When applied to the read pulse voltage V _R polysilicon 14, p base region 9 is forward-biased with respect to n ⁺ emitter region 15, n ⁺ occurs electrons injected from the emitter region 15 to the p base region 9, The potential of the n ⁺ emitter region 15 gradually changes in the positive potential direction. That is, the information stored in p base region 9 is read out to the emitter side.

After the read pulse voltage V _R is applied for a certain period of time, when the polysilicon 14 becomes the ground potential, the p base region 9 becomes
n ⁺ emitter region 15 is reverse biased, and n ⁺
The potential change of the emitter region 15 stops.

In this state, the information on the emitter side is read out through the polysilicon 13 and the electrode 19.

When this reading is completed, the electrode 19 is grounded and the n ⁺ emitter region 15 becomes the ground potential. However, in this state, the potential corresponding to the intensity of light, that is, the light information is still stored in the p base region 9, so it is necessary to remove this light information.

Therefore, the p-MOS is formed on the polysilicon 14 through the electrode 17.
A negative pulse voltage V _RH exceeding the threshold voltage V _{th of the} transistor is applied. As a result, the p-MOS transistor becomes conductive, the holes accumulated in the p base region 9 are removed, and the potential of the p base region 9 is fixed to the predetermined negative voltage applied to the p ⁺ element isolation region 6. .

By this refresh operation, the p base region 9 is brought into a completely initial state, and thereafter, the above-mentioned storage, read and refresh operations are repeated.

Thus, since a positive pulse is applied to the polysilicon 14 at the time of reading and a negative pulse is applied at the time of refreshing to turn on the p-MOS transistor, the above operation does not interfere.

By the way, when a strong light hits a part of the photoelectric conversion device in which the photosensor cells are arranged as shown in FIG. 3, the p base region 9 of the photosensor cell in that part is forward biased with respect to the n ⁺ emitter region 15. Then, the signal is read out to the emitter side and the blooming phenomenon occurs.

In order to prevent this, the polysilicon 14
Of the p base region 9 near the zero electric field, that is, before the signal is read to the emitter side.
It may be set so that the p-MOS transistor becomes conductive.

By setting the potential of the polysilicon 14 in this way,
Before the p base region 9 and the n ⁺ emitter region 15 are in the forward bias state, the p-MOS transistor becomes conductive and excess charges flow out to the p ⁺ element isolation region 6 side to prevent the blooming phenomenon. .

FIG. 4 is a circuit diagram of this embodiment. However, although the case where the number of pixels is 2 × 2 = 4 is taken as an example here, a circuit having an arbitrary number of pixels n × n can be easily configured from the circuit of FIG.

In the figure, each of the optical sensor cells E _{11 to} E ₂₂ is shown in FIG. 2 (o).
And has the configuration shown in FIG. That is,
A capacitor Cox 302 is formed by the p base region 9 of the bipolar transistor 301 and the polysilicon 14 that is opposed to the oxide film 10 in between, and the p base region 9 and p ⁺
P-MO by element isolation region 6 and polysilicon 14
The S transistor 303 is formed. In the present embodiment, the polysilicon 14 serves as one electrode of the capacitor Cox 302 and the gate of the p-MOS transistor 303, but it can be separately configured as in the conventional example (FIG. 1).

Each electrode 17 of the optical sensor cells E ₁₁ and E ₁₂ is connected to the first parallel output terminal of the shift register A via a switching transistor (hereinafter referred to as SWT) 304, and further connected to a terminal T ₃ via an SWT 305. Has been done.

The electrodes 17 of the optical sensor cells E ₂₁ and E ₂₂ are SWT30
It is connected to the second parallel output terminal of the shift register A via 6 and is further connected to the terminal T ₃ via SWT307.

The gate terminals of the SWTs 304 and 306 are the terminals T ₁
In addition, the gate terminals of the SWTs 305 and 307 are connected to the terminal T ₂ .

The emitter electrode 19 of each bipolar transistor 301 of the photosensor cells E ₁₁ and E ₂₁ is connected to the output terminal via the SWT 308, and is further grounded via the SWT 309.

Each emitter electrode 19 of the photosensor cells E ₁₂ and E ₂₂ is
Connected to the output terminal via SWT310, and SWT31
It is grounded through 1.

The gate terminals of the SWTs 308 and 310 are connected to the first and second parallel output terminals of the shift register B, respectively, and the gate terminals of the SWTs 309 and 311 are connected to the terminal T ₄ .

A predetermined negative voltage V _BB is applied to the source region of the p-MOS transistor 303 of each photosensor cell, that is, the p ⁺ element isolation region 6, and a predetermined positive voltage is applied to the collector electrode 21 of the bipolar transistor 301 of each photosensor cell. V _CC is applied.

Moreover, a voltage is applied to each of the terminals T _{1 to} T ₄ at a predetermined timing to turn on the corresponding SWT.

A shift pulse is input to the shift registers A and B at a predetermined timing, and a high level (positive voltage V _R ) is sequentially output from each parallel output terminal.

The operation of the circuit of this embodiment having such a configuration will be briefly described.

First, the SWTs 304, 306, 308, and 310 are turned off, and the SWTs 305, 307, 309, and 311 are turned on, and a negative voltage pulse for refreshing is applied to the terminal T ₃ . As a result, the all-optical sensor cell E ₁₁
The refresh operation of the ~E ₂₂ is performed.

Subsequently, the SWTs 305 and 307 are turned off, and the charge accumulation operation is performed. As a result, optical information at that location is stored in each p base region 9.

Next, the SWTs 309 and 311 are turned off, the SWTs 304 and 306 are turned on, and the operation of sequentially reading the accumulated information is performed.

First, by setting the first parallel output terminal of the shift register A to a high level, a positive voltage V _R is applied to each electrode 17 of the photosensor cells E ₁₁ and E ₁₂ , and the information stored in the p base region is displayed. Read to the emitter side. Subsequently, the first and second parallel output terminals of the shift register B are sequentially set to high level, and the SWT308 and SWT310 are sequentially turned on. By this operation, the information stored in the photo sensor cells E ₁₁ and E ₁₂ is sequentially output to the outside.

Next, the second parallel output terminal of the shift register A is set to a high level and the shift register B is operated as described above, so that the information stored in the photosensor cells E ₂₁ and E ₂₂ is similarly sequentially output to the outside. Output.

When the reading is completed in this way, the above-described refresh operation is performed, and thereafter, the accumulation, reading, and refresh operations are repeated.

〔The invention's effect〕

As described above in detail, in the method of manufacturing a semiconductor device according to the present invention, the distance between the element isolation region and the intermittence electrode region of the semiconductor transistor can be accurately determined in a self-aligned manner. The channel length of the insulated gate transistor having the region as the main electrode region can be made uniform.

Therefore, the threshold voltage of the insulated gate transistor can be made uniform, and the potential of the control voltage region can be reliably fixed at a proper time.

[Brief description of drawings]

FIG. 1 (a) is a plan view of a conventional photoelectric conversion device, FIG. 1 (b) is a sectional view taken along the line AA ', and FIGS. 2 (a) to (o) are manufacturing semiconductor devices according to the present invention. FIG. 3 is a plan view of a device manufactured by this embodiment, FIG. 3 is a plan view of the device manufactured by this embodiment, and FIG. 4 is a circuit diagram for explaining the operation of the device manufactured by this embodiment. 1 ... Substrate, 4 ... Epitaxial layer, 6 ... Element isolation region,
9 ... Base region, 10 ... Oxide film, 13, 14 ... Polysilicon (for electrodes), 15 ... Emitter region.

Claims (3)

[Claims] 1. A control electrode region made of a semiconductor of a first conductivity type capable of accumulating carriers by receiving light energy, and first and second semiconductors of a second conductivity type different from the first conductivity type. A main electrode region, a phototransistor, a device isolation region made of a semiconductor of the first conductivity type, the control electrode region and the device isolation region as main electrode regions, and for refreshing the phototransistor. In a method for manufacturing a semiconductor device including an insulated gate transistor, a mask material having a predetermined length is formed on the control electrode region and the control electrode region after forming the control electrode region and the element isolation region in a common substrate. A semiconductor region of the same conductivity type as that of the control electrode region and the element isolation region is formed in the substrate by being disposed between the element isolation region and the mask material as a mask. Method of manufacturing a semiconductor device and determines the channel length of the insulated gate transistor Te. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the phototransistor is a bipolar transistor. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the semiconductor region includes an ion implantation step and a heat treatment step.