JPS6112063A - Photoelectric conversion device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a high-speed, high-sensitivity, high-density and high-output photoelectric conversion device having an excellent interelement uniformity and having little dispersion of sensitivity characteristic by a method wherein, in an electrostatic induction transistor type photoelectric conversion device, the source region is constituted in a tunnel injection structure. CONSTITUTION:A high-resistance epitaxial growing layer 13 is provided on an n<+> type substrate 2 and a field oxide film 7 is provided by performing a wet oxidation. Then, regions for the gate of the SIT photoelectric conversion device and the tunnel injection part are decided according to the first mask-alignment, apertures are provided in the field oxide film 7 by performing an etching and very thin oxide films 15 are formed by performing a dry oxidation. Then, conductive layers 14 at a region, which is to become the source part in a tunnel injection structure, are left according to the second mask-alignment and the remaining parts are removed by performing an etching. An ion- implantation of boron B is performed in the whole surface and after an Si layer is formed on the whole surface, a thermal treatment of ion-implantation is performed. The surface of the Si layer on a p<+> control gate diffusion region 6 is made to expose according to the third mask-alignment, then an Si3N4 film 10 is formed on the whole surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a photoelectric conversion device employing a static induction transistor structure and a method for manufacturing the same.

[Prior art and its problems] Conventionally, as a transistor type photoelectric conversion device.

Bipolar type and field effect type are available in practical use.

A recently proposed SIT (Stati
There is a cInduction Transistor (electrostatic induction transistor) type image sensor (IEEE
Trans on Electron Devices
Vol, Il! D-26, No. 12 (Dec., 19
79)pp, 1970-1977).

This image sensor uses a static induction transistor as a photoelectric conversion section. A static induction transistor as a photoelectric conversion device will be explained below. The photoelectric conversion within the static induction transistor is mainly.

This is carried out near the second conductivity type region on the second main surface side, and the potential of the second conductivity type region changes in proportion to the amount of incident light, and the extremely thin oxidation A current flowing between a first main electrode region made of a conductive layer formed via a film and a second main electrode region on the second main surface side is controlled. That is, the current flowing between the first main electrode region and the second main electrode region is controlled in proportion to the amount of incident light. Regarding the specific manufacturing method, please refer to the patent application
The invention is disclosed in Japanese Patent Application No. 7-218589, Japanese Patent Application No. 57-218590, and Japanese Patent Application No. 57-218591. The above-mentioned Japanese Patent Application No. 57-218589 relates to a method of manufacturing an SIT image sensor having the simplest planar structure, and FIG. 2 shows the main parts of the manufacturing process. The prior art will be explained below based on the drawings.

In fig.

(A) After forming an n-buried layer 2 on an n-substrate or a p-substrate, high-resistance n-epitaxial growth 3 (
boron B is deposited (deposited) by ion implantation or diffusion into the field oxide film 7 and control gate 6 (which may be either n - + P -tl).
(posit) and drive-in (drive-in)
)do.

(B) Predetermined source portion 5 by mask alignment process
A window is opened, and phosphorus P or arsenic As doped polysilicon 8 or non-doped polysilicon 8 is deposited using CVD (Chemical Vapor Deposits).
Drive-in is performed by doping with Ririn P or arsenic As deposited by one of the vapor phase growth techniques.

(C) After etching leaving the source electrode part 8 and the wiring part 8 made of polysilicon by mask alignment, PSG (Phospho-5ilicate Gl) is etched.
As; phosphosilicate glass) film 9 is formed by CVD.

(D) After etching and removing the field oxide film 7 and PSG film 9 on the upper part of the control gate portion 6 by mask alignment, CVD of the nitride film 10 and CVD of the transparent electrode SnO 211 are performed to form a storage layer on the upper part of the control gate 6. MIS(Metal In5u1.a
torSemiconductor 5tructor
e; metal electrode-thin insulator-semiconductor structure) form a capacitor.

(E) Only the SnO2 film 11 on the upper part of the control gate 6 and the wiring part is left by mask alignment and etching process, and a contact hole to the shielding gate part 4 is opened.

Finally, AQ deposition and wiring etching are performed. Aμ
Electrode 12 is in contact with the SnO2 electrode.

The AQ electrode 13 is an AQ electrode for contact with the shielding gate 4.

As is clear from the above explanation, patent application No. 57-21858
In the manufacturing method disclosed in No. 9, passivation (Pa
7 except for ssivat, ion; surface stabilization technology)
Two masks are required, and the n+ source portion 5 and the p+ gate portions 4 and 6 are formed using separate masks in separate mask alignment steps.

For this manufacturing method, the present inventors have developed an n+ source portion 5
In addition, a self-line process for SIT image sensors in which a single mask is used to define the p+ gate portion was proposed and disclosed in Japanese Patent Application No. 57-218590. The final cross-sectional structure is shown in FIG.

Next, the manufacturing process of the device shown in FIG. 3 will be briefly described. After forming the n1 buried layer 2 on the n-substrate or on the p-substrate 1, the n-high resistance epitaxial growth 3 is performed.
(This can be any n − + P − +1), then L
OCO5 (Localized Oxidation
of 5ilicon: selective oxidation structure of a silicon substrate using a silicon nitride film) technique to form regions to become the source portion and gate portions 4 and 6 of the SIT. That is, the regions other than those to become the source portion 5 and gate portions 4 and 6 of the SIT are covered with a thick oxide film 7 made of LOGO 5. After the mask alignment process, the Si 3N 4 film on the regions 4 and 6 that will become the gate portion is removed,
Gate portions 4 and 6 of the SIT are formed by boron B ion implantation and a heat treatment process.

Next, after a mask alignment process, the Si s Na film and the Si02 film on the region 5 that is to become the source part are removed, and n+ doped polysilicon 8 is formed on the entire surface by CVD technology, and the n+ source diffusion region is formed by a heat treatment process. form 5. The n+ polysilicon 8 is etched to form a wiring portion. Next, after growing the PSG film by CVD, the Si on the control gate region 6 is removed by a mask alignment process.
Remove the O2 film. Si s Na of predetermined thickness is
After forming the entire surface using VD technology, the SnO2 film 11 is further coated with C.
VD grows. Above Sn021.1/Si 3N 41
A MIS structure is formed on the control gate 6 using a 0/5i(p'')6 structure. After etching the 5nOz film 11, a contact hole to the shielding gate portion 4 is opened, and sintering is performed by 50% evaporation. Excluding passivation, AQ electrode wiring up to 1.2.13 is 7
Two masks are required.

In the manufacturing process of the SIT image sensor pixel having the structure shown in FIG. Since the positions of the gates 4 and 6 are defined by the first mask, variations between the sources and gates can be suppressed compared to the manufacturing method shown in FIG. However, the number of masks required in both the method of FIG. 2 and the method of FIG. 3 is seven, because in the method of FIG. gate 4,
This is because the diffusion steps for 6 and the source 5 are performed using separate masks, and the same mask is used later when etching the SnO2 film 11 on the control gate 6, so the total number of masks is There is. Since the formation of the gate portions 4 and 6 and the formation of the source portion 5 are performed in separate processing steps, there is a drawback that the structure is susceptible to variations in characteristics.

The present inventors have further disclosed another method of manufacturing an SIT image sensor in Japanese Patent Application No. 57-218591.

The cross-sectional shape of the final device is shown in Figure 4(A).
Shown in (B). A feature of the manufacturing method shown in this figure is that the LOCO is used to form the shielding gate portion 4 deeply.
5, or plasma etching + LQCO5 technology is used, and in Fig. 4(A), the p+ gates 4 and 6 are deeply diffused into the shielding gate part 4 and control gate part 6 by LDCO3 technology. The position of the n+ source region 5 is determined by masking and alignment. That is, it is not self-aligned (self-aligned). In the structure shown in FIG. 4(B), the P+ gate diffusion 4 is formed deeply in the shielding gate portion 4 using plasma erasure, etching and LOCO5 techniques, and the positioning of the p1 control gate 6 diffusion and the n+ source portion 5 are The positioning of the diffusion is performed by mask alignment using separate masks.

In FIG. 4(A), the total mask diffusion is 7 masks excluding passionvation, and in FIG. 4(B) it is 7 to 8 masks.

As explained above, there are four methods of manufacturing an SIT image sensor that have been disclosed and proposed by the present inventors. In the manufacturing method shown in Figure 2, the gate and source diffusions of the SIT are positioned through a mask alignment process using separate masks, so when a large number of cells are arranged in a matrix, the sensitivity characteristics between pixels are The disadvantage is that it varies widely. However, the final structure of the device is planarized, which is advantageous in terms of increasing light receiving efficiency.

In the manufacturing method explained in Fig. 3, the positions of the gate and source of the SIT are defined by the first mask, so dimensional variations are much suppressed compared to the method shown in Fig. 2. However, there is a thick oxide film created by the LOCOS process between the SIT gate and source.
Poor light transmission to the SIT channel. Also, L.O.
The device surface has an uneven shape due to the influence of the oxide film caused by CO5, and the uneven shape causes light to be scattered, resulting in a structure in which it is difficult to take light into the device effectively. Furthermore, since gate diffusion and source diffusion are ultimately performed using separate mask alignment, the total number of masks is seven, which is the same as in the case of FIG. In the manufacturing method explained in FIG. 4(A), at the same time as the oxidation of the LOCO5 technology,
Since the P+ gate is diffused under the thick oxide film of cos, the light-receiving surface is uneven, and at the same time the source region is positioned by mask alignment. This has a large negative effect on the characteristics of solid-state imaging devices, which are made up of a plurality of cells arranged. Furthermore, in the SIT image sensor manufacturing method explained in FIG. 4(B), the positioning of the control gate diffusion and the source diffusion is performed by a mask alignment process, which causes variations in channel width dimensions and source/source diffusion.
Dimensional variations between gates are likely to occur, and when a plurality of cells are arranged in a matrix, the characteristics of each pixel will vary greatly.

As explained above, in the methods shown in FIGS. 2, 4 (A), and (B), the gate and source positions are determined separately in the mask alignment process, resulting in variations in characteristics between devices. There were drawbacks.

In addition, the method shown in FIG. 3 has the disadvantage that the device surface becomes uneven and the source and gate diffusions are performed separately, resulting in variations, resulting in poor light absorption efficiency.

Furthermore, when considering the total number of masks, the number of masks is 7 to 8 in all of the preceding examples shown in FIGS. 2, 3, and 4 (A) and (B).

[Object of the Invention] The present invention provides a novel SIT which eliminates the drawbacks of the above-mentioned prior art.
The purpose of the present invention is to provide a photoelectric conversion device and a method for manufacturing the same.

[Summary of the Invention] Therefore, the present invention is characterized in that a static induction transistor type photoelectric conversion device has a source region having a tunnel injection structure.

[Embodiment of the invention] FIGS. 1(A) to (G) show SIT according to an embodiment of the present invention.
Photoelectric conversion device wIII! It represents each manufacturing process of the manufacturing method. Hereinafter, the manufacturing steps (A) to (G) will be explained in order.

(A) A high-resistance epitaxial growth layer 3 is formed on the n+ substrate 14 to a thickness of about 5 .mu.I11 to 10 .mu.m. The conductivity type of this epitaxial growth layer 3 may be n + P-. Alternatively, it may be one layer. Next, wet oxidation is performed on the entire surface. The thickness of this field oxide film 7 is 5000 mm.
Approximately 8,000 people.

Next, a first mask alignment step is performed to determine the gate and tunnel injection portion regions of the SIT photoelectric conversion device, and a window is opened in the field oxide film by etching. Next, an extremely thin oxide film 15 is formed over the entire surface by dry oxidation. The thickness of the oxide film 15 is about 10A to 100A. A thermal nitride film may be used instead of this extremely thin oxide film 15.

Furthermore, before forming this extremely thin oxide film 15, ion implantation may be performed to control the final impurity concentration value of the channel region immediately below it.

Next, a conductive layer 14 of polysilicon (doped or non-doped), refractory metal (No, W, etc.), silicide, or the like is formed on the entire surface using techniques such as electron beam evaporation and snot to ivy.

(B) Next, in a second mask alignment step, the conductive layer 14 in the region that will become the source portion of the tunnel injection structure is left, and the remaining portion is removed by etching. Thereafter, using the conductive layer 14 as a mask, the extremely thin oxide film is etched to open a window in the area that is to become the gate area and expose the Si surface in that area.

Next, boron B ions are implanted over the entire surface to form p+ ion implantation layers (hereinafter referred to as p+ diffusion layers) 4 and 6 in the shielding gate portion 4 and control gate portion 6.

(C) Next, the entire surface is coated with PSG film or CVD5iO film.
After forming the insulating film 9 to a thickness of about 3,000 layers, the heat treatment for ion implantation performed in (B) is performed. p+
The impurity density near the surface of the diffusion layers 4 and 6 is IXIO19c
The diffusion depth of the p-type diffusion layers 4 and 6 is approximately 1 μm to 5 μm.

(D) Next, a third mask alignment process is performed to form a window in the control gate region 6 through the PSG film (
Alternatively, the CVD5i02 film) 9 is plasma etched to expose the Si surface above the p+ control gate diffusion region 6.

(E) Next, the entire surface is coated with Si 3N using CVD technology.
4 films 10 are formed. Thickness is approximately 500A ~ 1000A
It should be about λ. After forming the CVDSi s Na film, a transparent electrode 11 such as a SnOa or ITO (indium oxide, tin oxide) film is further formed using a technique such as CVD to form a control gate region. A Sn02 transparent electrode 11 is formed using a technique such as CVD to form a control gate region. The method for forming the 5n (12 transparent electrode 11a) is thermal decomposition of 5nCQi using 5bCQ3 as a doping source in an N2 carrier (400 to 60
0° C.) is used.

(F) SnO in the area above the control gate area
2 part 11 and the wiring part Sn0211 are left
After plasma etching the n02 electrode 11, the shielding gate portion 4. Further, a contact hole is opened to the conductive layer 14 (fourth and fifth mask alignment steps, however, the opening portion of the contact hole to the conductive layer 14 is not shown). In the plasma etching of Sn02, CCj2a gas is used at 0.1 torr. Further, an AQ electrode is formed on the entire surface by vapor deposition, and is used for contact with the conductive layer 14 that becomes a predetermined source electrode [1 wiring portion (not shown) and the Aρ wiring portion 13 for contacting the shielding gate 4 and the Sn0211
Etching is performed at 80, leaving the AQ wiring portion 12 for contact with. Furthermore, after sintering, Si s N
A final passivation step such as CVD growth of four films is performed (sixth and seventh mask alignment steps).

Next, the operation of the photoelectric conversion device manufactured through the above steps (A) to (F) will be explained using FIG. 1(F) showing the final cross-sectional shape of the device.

First, it is assumed that there is no accumulation of photocarriers in the p+ region of the control gate 6 in the absence of light. In order to use a static induction transistor as a photoelectric conversion device, the impurity density of the n-region 16 which becomes a channel is approximately lXl0''
'cm-'' below is the gate.

The impurity density in the source and drain regions is approximately lX
101'cm' or more. In order to prevent drain-source current from flowing even when the gate voltage is Ov, the dimensions and gate spacing are selected such that the gap between the gates and the channel are already depleted with only the diffusion potential. The potential distribution in the device thickness direction directly under the p-region of the control gate 6 has a high potential on the surface side (p-layer side), which forms a junction where a diode is formed between the gate region 4 and the Si n-layer substrate 14. ing. In addition, the source region 14
The potential distribution in the device thickness direction directly under the drain 17
If no voltage is applied to source 14 and source 14, the potential has a maximum value at a certain point between both regions (referred to as the true gate). Therefore, source 14 and drain 1
Even if a voltage is applied between 7 and 7, the tunnel current, that is, the drain current, does not flow because it is pinched off by the depletion layer formed by the barrier. Also, source 14 and drain 1
Even if a pulse voltage is applied to the gate electrode 11 without applying a voltage between the gate electrodes 7 and 7, no flow occurs (this operating state is called "normally off" and the opposite state is called "normally on"). Of course, by changing the element dimensions, it is possible to prevent current from flowing even if light is irradiated with either the gate pulse voltage or the source-drain voltage applied, or it is possible to make it flow. You can also do it. That is, in a photoelectric conversion device using an electrostatic induction transistor, with a voltage applied between the source 14 and the drain 17, the true gate potential formed directly below the source 14 is determined to a certain value. In this state, the control gate 6 is irradiated with light, and holes as one of the photoexcited charges are accumulated in the p+ region immediately below in accordance with the amount of light, and the potential of the gate 6p+ region changes depending on the amount of light. Therefore, the true gate potential is lowered from the previous state according to the change in gate potential, and as a result, the potential barrier is crossed for the first time and a drain-source current flows. After that, in order to perform the next photometry, a pulse voltage is applied to the gate electrode 11, and the gate electrode 11 and the Si s N 4 film 1
A voltage corresponding to the gate capacitor formed with 0, etc. is applied, and furthermore, in terms of an equivalent circuit with the gate capacitor, a diode junction capacitance (
Since CD8) is connected, the applied pulse voltage is applied to the gate capacitor and the diode junction capacitance (CD8).
A part of the voltage divided by S) is applied to the terminal voltage of the diode. As a result, since the diode is charged, the gate region 6p returns to its initial state, and photometry can be carried out repeatedly. Furthermore, by externally applying a voltage to the shielding gate 4 region, the current flowing through the source 14 and drain 17 can be freely controlled.

The above is an explanation of the operation of the photoelectric conversion device according to the present invention. According to the method for manufacturing the photoelectric conversion device of the present embodiment described above, diffusion holes in the source region can be formed by adopting a tunnel injection structure for forming the source region. The manufacturing process becomes extremely simple, as it is no longer necessary.

At the same time, the area occupied by the source region and gate region can be minimized to the limit of microfabrication technology. Also, the number of masks is saved by one compared to the prior art manufacturing process shown in FIG. In addition, the source region and gate region having a tunnel implantation structure are determined at the same time by the second mask process, and since the diffusion (ion implantation) to form the transistor is performed only - times, the SIT portion constituting the device is The channel dimensions and the distance between the gate region 4.6 and the source region are all made uniform. Therefore, the characteristics of the tunnel injection type SIT photoelectric conversion device manufactured according to this example are made uniform, and the variation in output characteristics with respect to the received light intensity is suppressed to an extremely low level, and high yield can be expected from an industrial perspective.

Furthermore, the Si surfaces are on the same plane and are flattened, so that when light is received, the proportion of scattering due to unevenness on the semiconductor surface is reduced compared to conventional manufacturing methods.

Furthermore, it is extremely simple compared to conventional manufacturing methods, and in particular eliminates the need for source diffusion, further increasing the density that SIT has traditionally had.

High output is possible because the source length can be made longer in the same area.

In the above embodiment, a tunnel injection gate accumulation type SIT photoelectric conversion device having a gate divided into a shielding gate 4 and a control gate 6 has been described. A ring may also be used. In this case, only the control gate region 6 becomes the gate region of the SIT, so that the SIT has a structure in which the control gate region 6 surrounds the tunnel injection region. However, it is clear that the same manufacturing process as that of the present invention can be applied.

Further, in the above embodiment, an example was shown in which the insulating film 9 such as a PSG film or a CVD5n02 film was formed so that the source electrode wiring and the gate electrode wiring could intersect. It is clear that the manufacturing process can be further simplified by preventing the two wires from intersecting each other.

Furthermore, it is clear to those skilled in the art that the conductivity types of the respective parts in FIG. 1 of the embodiment described above may be completely opposite.

[Effects of the Invention] As described above, according to the present invention, a tunnel injection structure is adopted for the source region, the source region and the gate region are determined using the same mask, and the diffusion process is performed only once. As a result, the uniformity between elements is extremely excellent, and there is almost no variation in sensitivity characteristics, resulting in a high yield.As the device after manufacturing is flattened, it has good light absorption efficiency, high speed, high sensitivity, and high density. A high-output photoelectric conversion device can be obtained.

[Brief explanation of drawings]

FIGS. 1(A) to (F) show an SIT according to an embodiment of the present invention.
Explanatory diagram of the manufacturing process of the photoelectric conversion device, Figures 2 (A) to (
E) is an explanatory diagram of the manufacturing process as a precedent example of a gate accumulation type SIT photoelectric conversion device, Figures 3 and 4 (^),
(B) is a structural cross-sectional view showing another example of a gate accumulation type SIT photoelectric conversion device. 2...N-child substrate, 3...High resistance epitaxial layer,
4... Shielding gate region of divided gate SIT, 6... Control gate region of divided gate SIT. 7... Field oxidation electrode, 9... Insulating film of PSG or CVD5iO2 film, 11... Transparent electrode, 12
... Afi electrode part, 13 ... AQ contact electrode of shielding gate, 14 ... conductive film that becomes source electrode, 15 ... tunnel injection region with extremely thin oxide film, 16 ... channel region, 17... Drain electrode. Figure 7 (B) Figure 7 Figure 2 (A) (B) Figure 2 Figure 3

Claims (2)

[Claims] (1) A photoelectric conversion device of a static induction transistor type formed on a substrate, characterized in that a source region has a tunnel injection structure. (2) In a method of forming a static induction transistor type photoelectric conversion device on a substrate, the steps include forming a high resistance epitaxial growth layer on the substrate, forming a field oxide film thereon, and a first mask alignment step. a step of opening a window in a region where a transistor is to be formed, forming a thin insulating film there, and then forming a conductive layer over the entire surface; and a step of opening a window in a region where a gate of the transistor is to be formed through a second mask alignment step; A step of implanting ions into the region where the window has been opened, and a step of forming an insulating film to a predetermined thickness over the entire surface, and then activating the ion implantation layer to form a diffusion region that will become the electrode of the transistor. A method for manufacturing a photoelectric conversion device, comprising: