JPH0430752B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method of manufacturing a solid-state imaging device, and particularly relates to a gate storage type static induction transistor (hereinafter abbreviated as SIT) type related to a simplified self-aligned planar process. The present invention relates to a method of manufacturing an image sensor.

[Description of Prior Art] Conventionally, there are CCD type and MOS type solid-state imaging devices that have been put into practical use. Recently, there is a SIT type image sensor proposed by the present inventor (IEEE
Trans on Electron Devices Vol.ED−26, No.12
(Dec.1979) PP.1970-1977).

The present inventors have also made various basic applications in matrix operation as applications in conjunction with the proposal of the basic structure. Regarding the specific manufacturing method, please refer to Japanese Patent Application No. 57-218589 and Japanese Patent Application No. 57-218589.
The invention is disclosed in No. 218590 and Japanese Patent Application No. 57-218591. The above-mentioned Japanese Patent Application No. 57-218589 relates to a method for manufacturing a SIT image sensor having the simplest planar structure, and FIG. 2 shows the main parts of the manufacturing process. The prior art will be explained below based on the drawings. In Fig. 2, (A) After forming an n ⁺ buried layer 2 on an n ⁺ substrate or a p ^- substrate 1, high resistance n ^- epitaxial growth 3 (this can be any of n ^- , p ^- , i). good)
Then, boron B is deposited and driven into the field oxide film 7 and control gate 6 portions by ion implantation or diffusion.

(B) A window is opened in a predetermined portion of the source 5 through a mask alignment process, and phosphorus or As-doped polysilicon 8 or non-doped polysilicon 8 is coated with CVD (Chemical Vapor
Phosphorus P deposited using
Or do a drive-in with arsenic doping.

(C) After etching the polysilicon 8 in the source electrode portion and wiring portion by mask alignment, a PSG (Phospho-Silicate Glass) film 9 is formed by CVD.

(D) After etching and removing the field oxide film 7 and PSG film 9 above the control gate 6 portion by mask alignment, the nitride film 10 is removed.
CVD and transparent electrode CVD of SnO ₂ film 11 and MIS for storage in control gate 6 part
(Metal Insulator Semiconductor structure)
form a capacitor.

(E) Control gate 6 section and wiring section
Only the SnO ₂ film 11 is left by the mask alignment and etching process, and a contact hole is opened to the shielding gate 4 portion. Finally Al
Perform vapor deposition and etching for wiring. The Al electrode 12 is in contact with the electrode SnO ₂ film 11 . The Al electrode 13 is an Al electrode for contact with the shielding gate 4.

As is clear from the above explanation, the patent application
The manufacturing method disclosed in No. 218589 requires seven masks excluding passivation, and also requires 5 masks for n ⁺ source, 4 p ⁺ gate,
The six portions are each formed using separate masks through a mask alignment process. For this manufacturing method, the present inventors use a single mask to define the n ⁺ source 5 portion and the p ⁺ source 4 and 6 portions.
We proposed a self-alignment process for SIT image sensors and disclosed it in Japanese Patent Application No. 1983-218590. The final cross-sectional structure is shown in FIG.

Next, the manufacturing process of the device shown in FIG. 3 will be briefly described. After forming an n ⁺ buried layer 2 on the n ⁺ substrate or p ^- substrate 1, after n ^- high resistance epitaxial growth 3 (this can be any of n ^- , p ^- , i), LOCOS (LOCaliged Oxidation
of Silicon) technology to simultaneously define the regions that will become the source 5 portion and the gates 4 and 6 portions of the SIT. That is, the source 5 part of SIT, the gate 4,
The area other than the area that should become part 6 is covered with a thick field oxide film 7 made of LOCOS. After the mask alignment process, the Si ₃ N ₄ film on the regions to become the gates 4 and 6 is removed, and the gates 4 and 6 of the SIT are formed by boron B ion implantation and a heat treatment process.

Next, after a mask alignment process, the Si ₃ N ₄ film and SiO ₂ film on the region that is to become the source 5 portion are removed, n ⁺ doped polysilicon 8 is formed on the entire surface by CVD technology, and n + doped polysilicon 8 is formed by a heat treatment process. ⁺ source 5
Form a diffusion region. The n ⁺ doped polysilicon 8 is etched to form a wiring portion. next,
After growing the PSG film 9 by CVD, the SiO ₂ film on the control gate 6 region is removed by a mask alignment process. After Si ₃ N ₄ 10 of a desired thickness is formed on the entire surface by CVD technology, a SnO ₂ film 11 is further grown by CVD. An MIS structure is formed on the control gate 6 using the SnO ₂ 11/Si ₃ N ₄ 10/Si(p ⁺ )6 structure. After etching the SiO ₂ film 11, a contact hole is opened to the shielding gate 4 portion, and Al vapor deposition and sintering is performed. Excluding passivation, seven masks are required up to the Al electrode wirings 12 and 13.

In the manufacturing process of the SIT image sensor pixel having the structure shown in FIG. 3, the positions of the source 5 and gates 4 and 6 are defined by the first mask.
Compared to the manufacturing method shown in FIG. 2, variations between the source and gate can be suppressed. However, the second
In the method shown in the figure and the method shown in Fig. 3, the number of required masks is 7. In the method shown in Fig. 3, the positions of the gates 4, 6 and source 5 of the SIT are defined by the first mask. However, gate 4,
This is because the diffusion steps of 6 and the source 5 are performed using separate masks, and the same mask is used later when etching the SnO ₂ film 11 on the control gate 6, so the total number of masks is 7. It has become one piece. In this case, since the formation of the gates 4 and 6 and the formation of the source 5 are performed in separate processing steps, there is a drawback that the structure is susceptible to variations in characteristics.

The present inventors have further disclosed another method for manufacturing an SIT image sensor in Japanese Patent Application No. 57-218591. The cross-sectional shape of the final device is shown in FIGS. 4A and 4B. The feature of the manufacturing method shown in this figure is that the shielding gate 4 portion is formed deeply.
LOCOS or plasma etching + LOCOS
Figure 4A shows an example in which p ⁺ gates 4 and 6 are deeply diffused in the shielding gate 4 and control gate 6 parts using LOCOS technology, and the n ⁺ source 5 The location of the region is determined by mask alignment. That is,
It is not self-aligned. In the structure shown in FIG. 4B, the shielding gate 4 portion is plasma etched and
The p ⁺ gate 4 diffusion is formed deeply using LOCOS technology, and the positioning of the p ⁺ control gate 6 diffusion and the positioning of the n ⁺ source 5 portion diffusion are performed by mask alignment using separate masks.

In FIG. 4A, the total number of masks is seven, excluding passivation, and in FIG. 4B, it is seven to eight.

As explained above, there are four methods of manufacturing SIT image sensors that have been disclosed and proposed by the present inventors. In the manufacturing method shown in Figure 2, the gate and source diffusions of the SIT are positioned through a mask alignment process using separate masks, so when arranging a large number of cells in a matrix, the sensitivity characteristics between pixels There are drawbacks that greatly affect variation. However, the final structure of the device is planarized, which is advantageous in terms of increasing the light reception efficiency.

In the manufacturing method explained in Figure 3, the positions of the gate and source of the SIT are defined by the first mask, so dimensional variations are much smaller than in the method shown in Figure 2. However, there is a thick oxide film created by the LOCOS process between the SIT gate and source, and the light transmittance to the SIT channel is poor. In addition, the device surface has an uneven shape due to the effect of the oxide film caused by LOCOS, and light is scattered due to the uneven shape, resulting in a structure that makes it difficult to effectively introduce light into the device. Furthermore, since gate diffusion and source diffusion are ultimately performed using separate mask alignment, the total number of masks is 7, which is the same as in the case of FIG. 2.

In the manufacturing method explained in FIG. 4A,
At the same time as the oxidation of LOCOS technology, p ⁺ gate diffusion is performed under the thick oxide film of LOCOS, so the light-receiving surface is uneven.At the same time, the source region is positioned by mask alignment, and the source diffusion region The variations in the positions of the elements greatly affect the variations in the characteristics of the final arrayed devices.

Furthermore, in the SIT image sensor manufacturing method explained in FIG. 4B, the control gate diffusion and source diffusion positions are performed by a mask alignment process, so variations in channel width dimensions and between source and gate dimensions are avoided. Variations are likely to occur, and when a plurality of cells are arranged in a matrix, the characteristics of each pixel will vary greatly.

As explained above, in the prior art method shown in FIGS. 2 and 4A and B previously disclosed by the present inventors, the gate and source positions are determined separately in the mask alignment process, so there are multiple When individual cells were integrated, there was a problem in that the characteristics of each pixel varied.

Further, in the method shown in FIG. 3, the device surface becomes uneven and source diffusion and gate diffusion are performed separately, resulting in variations and poor light absorption efficiency.

Furthermore, when considering the total number of masks, the preceding examples of FIGS. 2, 3, and 4 A and B are all 7 to 8 masks, and depending on the combination with the scanning circuit, this number may vary depending on the combination with the scanning circuit. It was inevitable that the number would be higher than this.

In addition, devices realized using conventional manufacturing methods have uneven surfaces due to LOCOS,
Because it is not a self-aligning process, variations in the sensitivity characteristics of each pixel tend to occur, making it unsuitable for large-capacity image sensors (up to 500 x 700 pixels), where uniformity is particularly important. .

[Object of the invention] The present invention has the following features except for the above-mentioned disadvantages.
It is an object of the present invention to provide a novel method for manufacturing an image sensor that has uniform sensitivity characteristics of each element and has good light absorption efficiency.

[Summary of the Invention] Therefore, the present invention provides a step of forming a buried layer in each transistor formation region on a semiconductor substrate, performing high resistance epitaxial growth, and then forming a field oxide film. In the second mask alignment step, a window is opened in the partial well that separates each transistor region, and in the step of doping with impurities, the second mask alignment step is used to shield the electrostatic induction transistor for forming the light receiving part. A step of forming a non-doped polysilicon film and further an insulating film on the entire surface after opening windows in the areas where the gate, control gate, and source regions are to be formed and the area where the electrodes of the well are to be taken out;
A third mask alignment step leaves the non-doped polysilicon film and insulating film on the portion where the source region of the static induction transistor is to be formed, and removes the other non-doped polysilicon film and insulating film to form the shielding gate, control gate and After doping the portions of the well where the electrode extraction regions are to be formed with impurities, a step of again forming an insulating film over the entire surface and a fourth mask alignment step are performed to form the scanning circuit transistor region and the control gate region of the electrostatic induction transistor. By removing the insulating film on the source region and forming a dry thermal oxide film on the entire surface, and the fifth mask alignment step,
a step of leaving the oxide film in the scanning circuit transistor region and the control gate region of the static induction transistor, removing other oxide films, and forming a doped polysilicon film doped with impurities over the entire surface; and a sixth mask. The alignment process leaves doped polysilicon films on the control gate region of the static induction transistor and the gate region of the scanning circuit transistor, and uses the doped polysilicon as a mask to form windows for the source and drain of the scanning circuit transistor. a step of performing open etching and doping with impurities; and a step of forming electrodes after opening contact holes to the shielding region and the source and drain regions of the scanning circuit transistor through a seventh mask alignment step. The present invention is characterized in that an image sensor is manufactured using the following steps.

[Embodiment of the Invention] FIGS. 1A to 1H show each manufacturing process of an image sensor manufacturing method according to an embodiment of the invention. below,
Each manufacturing process A to H will be explained in order.

(A) Both (111) and (100) plane orientations of the substrate are good.
A common buried layer 22 is formed on the p ^- substrate 21 by diffusion or ion implantation of As or Sb, etc. in a region to become the sensor area of the SIT image sensor and a region to constitute the peripheral scanning circuit. The buried layer 22 has a common electrode around the sensor area or at a predetermined portion. This electrode part is shown in Figure 1A.
Although not shown in the figure, it becomes a common drain region of multiple matrices of the SIT image sensor. The reason for forming such a buried layer 22 is that the driving and scanning circuit for the matrix of the pixel portion of the SIT image sensor is intended to be formed on the same substrate.

Next, a high resistance epitaxial growth layer 23 is grown to a thickness of about 3 μm to 10 μm. The conductivity type of this epitaxial growth layer 23 may be either n ^- or p ^- . Further, it may be an i-layer. Next, perform wet oxidation on the entire surface. The thickness of this field oxide film 24 is approximately 5000 Å to 8000 Å.

(B) In the first mask alignment step, a window is opened in a region for forming a scanning circuit transistor. Next, B ion implantation or thermal diffusion is performed on the entire surface of the well 2 of the scanning circuit transistor.
form 5. When forming this well, an oxide film is
Attach about 2000Å to 4000Å. Further, the surface concentration of the well is about 5×10 ¹⁵ cm ⁻³ .

(C) Through the second mask alignment process, the shielding gate 26 part, control gate 27 part, source 28 part,
Furthermore, a window is simultaneously opened to the electrode extraction portion 29 of the well of the peripheral circuit transistor. Next, a non-doped polysilicon layer 30 is applied to the entire surface.
It is formed using a technique such as CVD, and a PSG film 31 is further formed on the entire surface using a technique such as CVD. The thickness of the polysilicon layer 30 is about 3000 Å to 5000 Å. Instead of PSG film, the same thickness
It may also be a CVDSiO ₂ film.

(D) Through the third mask alignment process, the source 28
The non-doped polysilicon layer 30 and the PSG film 31 on the area where it should become are left, and the other parts of the non-doped polysilicon layer 30 and the PSG film 31 are completely removed. Since this step requires dimensional accuracy, it is performed using a dry process such as plasma etching.

(E) Boron is diffused or ion-implanted over the entire surface again to form p ⁺ diffusion layers in the shielding gate 26 portion, control gate 27 portion, and well electrode extraction portion 29. The impurity density near the surface of these 4, 6, and 14 P ⁺ diffusion layers is about 1×10 ¹⁹ cm ⁻³ .

(F) After forming the PSG film or CVDSiO ₂ film 32 again to a thickness of about 3000 Å on the entire surface, the control gate 27 region, the source 28 region, and the active region 33 of the scanning circuit transistor are coated in the fourth mask alignment step. for opening the window
PSG film (or CVDSiO ₂ film) 31 and
Perform plasma etching of the SiO ₂ film 32,
The Si surface on the p ⁺ control gate 27 diffusion region and the active region 33 of the scanning circuit transistor, and also the polysilicon layer 30 on the source 28 region are exposed.

(G) A SiO ₂ film 34 is formed by dry oxidizing the entire surface. The thickness is approximately 500 Å to 1000 Å. After that, a fifth mask alignment process is performed using the mask used in the third mask alignment process, leaving the dry oxide film 34 on the active region 33 of the scanning circuit transistor and the control gate 27, and removing other dry oxide films. Remove 34 and SIT
The polysilicon surface above the source 28 region is again exposed. Furthermore, n ⁺ such as As or P on the entire surface
A doped polysilicon film 35 is formed using a technique such as CVD. This polysilicon film 3
The thickness of 5 is about 3000 Å to 4000 Å. By the step of forming the polysilicon film 35, a storage capacitor region 36 and a transistor gate 37 region of the MIS structure are formed on the control gate 27 and the active region 33 of the scanning circuit transistor, respectively. In this case, a transparent electrode such as SnO ₂ may be used on the control gate 27 region.

(H) After etching the doped polysilicon 35 on the control gate 27 region and the gate 37 region of the scanning circuit transistor and the doped polysilicon 35 on the wiring part, the other doped polysilicon 35 is etched.
Using the No. 5 film as a mask, the gate oxide film 34 on the region where the source and drain of the scanning circuit transistor are to be formed is removed by etching. Next, by again implanting or diffusing As or P ions over the entire surface, the n ⁺ regions of the source 38 and drain 39 of the peripheral scanning circuit transistor and the source 28 region are formed. The diffusion depth of the source 38 and drain 39 of the scanning circuit transistor is
The diameter is about 1 μm to 2 μm, and the surface concentration is about 1×10 ¹⁹ cm ⁻³ . Also, the diffusion depth of the source 28 region is
It is about 0.1 μm. Next, PSG film 4 is applied again to the entire surface.
0 is formed using a technique such as CVD. after that,
Contact holes are opened to the shielding gate 26 portion, the electrode extraction portion 29 of the well, and the source 38 and drain 39 portions of the scanning circuit transistor (sixth and seventh mask alignment steps). Furthermore, an Al electrode is formed on the entire surface by vapor deposition, and a predetermined shielding gate 26,
Al is etched, leaving the electrode extraction portion 29 of the well, the Al wiring portion 41 for contact with the source 38 and drain 39 portions of the scanning circuit transistor, and the Al wiring portion 42 for contact with the doped polysilicon layer 34 ( 8th mask matching step).

The SIT image sensor of this example is manufactured through the above-mentioned steps, and its operation is similar to that of the conventional example.
- The video signal is read out using the Y address method.

According to the image sensor manufacturing method described above, the positions of the source 28 region and the gate 26 and 27 regions of each pixel of the SIT image sensor are simultaneously determined by the second mask process, and the positions shown in FIG. As shown, the source 28 diffusion region is diffused through the undoped polysilicon, so by limiting the thickness of the undoped polysilicon, the source 28 diffusion region can be formed extremely shallow. This allows the true potential of the SIT that makes up the pixel to be brought closer to the light incident side surface, and as a result, the diffusion depth of the gate 26 and 27 diffusion regions can be made shallower, improving the short wavelength sensitivity of light. can do. Furthermore, gate 26,
Since the 27 diffusion regions are simultaneously diffused, the channel dimensions of the SIT portion constituting each pixel and the distance between the gate 26 and 27 regions and the source region are all made uniform. Therefore, the characteristics of the SIT portion are made uniform, and variations in the output characteristics with respect to the received light intensity between each pixel are suppressed to an extremely low level.

In addition, the Si surfaces of the gate 26, 27 diffusion region and the source 28 diffusion region of each pixel are on the same plane, which reduces scattering due to unevenness on the semiconductor surface when receiving light, compared to the conventional manufacturing method. The light absorption rate decreases and the light absorption rate improves.

Incidentally, in the above embodiment, a gate accumulation method of an SIT image sensor having a divided gate of a shielding gate 26 and a control gate 27 was established. It's okay.
In that case, only the control gate 27 area is
Since this is the gate region of the SIT, the structure of the SIT is a conventional SIT structure in which the control gate 27 region surrounds the source 28 region. However, it is clear that the same manufacturing process as that of the present invention can be applied, and source 28
Since the positioning of the diffusion region and the gate 26, 27 diffusion regions is performed using the same mask, and the heat treatment process associated with the diffusion is also performed at the same time, an image sensor with suppressed variations in characteristics can be obtained.

Furthermore, it is clear that the conductivity types of the respective parts in the above embodiments may be completely opposite, and furthermore, a CMOS circuit structure may be used as the scanning circuit structure.

[Effects of the Invention] As described above, according to the present invention, when the distance between the gate portion and the source portion of the image sensor cell and the dimension of the channel are determined by the same mask, and a plurality of image sensor cells are arranged in a line or matrix, To,
An image sensor with uniform sensitivity characteristics of each pixel is obtained, and since the device is flattened after manufacturing, it has good light absorption efficiency, making it an ideal image sensor especially for manufacturing large-capacity area sensors. A manufacturing method is obtained.

[Brief explanation of drawings]

Figures 1A to 1H are explanatory diagrams of the SIT image sensor manufacturing process according to an embodiment of the present invention, and Figure 2A
~E is an explanatory diagram of the manufacturing process as a conventional example of a gate accumulation type SIT image sensor, and Figures 3 and 4 A and B both use a manufacturing process as another conventional example of a gate accumulation type SIT image sensor. FIG. 2 is a cross-sectional view of the device structure. 21... p ^-substrate , 22... buried layer, 23... high resistance epitaxial growth layer, 24... field oxide film, 25... well, 26... shielding gate, 27... control gate, 28, 38... source, 29... electrode Extraction portion, 30... Non-doped polysilicon layer, 31, 40... PSG film, 32
...CVD oxide film, 33...active region, 34...
Dry oxide film, 35...Doped polysilicon, 3
6... Capacitor region, 37... Transistor gate, 39... Drain, 41, 42... For contact
Al wiring part.

Claims (1)

[Claims] 1. In a method for manufacturing a solid-state imaging device in which a plurality of electrostatic induction transistors for photoelectric conversion and transistors for a scanning circuit are formed on a semiconductor substrate, a buried layer is formed in a region where each transistor is to be formed on the substrate, and a high resistance After epitaxial growth, a step of forming a field oxide film and a first step are performed.
In the second mask alignment step, a window is opened in the partial well that separates each transistor region, and in the step of doping with impurities, the second mask alignment step is used to shield the electrostatic induction transistor for forming the light receiving part. A process of forming a non-doped polysilicon film and an insulating film on the entire surface after opening windows in the areas where the gate, control gate, and source regions are to be formed and the area where the electrodes of the well are to be taken out, and a third mask alignment process. By leaving the non-doped polysilicon film and insulating film on the portion where the source region of the static induction transistor is planned to be formed, the other non-doped polysilicon film and insulating film are removed, and the electrode extraction areas of the shielding gate, control gate and well are removed. After doping the area to be formed with impurities, a step of again forming an insulating film on the entire surface and a fourth mask alignment step are performed to form insulation on the scanning circuit transistor region and the control gate region and source region of the static induction transistor. Through the step of removing the film and forming a dry thermal oxide film on the entire surface, and the fifth mask alignment step, the oxide film in the scanning circuit transistor region and the control gate region of the static induction transistor is left, and other oxide films are removed. The doped polysilicon film on the control gate region of the static induction transistor and the gate region of the scanning circuit transistor is Leaving the polysilicon film and using the doped polysilicon as a mask, etching the source and drain of the scanning circuit transistor to open windows and doping with impurities, and a seventh mask alignment step remove the shielding region and the scanning circuit. 1. A method for manufacturing a solid-state imaging device, comprising the steps of: opening contact holes to source and drain regions of a transistor for use in the semiconductor device, and then forming electrodes.