JPS6184858A - Manufacture of solid-state image pickup device - Google Patents

Abstract

PURPOSE:To improve the efficiency of photo absorption by making the photosensitivity characteristic of each element uniform by a method wherein the positions of the source and drain regions of each picture element of the SIT image sensor are determined at the same time, and the source-diffused region is diffused through non-doped poly Si. CONSTITUTION:A buried layer 22 is formed on a p<-> substrate 21 by diffusion or ion implantation. Next, a high-resistant epitaxial grown layer 23 is grown. Then, wet oxidation is carried out over the whole surface, and windows are opened; then, a well 25 is formed by ion implantation or thermal diffusion over the whole surface. Windows are opened at the same time to the parts of the shielding gate 26, control gate 27, source 28, and a well electrode lead-out 29, and a non-doped poly Si layer 30 and a PSG film 31 are formed over the whole surface. The Si layer 30 and the PSG film 31 are left on the region to serve as the source 28, and those at the other part are removed. p<+> diffused layers are formed at the parts of the shielding gate 26, control gate 27, and well electrode lead-out 29 by diffusion or ion implantation.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a solid-state imaging device, and in particular to a gate accumulation type static induction transistor (hereinafter abbreviated as SET) related to a simplified self-line planar process. The present invention relates to a method of manufacturing a type image sensor.

[Description of Prior Art] Conventionally, solid-state imaging devices have been put into practical use as CCD type and MOS type. SI recently proposed by one inventor
There is a T-type image sensor (IEEE Trans o
nElecjron Devices 1101. ED
-26, No. 12 (Dec, 1979) PP, 1
970-・1977).

The present inventors have also made various basic applications in matrix operation as applications in conjunction with the proposal of the basic structure. Regarding the specific manufacturing method, please refer to the patent application filed in 1983.
The invention is disclosed in Japanese Patent Application No. 57-218589, Japanese Patent Application No. 57-218590, and Japanese Patent Application No. 57-218591. The Japanese Patent Application No. 57-218589 relates to a method for manufacturing an SIT image sensor having the simplest planar structure, and FIG. 2 shows the main parts of the manufacturing process. The prior art will be explained below based on one drawing. In fig.

(A) After forming an n+ buried layer 2 on an n+ substrate or a p- substrate 1, high resistance n-epitaxial growth 3 (this can be either n-+P~, 1) and field oxidation@1 and control Boron B is deposited and driven into the gate 6 portion by ion implantation or diffusion.

(B) A window is opened in a predetermined portion of the source 5 through a mask alignment process, and phosphorus or As-doped polysilicon 8 or non-doped polysilicon 8 is deposited by CVD (
Chemical Vapor Depositio
n) Phosphorous P or Arsenic As deposited by technology
doping and hold a drive-in.

(C) After etching leaving the polysilicon 8 in the source electrode part and wiring part by mask alignment, P
SG (Phospho-5ilicate Glass
A diphosphorus silicate glass film 9 is formed by CVD.

(D) After etching and removing the field oxide film 7 and PSG film 9 above the control gate 6 portion by mask alignment, CVD of the nitride film 1o and CVD of the transparent electrode SnO2 film 11 are performed to form an N product on the control gate 6 portion. MIS (Met, al In5ulat
, or Semiconduct, or gt, ruct
, ure) form a capacitor.

(E) Only the control gate 6 portion and the Sn02 film 11 in the wiring portion are left by the mask alignment and etching process, and a contact hole is opened to the shielding gate 4 portion. Finally, AQ deposition and wiring etching are performed. AQftt? ! 12 is electric tlsn (lz
Contact is made with membrane 11. AQ electrode 13 is an AQ electrode for contacting with the shielding gate 4.

As is clear from the above explanation, patent application No. 57-21858
In the manufacturing method disclosed in No. 9, passivation (Pas
Seven masks are required except for sivation), and the n+ source 5 portion and the ρ+ gates 4 and 6 are formed using separate masks through a mask alignment process. For this manufacturing method, the inventors have
We proposed a self-line process for SIT image sensors that uses a single mask to define the + source 5 part and the p4' source 4 and 6 parts, and patent application No. 57-218590.
It was disclosed in the issue. The final cross-sectional structure is shown in FIG.

Next, the manufacturing process of the device shown in FIG. 3 will be briefly described. After forming the n+ buried layer 2 on the n+ substrate or the p- substrate 1, the n- high resistance epitaxial growth 3 is performed.
(This can be any n”-+P-+1), then LO
CO5 (LOCaliged Oxidat, ion
ofSilicon) technology to simultaneously define regions to become the source 5 portion and the gates 4 and 6 portions of the SIT. That is, the regions other than those that should become the source 5 and gates 4 and 6 of the SIT are covered with a thick field oxidation 11A7 formed by LOCO5. After the mask alignment process, Si 3 on the area that will become the gates 4 and 6 is
The Na film is removed, and gates 4 and 6 of the SIT are formed by boron B ion implantation and a heat treatment process.

Next, after the mask alignment step, the Si 3N 4 film and the Si0 2 film on the region that will become the source 5 portion are removed,
An n+ doped polysilicon 8 is formed on the entire surface by CVD technology, and an n+ source 5 diffusion region is formed by a heat treatment process. Eight layers of n+ doped polysilicon are etched to form wiring portions. Next, after growing the PSG film 9 by CvD, the 5102 film on the control gate 6 region is removed by a mask alignment process. Si of desired thickness]
After forming Ni 10 on the entire surface using CVD technology, further S
The n02 film 11 is grown by CVO. The above SnO211/S
A MIS4i1 structure is formed on the control gate 6 using the i3N410/5i(P'')6 structure.Si
After etching the 02 film 11, the shielding game
A contact hole is opened to the 84 portion, and sintering is performed by vapor deposition. Excluding passivation, seven masks are required for AQfl electrode wiring of 12°13.

In the manufacturing process of the SIT image sensor pixel having the structure shown in FIG. Since the position of the gate 4.6 is defined by the first mask, variations between the source and the gate are suppressed compared to the manufacturing method shown in FIG. However, the method shown in Figure 2.

In the method shown in FIG. 3, the number of required masks is 7. In the method shown in FIG.
Although the position of the source 5 and the source 5 are defined by the first mask, the diffusion process of the gates 4, 6 and the source 5 is performed using separate masks, and later the SnO2 on the control gate 6 is Since the same mask is used when etching the film 11, the total number of masks is seven. In this case, since the formation of the gates 4 and 6 and the formation of the source 5 are performed in separate processing steps, there is a drawback that the structure is susceptible to variations in characteristics.

The present inventors have further disclosed another method for manufacturing an SIT image sensor in Japanese Patent No. 1i57-218591. The cross-sectional shape of the final device is shown in FIGS. 4(A) and 4(B). A feature of the manufacturing method shown in this figure is that it uses the ACOS or plasma etching + LOCO5 technology to form the shielding gate 4 portion deeply. This is an example in which deep/p4-gates 4 and 6 are diffused in the control gate 6 portion by LOCO5 technology, and the position of the n+ source 5 region is determined by mask alignment. That is, it is not self-aligned (self-aligned). In the structure shown in FIG. 4(B), a deep p+ agate diffusion is formed in the shielding gate 4 portion using plasma etching and acos technology, and the positioning of the p+ control gate 6 diffusion and n
The positioning of the diffusion of the +source 5 portion is performed by mask alignment using separate masks.

In FIG. 4(A), the total number of masks is 7, excluding passivation, and in FIG. 4(B), the total number of masks is 7 to 8.

As explained above, there are four methods of manufacturing an SIT image sensor that have been disclosed and proposed by the present inventors. Second
In the manufacturing method shown in the figure, the gate diffusion and source diffusion of the SIT are positioned by a mask alignment process using separate masks. Therefore, when arranging a large number of cells in a matrix, there is a large variation in sensitivity characteristics between pixels. There are some drawbacks that affect it. However, the final structure of the device is planarized, which is advantageous in terms of increasing light reception efficiency.

In the manufacturing method explained in Figure 3, the positions of the gate and source of the SIT are defined by the first mask, so dimensional variations are much smaller than in the method shown in Figure 2. but.

A thick oxide film formed by the LOCOS process exists between the gate and source of the SIT, and the transmittance of light to the channel of the SIT is poor. In addition, the device surface has an uneven shape due to the influence of the oxide film caused by LOGDS, and light is scattered due to the uneven shape, resulting in a structure that makes it difficult to effectively introduce light into the device.

Furthermore, since gate diffusion and source diffusion are ultimately performed using separate masks, the total number of masks is 7 and the second
Same as in the figure.

In the manufacturing method explained in FIG. 4(A).

Simultaneously with the oxidation of the LOCO5 technology, ρ" gate diffusion is performed under the thick oxide film of the LOGDS, so the light receiving surface is uneven. At the same time, the source region is positioned by mask alignment, and the source diffusion region The variations in the positions of the elements greatly affect the variations in the characteristics of the final arrayed devices.

Furthermore, in the SIT image sensor manufacturing method explained in FIG. 4(8), the control gate diffusion and source diffusion positioning is performed by a mask alignment process, so that variations in channel width dimensions may occur.
Dimensional variations between gates are likely to occur, and when a plurality of cells are arranged in a matrix, the characteristics of each pixel will vary greatly.

As explained above, in the prior art method shown in FIG. 2, FIG. Therefore, when a plurality of cells are integrated, there is a problem in that the characteristics of each pixel vary.

Further, in the method shown in FIG. 3, the device surface becomes uneven and the source diffusion and gate diffusion are performed separately, so there is a corresponding variation and there is a problem that the light absorption efficiency is poor.

Furthermore, considering the total number of masks, the previous examples in Figures 2, 3, and 4 (A) and (B) are all 7 to 8 masks, and this number depends on the combination with the scanning circuit. It was inevitable that the number would be higher than this.

In addition, devices realized using conventional manufacturing methods have uneven surfaces due to LOGO5, and because they do not use a self-line process, variations in the sensitivity characteristics of each pixel are likely to occur, especially for large-capacity image sensors (500
(up to 700 pixels), it was unsuitable because uniformity was an important point.

[Purpose of the invention] The present invention has the above-mentioned drawbacks.

It is an object of the present invention to provide a novel method for manufacturing an image sensor that has uniform sensitivity characteristics of each element and has good light absorption efficiency.

[Summary of the Invention] Therefore, the present invention includes a step of forming a buried layer in each of the transistor formation regions on a semiconductor substrate, performing high resistance epitaxial growth, and then forming a field oxide film, and a first mask. In the alignment step, a window is opened in a partial well that separates each transistor region, and in the step of doping with impurities, in the second mask alignment step, D Ml for forming the light receiving part, the shielding gate of the J-conducting transistor, and the control gate are formed. . A step of forming a non-doped polysilicon film and further an insulating film on the entire surface after opening windows in each region/formation portion of the source and the electrode extraction region of the well.

A third mask alignment step leaves the non-doped polysilicon film and the insulating film on the portion where the source region of the static induction transistor is to be formed, and removes the other non-doped polysilicon film and the insulating film to form the shielding gate, control gate and After doping the portions of the well where the electrode extraction regions are to be formed with impurities, a step of again forming an insulating film on the entire surface and a fourth mask alignment step are performed to form the scanning circuit transistor region and the control gate region of the electrostatic induction transistor. The oxide film in the scanning circuit transistor region and the control gate region of the electrostatic induction transistor is removed by removing the insulating film on the source region and forming a dry thermal oxide film on the entire surface, and a fifth mask alignment step. A step of removing the remaining oxide film and forming a doped polysilicon film doped with impurities over the entire surface.

The sixth mask alignment step leaves the doped polysilicon film on the control gate region of the electrostatic induction transistor and the gate region of the scanning circuit transistor, and uses the doped polysilicon film as a mask to , a step of doping impurities by etching to open a train window, and a seventh mask alignment step to open contact holes to the shielding region and the source and drain regions of the scanning circuit transistor, and then form electrodes. The present invention is characterized in that the image sensor is manufactured by the steps of:

[Embodiment of the Invention] FIGS. 1A to 1H show each manufacturing process of an image sensor manufacturing method according to an embodiment of the invention. below.

Each manufacturing process (A) to (H) @: will be explained in order.

(A) The plane orientation of the substrate is (111) and (100)
Both are good.

A common buried layer 22 is formed on the p-substrate 21 by diffusion or ion implantation of As or SB, etc. in a region to become the sensor area of the SIT image sensor and a region to constitute the peripheral scanning circuit. The buried layer 22 has a common electrode around the sensor area or at a predetermined portion.

Although this electrode portion is not shown in FIG. 1(A), it becomes a common train area for a plurality of matrices of the SIT image sensor. The reason why such a buried layer 22 is formed is that the driving and scanning circuits for the matrix of the pixel portion of the SIT image sensor are to be formed on the same substrate.

Next, a high resistance epitaxial growth layer 23 is formed to a thickness of 3μ11.
Grow about 1 to 10 μm. The conductivity type of this epitaxial growth layer 23 may be n + P-.

Alternatively, it may be an i-layer. Next, wet oxidation is performed on the entire surface. The thickness of this field oxide film 24 is approximately 5000 to 8000 mm.

(B) In the first mask alignment process, a window is opened in a region for forming a scanning circuit transistor.

Next, a well 25 for a scanning circuit transistor is formed over the entire surface by ion implantation or thermal diffusion of B. When forming this well, an oxide film of about 2,000 to 4,000 feet is deposited.

Also, the surface concentration of the well is 5X10"'rya-'
That's about it.

(C) Through the second mask alignment process, windows are simultaneously opened in the shielding gate 26 portion, control gate 27 portion, source 28 portion of the SIT image sensor, and also in the electrode ridge portion 29 of the peripheral circuit transistor well. Let's do it. Next, a non-doped polysilicon layer 30 is formed on the entire surface using a technique such as CVD, and is further formed on one surface of the three PSG films using a technique such as CVD. The thickness of the polysilicon layer 30 is about 3,000 to 5,000 Å. CVD5i of the same thickness instead of PSG film
It may also be an O2 film.

CD) Through the third mask alignment process, the source 28
Non-doped polysilicon layer 30, P
The SG film 3 is removed, and the other parts of the non-doped polysilicon layer 30 and the PSG film 3 are completely removed. Since this step requires dimensional accuracy, it is performed by a dry process such as plasma etching.

(E) Diffusion or ion implantation of boron is performed again on the entire surface, and the shielding gate 26 part, the control gate 27 part, and the electrode extraction part 29 of the well are removed.
A 2+ diffusion layer is formed. The impurity density near the surface of these 4.6°14 ρ1 diffusions M is about LX101gc+n'.

(F) After forming the PSG film or CVD5i02 film 32 on the entire surface again to a thickness of about 3000 nm, the control gate 27 region,
A PSG film (or C
VD5i0 = film) 31 and 5102 film 32 are plasma etched to expose the Si plane on the p" control gate 27 diffusion region and the active region 33 of the scanning circuit transistor, and furthermore the polysilicon layer 30 on the source 28 region.

(G) Dry oxidize the entire surface to form a SiO: film 34. The thickness will be approximately 500 people to 100A. After that, a fifth mask alignment process is performed using the mask used in the third mask alignment process, leaving the dry oxidation l1i34 on the active region 33 of the scanning circuit transistor and the control gate 27, and drying the other driver and silicon oxide. 11g
34 is removed, and the polysilicon surface above the source 28 region of the SIT is again exposed. Furthermore, As or P is applied to the entire surface.
An n-doped polysilicon film 35 is formed using a technique such as CvO. The thickness of this polysilicon@35 is approximately 3000 to 4000 Å. By the process of forming the polysilicon film 35, the control gate 27 is
top, and active area 3 of the scanning circuit transistor
A storage capacitor region 36 and a transistor gate 37 region each having a modified S structure are formed on 3. In this case, a transparent overlay such as Sn02 may be used on the control gate 27 region.

(H) After etching the doped polysilicon 35 on the control gate 27 region and the gate 37 region of the scanning circuit transistor, leaving the doped polysilicon 35 on the wiring part, etching the other doped polysilicon,
Using this polysilicon film 35 as a mask, the gate oxide film 34 on the region where the source and drain of the scanning circuit transistor are to be formed is removed by etching. Next, As or P ions are again implanted or diffused into the entire surface of the source 38 of one peripheral scanning circuit transistor. The n+ region of the drain 39 and the source 28 region are formed. Source 38 of the scanning circuit transistor. The diffusion depth of the drain 39 is about 1 μm to 2 μm, and the surface concentration is 1×1019 cm.
'That's about it. Furthermore, the diffusion depth of the source 28 region is 0.
．． It is about 1 μm. Next, a four-layer PSG film is formed again using a technique such as 0VD on the entire surface. After that, the shielding gate 26 part, the electrode extraction part 29 of the well.
Source 38 of the scanning circuit transistor. A contact hole is opened to the drain 39 portion (sixth and seventh mask alignment steps). Furthermore, 11 electrodes are formed on the entire surface by vapor deposition, and are provided at predetermined shielding gates 26, well electrode extraction portions 29. AQ etching is performed, leaving an AQ wiring portion 41 for contact with the source 38 and drain 39 portions of the scanning circuit transistor and an AQ wiring portion 42 for contact with the doped polysilicon layer 34 (eighth mask alignment step). .

The SIT image sensor of this embodiment is manufactured through the above-mentioned steps, and its operation is similar to the conventional example, in which video signals are read out using the X-'/address method in which one pixel is an SIT having a capacitor at the gate. It will be done.

According to the method for manufacturing the SIT image sensor described above, the positions of the source 28 region and the gate 26 and 27 regions of each pixel of the SIT image sensor are simultaneously determined by the second mask process, As shown in FIG. 1, the source 28 diffusion region is diffused through non-doped polysilicon, so by controlling the thickness of this non-doped polysilicon, the source 28 diffusion region can be formed extremely shallow.

This makes it possible to bring the true potential of the SIT that makes up the pixel closer to the light incident side surface, and as a result,
The diffusion depth of the gate 26 and 27 diffusion regions can also be made shallow, and the short wavelength sensitivity of light can be improved. Furthermore, since the gate 26 and 27 diffusion regions are simultaneously diffused, the channel dimensions of the SIT portion constituting each pixel and the distance between the gate 26 and 27 regions and the source 28 region are all made uniform. Therefore.

The characteristics of the SIT portion are made uniform, and variations in the received light intensity: output characteristics of each pixel are suppressed to an extremely low level.

In addition, the Si surfaces of the gate 26 and 27 diffusion regions and the source 28 diffusion region of each pixel are on the same plane, and are subject to scattering due to unevenness on the semiconductor surface when receiving light, compared to the conventional manufacturing method. The ratio decreases and the light absorption rate increases.

In addition, in the above embodiment, the shielding gate 26
Although the gate accumulation method of the SIT image sensor having the divided gate of the control gate 27 and the control gate 27 has been described, insulator separation may be used instead of the shielding gate 26. In that case, the control gate 27
Since only the region becomes the gate region of the SIT, the forgery of the SIT is a forgery of the conventional SIT in which the source 2B region is surrounded by the control gate 27 region. However, it is clear that the same process as the manufacturing process of the present invention can be applied, since the positioning of the source 28 diffusion region and the gate 1 to 26° 27 diffusion regions is performed using the same mask, and the heat treatment process accompanying the diffusion is also performed at the same time. An image sensor with suppressed variation in characteristics can be obtained.

Further, it is clear that the conductivity types of the respective parts in the above embodiments may be completely opposite, and furthermore, a CMOS circuit trench structure may be easily constructed as the scanning circuit structure.

[Effects of the Invention] As described above, according to the present invention, when the distance between the gate part and the source part of the image sensor cell and the dimension of the channel are determined by the same mask, and a plurality of image sensor cells are arranged in a line or matrix, , an image sensor with uniform sensitivity characteristics of each pixel is obtained, and since the device is flattened after manufacturing, it has good light absorption efficiency, making it an ideal image especially for manufacturing large-capacity area sensors. A method for manufacturing a sensor is obtained.

[Brief explanation of the drawing]

FIGS. 1(A) to (H) show an SIT according to an embodiment of the present invention.
Image sensor manufacturing process step explanatory diagram, Figure 2 (A)
~(E) are explanatory diagrams of manufacturing process steps as conventional examples of gate accumulation type SIT image sensors, and FIGS. 3 and 4 (A) and ([3) are both other conventional examples of gate accumulation type SIT image sensors. 1 is a cross-sectional view of a device forgery using the manufacturing process of 21...ρ-substrate, 22...buried layer, 23
... High resistance epitaxial growth layer, 24 ... Field oxide film, 25 ... Well, 26 ... Shielding gate, 27 ... Control gate, 2
8.38 Mountain Source, 29... Electrode extraction part, 30... Non-doped polysilico-7 layer, 31,
110...PSG film, 32...CvD oxide film, 3
3... Active region, 34... Dry oxide film, 35... Doped polysilicon, 36...
Capacitor region, 37... Transistor gate, 3
9...Drain, 41.42...A for contact
Q wiring part. /'', Agent Patent Attorney Crest 1) Makoto 1゛- Figure 7 rA (B) (C) g Figure 17 (E) Figure 7 W, Figure 2 (A) (B) fI 2 Figure 3 Figure 3 Figure 4

Claims (1)

[Claims] In a method for manufacturing a solid-state imaging device in which a plurality of electrostatic induction transistors for photoelectric conversion and transistors for a scanning circuit are formed on a semiconductor substrate, a buried layer is formed in a region where each of the transistors is to be formed on the substrate, and high-resistance epitaxial growth is performed. After that, a field oxide film is formed, a first mask alignment process is performed to open a window in a partial well separating each transistor region, and an impurity is doped, and a second mask alignment process is performed to form a field oxide film. After opening windows in the areas where the shielding gate, control gate, and source regions of the electrostatic induction transistor for forming the light-receiving part are to be formed and the area where the electrodes of the well are to be taken out, a non-doped polysilicon film and an insulating film are formed on the entire surface. a non-doped polysilicon film and an insulating film on a portion where a source region of the static induction transistor is to be formed are left by a forming step and a third mask alignment step;
After removing the other non-doped polysilicon film and the insulating film and doping the portions where the shielding gate, control gate and well electrode extraction regions are to be formed with impurities, forming an insulating film over the entire surface again; A step of removing the insulating film on the scanning circuit transistor region and the control gate region and source region of the electrostatic induction transistor by a mask alignment step, and forming a dry thermal oxide film on the entire surface, and a fifth mask alignment step. , leaving an oxide film in the scanning circuit transistor region and the control gate region of the static induction transistor;
A step of removing other oxide films and forming a doped polysilicon film doped with impurities over the entire surface, and a sixth mask alignment step, are performed on the control gate region of the static induction transistor and the gate region of the scanning circuit transistor. The above doped polysilicon film is left and the doped polysilicon is used as a mask to perform etching to open the source and drain of the scanning circuit transistor to dope impurities, and a seventh mask alignment step removes the shielding. Sources of transistors for area and scanning circuits,
1. A method for manufacturing a solid-state imaging device, comprising the steps of: opening a contact hole to a drain region and then forming an electrode.