JPH0444467B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to solid-state imaging devices, and particularly to improvements in solid-state imaging devices using SIT (static induction type transistors).

As a solid-state imaging device using SIT, the starting technology is disclosed in Patent Application Publication No. 15229 of 1982.
The most basic device is disclosed, and more specific and improved versions of this device are disclosed in patent applications No. 204656 of 1982 and No. 157693 of 1982.
It has been proposed as a number.

The basic structure of SIT is similar to that of J-FET (junction field effect transistor), but it has the advantage that the impurity density of the semiconductor layer in which the channel region is formed is low. For example, common J-
In FET, the impurity density of the semiconductor layer in which the channel region is formed is about 10 ¹⁵ to 10 ¹⁷ cm ^-3 , whereas in SIT it is about 10 ¹² to 10 ¹⁵ cm ^-2 .

Therefore, the depletion layer formed in the channel region is formed over a wide range even in a state of thermal equilibrium where no external voltage is applied, and furthermore, the channel region has a short length. .

Due to the features described above that are different from ordinary J-FETs, the channel enters a pinch-off state in a state of thermal equilibrium or with the gate slightly reverse biased, and a potential barrier appears just in front of the source electrode. This makes it possible to control the movement of carriers constituting the source-drain current flowing from the source electrode to the drain electrode. That is, the source-drain current is determined by the amount of carriers that cross the potential barrier and reach the drain electrode.

On the other hand, the degree of the potential barrier described above also changes depending on the drain voltage applied to the drain electrode (with the source electrode as a reference). That is, by applying a drain voltage, electrostatic induction occurs, and since the impurity density in the channel region is low, the height of the potential barrier changes, and furthermore, the peak point of the potential barrier moves.

The degree of potential barrier also changes depending on the accumulation of electron-hole pairs formed by light incident on the channel region. That is, electrons and holes generated near the depletion layer in the channel region move along the potential barrier, are separated, and are accumulated in the gate region. Therefore, the height of the potential barrier changes. The degree of this change corresponds to the amount of incident light. Therefore, by applying an appropriate drain voltage, the source-drain current that flows has a magnitude corresponding to the amount of incident light.

As described above, the degree of the potential barrier changes depending on the gate voltage-drain voltage or incident light. Therefore, for example, if a bias voltage is applied so that the channel remains in the "OFF" state even when light is incident, carriers due to the incident light are accumulated, and then an appropriate readout voltage is applied, Non-destructive readout, that is, image information, that is, the degree of incident light, can be amplified and read out without destroying the accumulated state of carriers. A solid-state imaging device can be configured based on such a principle.

Furthermore, the degree of potential barrier varies greatly depending on dimensional accuracy. In SIT, a potential barrier is created by the diffusion potential between the source region and the gate or channel region. That is, the potential distribution is mainly determined by the boundary conditions of each region. Therefore, the characteristics are very sensitive to the arrangement or size of each region.

For this reason, the size of each cell, that is, the occupied area, needs to be large to a certain extent from the viewpoint of sensitivity, and it is considered difficult to improve the degree of integration by reducing the occupied area. ing.

The present invention has been made in view of this point, and an object of the present invention is to provide a solid-state imaging device that can improve the degree of integration while maintaining sufficient sensitivity.

That is, in the present invention, an uneven portion is formed on the surface of a semiconductor layer including a channel region, a gate region is formed in an inclined portion spanning the protruding portion and the recessed portion, and either the source or the drain region is connected to the gate region. The above objective is achieved by forming the insulating layer on a portion of the periphery and performing isolation between the cells at least in the recessed portions using an insulating layer.

Hereinafter, the present invention will be described in detail according to embodiments shown in the accompanying drawings.

FIG. 1 shows an embodiment of a solid-state imaging device using SIT according to the present invention. In this figure, A is a partially cutaway plan view, and B is a partially cutaway plan view.
It is an end view seen from the direction of the arrow in the top view of A. In this diagram B, components that connect each cell are omitted to avoid complicating the diagram.
Further, the end face of a cell corresponding to one pixel, which corresponds to FIG. 1B, is shown enlarged in FIG.

In these figures 1A, B and 2, impurity density using materials such as silicon (Si) is high.
A channel region 12 made of an n ^- layer with low impurity density is formed on the n ⁺ layer substrate 10 .

A valley-shaped recess is formed on the upper surface of the n ^- layer where the channel region 12 is formed, and a control gate region 14 made of a p ⁺ layer having a high impurity density is provided in this portion. The sides of this control gate region 14 have a high impurity density.
A source region 16 made of an n ⁺ layer is provided.
These control gate regions 14 and source regions 16 are arranged in a regular two-dimensional matrix at appropriate intervals, as shown in FIG. 1A.
4 and the source region 16 form a cell corresponding to one pixel.

The source regions 16 are not arranged at the same position in each cell, but are arranged so that the source regions 16 face each other in cells located in the left-right direction in FIG. Further, a floating gate region 18 made of a p ⁺ layer with high impurity density is formed between the opposing source regions 16 . That is, this floating gate region 1
The control gate region 14 and the source region 16 are arranged symmetrically with respect to the center 8 . As shown in FIG. 1B, the cross-sectional shape is continuous and wavy.

The floating gate region 18 is provided in common for the left and right cells, and is held at the same potential or a predetermined potential as the source region 18 by suitable electrode means (not shown). As a result, a depletion layer or a potential barrier is formed in the channel region 12, and channels are separated between each cell.

An insulating isolation region 18I made of an insulating layer is formed in contact with the control region 14 in a region other than the region occupied by a pair of left and right cells (hereinafter referred to as "cell blocks") that share the floating gate region 18, that is, between each cell block. ing. A portion of the insulation isolation region 18I is located at the bottom of the recess in the semiconductor layer, so even if the layer is relatively thin, each cell can be sufficiently isolated. The insulating isolation region 18I has a similar function to the floating gate region 18 in that it isolates each cell block, but it does not have the function of providing a potential reference.

A portion of the semiconductor layer constructed as described above is shown in FIG. 3A. As shown in this figure, the cell, particularly the control gate region 14, is formed on a slope centered on the bottom of a valley whose cross section is approximately V-shaped. Therefore, compared to the case where the control gate region is formed in a planar shape without forming the valley, the boundary region between the control gate region 14 and the channel region 12 is expanded, and the junction capacitance formed at the junction is increased. And by extension,
The effective light-receiving area for random incident light increases, improving the sensitivity of the cell. In other words, in order to obtain the same cell sensitivity as the conventional cell, the area occupied by the cell in the direction of the main surface of the substrate 10 may be small, and the degree of integration can be improved.

Note that the arrangement shape of the cells may be a substantially U-shaped valley-like cross-sectional shape, as shown in FIG. 3B. Further, the valley portion may be provided two-dimensionally. Note that instead of the valley-like shape, a mountain-like convex portion may be formed and cells may be formed on the slopes of the convex portion, but from the viewpoint of separation between each cell and the manufacturing process described below, A concave design is advantageous.

Next, as shown in FIGS. 1A, B and 2, a channel region 12 is formed.
A control gate region 14 is provided on the top surface of the n ^- layer.
A silicon oxide (SiO ₂ ) film 20 is formed on the entire source region 16 except for the exposed portion for surface protection. A source electrode 22 is formed in an exposed portion of the source region 116 to connect adjacent cells. The direction of this connection is shown in Figure 1A.
As shown in , this is a direction that intersects the connection direction of gate electrodes, which will be described later.

Next, a transparent gate electrode 24 is formed on the exposed portion of the control gate region 14 with an insulating layer 26 interposed therebetween. The insulating layer 26 is, for example,
It is made of a SiO ₂ film and is provided extending above the source electrode 22 . A gate electrode 24 is formed along this insulating layer 26. That is, a capacitor is formed between the control gate region 14 and the gate electrode 24 by the insulating layer 26, and the source electrode 22 and the gate electrode 24 are insulated. The direction in which the gate electrode 24 is connected intersects with the direction in which the source electrode 22 is connected, thereby making it possible to read out information stored in any cell. That is, by selecting any one of the plurality of source electrodes 22 and selecting any one of the plurality of gate electrodes 24, a cell at a position where both electrodes intersect is selected.

A drain electrode 28 is provided on the side of the substrate 10 opposite to the n ^- layer where the channel region 12 is formed.
is formed.

Next, the electrical equivalent circuit of the solid-state imaging device having the above-described structure, the connection between each electrode, and the connection with the driving means will be explained.

FIG. 4 shows the electrical circuit and connections to external devices. Some of the connections with external devices are also shown in FIG. In these figures, a plurality of cells PC corresponding to each pixel are secondarily arranged in a matrix, as shown in FIG. 1A. A read address circuit 30 is connected to each of the plurality of gate electrodes 24, and a read pulse voltage is sequentially applied thereto. On the other hand, the plurality of source electrodes 22 are each connected to the drain of a transistor 40 that performs a switching operation, and the source is connected to the output terminal 3.
8, respectively. The gates of the transistors 40 are each connected to the video line selection circuit 32. The video line selection circuit 32 sequentially outputs selection pulse voltages to the transistors 40, thereby sequentially driving the transistors 40.

For example, the transistor 40 is normally “OFF”
The read address circuit 30 and the video line selection circuit 3 are configured by the SIT in the state of
2 is constituted by, for example, a shift register.

Further, a load resistor 34 and a power source 36 are connected between the output terminal 38 and the ground, that is, the drain electrode 28.
are connected, which forms the source-drain current during readout, and furthermore, the source-drain current.
The drain current is converted to voltage.

In addition, in Fig. 4, the area indicated by the dashed line
IM corresponds to the part of the structure shown in FIG. 1A etc.

Next, the overall operation of the above embodiment will be explained.

First, when light is incident on each cell, electron-hole pairs are generated in the potential gradient portion formed from the control gate region 14 to the channel region 12. Specifically, the incident light mainly passes through the control gate region 14 and reaches the channel region 12, where electron-hole pairs are generated. Of the generated electron-hole pairs, electrons move toward the drain electrode 28, and holes move toward the control gate region 14 and are accumulated. This accumulation of holes is due to the fact that a capacitor is formed between the control gate region 14 and the gate electrode 24. Furthermore, the amount of accumulated holes is
Since the control gate region 14 is formed in a sloped shape, it is larger than the conventional case. Particularly, when the incident light is not parallel and is incident from a random direction, the effect of accumulation of holes with respect to the light that is incident from an oblique direction to the cell PC becomes remarkable.

Through the above operations, image information is accumulated in each cell PC. Next, video line selection circuit 3
A selection pulse voltage is sequentially applied to the plurality of transistors 40 connected to the plurality of source electrodes 22 by the plurality of source electrodes 22 . As a result, the corresponding transistor 40 is driven, and the source electrode 22 and drain electrode 28 of a plurality of cells PC arranged in the corresponding column direction among the cells PC shown in FIG. and is connected to the power supply 36. Therefore, the preparation for the flow of source-drain current is completed. In addition, in this state, each cell PC
For example, the power supply 3
6 voltage etc. are adjusted.

Through the above operations, a video line from which image information is to be read is selected. Next, the read address circuit 30 selects a plurality of gate electrodes 24.
A pulse voltage is sequentially applied to the two. The cell located on the video line selected by this
The PCs become conductive one after another, and a source/drain current corresponding to the amount of holes accumulated in the control gate region 14, that is, the amount of incident light, flows to the resistor 34, and is further converted into a voltage by the resistor 34, and is output to the output terminal. It is output from 38.

Through the above operation, image information corresponding to the incident light is outputted as a voltage change at the output terminal 38.

FIG. 5 shows an embodiment in which the present invention is applied to a line sensor. Note that the same reference numerals are used for the same components as in the above-described embodiment, and the following description will be omitted.

In this embodiment, it is advantageous to form a recess in the left-right direction in the figure and to provide the control gate region 14 on the slope of the recess. The source region 16L of each cell is provided in common for all cells, and the floating gate region 18L is also provided in common. In the case of a line sensor, the above-mentioned video line selection is not required, so the source region 16L can be configured in common. The floating gate regions 18L do not necessarily have to be shared. Note that in the above-described embodiment as well, the floating gate region 18 and each cell may have a common configuration.

The video line selection circuit 32L and the transistor 40L are shown for comparison with FIG. 4, although they are not necessarily necessary.

In the above embodiment, holes are accumulated when light also enters the floating gate region 18, and a pair of cells PC constituting the cell block
This results in the inconvenience that the separation between the two is not well achieved.

Another embodiment that eliminates such inconvenience will be described. 6A and 6B show other embodiments of the present invention, FIG. 6A is a plan view corresponding to FIG. 1A, and FIG. 6B is a plan view corresponding to FIG. 1B. FIG. 6 is an end view taken from the arrow in FIG. 6A; In this embodiment, the same reference numerals are used for the same components as in the embodiment shown in FIGS. 1 to 4, and the explanation thereof will be omitted.

In the embodiment shown in FIGS. 6A and 6B,
The source region 16 is the floating gate region 1
It is located close to 8. That is, if the distance between the source region 46 and the floating gate region 18 is WA, and the distance between the source region 46 and the control gate region 14 is WB, then WA<WB.
It becomes a relationship. In this way, the potential barrier formed on the floating gate region 18 side is higher than the potential barrier formed on the control gate region 14 side, so that the cells in the cell block
Good separation between PCs.

Furthermore, in this embodiment, an insulating film 42 is formed on the source region 46 and the floating gate region 18.
An aluminum film 44 is formed through the aluminum film. Therefore, floating gate region 1
No light enters the portion 8, and holes are not accumulated in the floating gate region 18. Therefore, separation between cell PCs becomes good.
Note that the luminescent film 44 does not need to be provided below the gate electrode 24, and may be provided above it.

Such improvement in isolation between the cells PC can also be achieved by forming the floating gate region 18 deeper in the channel region 12 than in the control gate region 14; This can also be achieved by making the impurity density of the control gate region 18 higher than that of the control gate region 14.

Cells constituting a cell block by any one of the above configurations or a combination of multiple configurations.
The isolation between PCs can be improved, and the degree of integration of cell PCs arranged per unit area can be significantly improved.

Next, the manufacturing process of the solid-state imaging device described above will be explained with reference to FIGS. 7A to 7W.

First, as the substrate 10, antimony Sb is 10 ¹⁸
An n ⁺ type silicon substrate doped to about cm ^-3 is used. The n ^- layer 50 on which the channel region 12 is formed is epitaxially grown on the substrate 10 . That is, since the n ^- layer 50 is a layer in which electron-hole pairs are formed and further separated by incident light and a channel region 12 is formed, dislocations, defects, etc. are sufficiently removed. This is because it is necessary. This n ^- layer 50 is formed to a thickness of about 5 to 10 μm, and the impurity density is
It is about 10 ¹³ to 10 ¹⁵ cm ^-3 .

Note that in order to prevent recombination of carriers in the n ^- layer 50 and extend the life of the separated carriers, gettering may be applied to heavy metals.

Next, an oxide film 5 is formed over the entire surface of the n ^- layer 50.
2A is formed, wet etching is performed using a suitable mask to remove portions of the oxide film 52A corresponding to control gate region 14 and part of insulation isolation region 18I. This condition is shown in FIG. 7A.

Next, the n ^- layer 50 is etched to form a V-shaped recess in which the control gate region 14 and the like will be formed.

This etching of the n ^- layer 50 is performed, for example, by anisotropic etching of the crystalline material. In a silicon crystal, for example, crystal plane 11
1, compared to other crystal faces, sodium hydroxide,
Etching speed with alkaline solutions such as potassium hydroxide and hydrazine is extremely slow. The etching rate of crystal plane 111 is
It is about 0.3 to 0.4% relative to 0.00. By utilizing such properties, the n ^- layer 50 can be etched well.

After this etching, the oxide film 52A is once removed as shown in FIG. 7B.

Next, an oxide film 90 is formed over the entire surface of the n ^- layer 50. The thickness of this oxide film 90 is 400 mm.
It is formed by immersion in an oxygen atmosphere at 1000°C for about 40 minutes.

A Si ₃ N ₄ film 92 of 1200 Å is deposited over the entire oxide film 90 by CVD (chemical vapor deposition).
It is formed with a film thickness of about Formation is carried out by exposure to a reactive gas atmosphere at 800° C. for about 40 minutes. This condition is shown in FIG. 7C.

Plasma etching is then performed using a suitable mask to etch portions of the coating 92 corresponding to the isolation regions 18I. This operation is performed in a mixed gas atmosphere of CF ₄ and O ₂ at an atmospheric pressure of 0.1 Torr. The state after this operation is the seventh
Shown in Figure D.

By a similar operation, the oxide film 90 is also etched as shown in FIG. 7E.

Next, oxidation is performed to form a SiO ₂ layer 94 corresponding to the isolation region 18I. In this case,
The n ^- layer 50 exposed by the etching may be etched by plasma to a thickness of about 1 μm. This plasma etching operation is performed, for example, in a PCl ₃ gas atmosphere.
The situation at the end of this operation is shown in FIG. 7F.

Next, plasma etching is performed using a suitable mask, and the pattern of the p ⁺ layers 54 and 56 corresponding to the control gate region 14 and floating gate region 18 is formed on the coating 92 as shown in FIG.
is formed as shown in , and furthermore, BBr ₃
Impurities that serve as acceptors are implanted. By this operation, as shown in FIG. 7H, p ⁺ layers 54 and 56 are each formed to a thickness of about 1 to 5 μm, preferably about 1 to 3 μm.
The impurity may be implanted by thermal diffusion after vapor deposition, or by ion implantation. In the case of thermal diffusion, impurities are implanted in an oxygen or wet oxygen (or water vapor) atmosphere at, for example, 1100°C.

Next, the film 92 is removed by plasma etching in a gas atmosphere of 0.1 Torr, CF ₄ and O ₂ , and the oxide film 90 is removed by patch oxidation de-etching. This situation is shown in FIG. 7I.

Next, an oxide film 52 is formed over the entire surface of the n ^- layer 50. This operation is performed in an oxygen atmosphere at 1100℃.
This is done by soaking for about 30 minutes, and the film thickness is, for example, about 5000 Å. (See Figure 7J).

Next, in order to form the n ^- layer 60 corresponding to the source region 16, mask alignment is performed, and a pattern of the n ⁺ layer 60 is formed in the oxide film 52 by wet etching (see FIG. 7K). ). In this state, an impurity that can serve as a donor, such as arsenic (As), is implanted by thermal diffusion or ion implantation. Through this operation, as shown in Figure 7L,
An n ⁺ layer 60 is formed.

A DOPOS (phosphorous doped polycrystalline silicon) layer 62 is then formed over the entire surface as shown in FIG. 7M. This DOPOS layer 62 is
It is formed by CVD (chemical vapor deposition) using a gas atmosphere of SiH ₄ and PH ₃ .

Next, a portion of the DOPOS layer 62 is etched by plasma etching using a suitable mask to form an electrode layer 64 corresponding to the source electrode 22. This condition is shown in FIG. 7N. For plasma etching, a gas atmosphere such as CF ₄ , CF ₄ and O ₂ or PCl ₃ is used.

Next, a PSG (phosphorus glass) layer 66 is formed as an interlayer insulating layer over the entire surface as shown in FIG. 7O. This PSG layer 66 is formed by a CVD method, for example, by heating to about 400° C. in a gas atmosphere of SiH ₄ , O ₂ and PH ₃ . Alternatively, it can be carried out by heating to about 750°C in a gas atmosphere of SiH ₄ , H ₂ O and PH ₃ .

Wet etching is then performed using a suitable mask to expose the surface of p ⁺ layer 54, as shown in FIG. 7P.

Next, an insulating layer 68 of Si ₃ N ₄ is formed over the entire surface as shown in FIG. 7Q. The insulating layer 68 is formed by CVD to a thickness of 400 to 700 Å in a SiH ₄ and NH ₃ gas atmosphere.

Next, a transparent electrode layer 70 made of SnO ₂ or DOPOS is formed over the entire surface as shown in FIG. 7R. This electrode layer 70 has a thickness of, for example, 3000 Å.
It is formed by CVD method using SbCl ₅ etc. to a certain thickness.

Next, plasma etching is performed using a suitable mask, and the electrode layer 70 is etched except for the portion on the p ⁺ layer 54, as shown in FIG. 7S. This operation involves CCl ₄ , CF ₄ , CF ₄ and
This is done using a gas such as O ₂ or PCl ₃ .

Through the above operations, the solid-state imaging device according to the embodiment shown in FIGS. 1 to 4 is manufactured. Note that, for the sake of explanation, only the main parts of the apparatus shown in FIGS. 1 and 2 are shown. Also, n ⁺ corresponding to the source region 16
The position and shape of layer 60 can be easily adjusted by appropriately changing the shape of the mask in the step in FIG. 7K.

Next, the formation of the film 44 described in the embodiment shown in FIGS. 6A and 6B will be described with reference to FIGS. 7T to 7W. Note that the shimmering film formed in the following steps is similar to that of the gate electrode 24.
That is, it is provided parallel to the electrode layer 70 shown in FIG. 7S.

First, a portion of the insulating film 68 above the p ⁺ layer 56 is etched by plasma etching using a suitable mask. This operation is carried out using a gas atmosphere of eg CF ₄ (see FIG. 7T).

Next, wet etching exposes the
The PSG layer 66 and oxide film 52 are etched as shown in FIG. 7U.

Next, as shown in FIG. 7V, an aluminum film layer 72 is formed over the entire surface with a thickness of about 1.0 μm. This shimmering layer 72 is formed by vacuum deposition using an electron beam or resistance heating, or by sputtering.

Next, a portion of the phosphor layer 72 is etched using a suitable mask, and an electrode layer 80 made of aluminum is formed on the substrate 10. This condition is shown in FIG. 7W. Formation of this electrode layer 80 is performed, for example, by a method such as sintering.

Note that the shimmering layer 72 is connected to the p ⁺ layer 56 corresponding to the floating gate region 18,
It has a function as an electrode for applying voltage to the floating gate region 18.

The manufacturing process described above is only an example, and other manufacturing processes may be used. Also, other materials may be used, such as
The n ⁻ layer 50 may be an intrinsic semiconductor layer into which impurities are not implanted. Further, as the insulating layer 68,
SiO ₂ , Al ₂ O ₃ , tantalum oxide, or a composite film of these may be used.

In all of the above embodiments, the channel is formed by the n ⁺ layer, but it is
The channel may be formed by a p ^- semiconductor layer. Furthermore, the same effect can be obtained even if the source and drain correspond to each other in the opposite manner to those in the above embodiment. The same applies to the selection of video lines or the application of pulse voltages for reading, and the above embodiments may be reversed.

Further, a normal transistor may be used as the driving transistor 40, or the transistor 40, the read address circuit 30, and the video line selection circuit 32 may be integrated with the imaging device to form an integrated circuit. . As for the material,
Although silicon is mainly used, the present invention is not limited to this in any way, and germanium,
- group compound semiconductors etc. can also be used.

Furthermore, in order to obtain color image information, it is necessary to
For example, configure a matrix of PCs corresponding to red (R), green (G), and blue (B), apply a color filter to the incident light, separate the R, G, and B light, and enter each corresponding cell PC. All you have to do is let it happen.

As explained above, according to the solid-state imaging device according to the present invention, uneven portions are formed on the surface of the semiconductor layer,
Since the gate region, particularly the control gate region where light enters, is provided in the recess, and the source region is located only on one side of the control gate region, it is possible to effectively expand the light-receiving area of the cell. This makes it possible to improve the degree of integration while maintaining sufficient sensitivity. Furthermore, since the cells in the recess are separated by an insulating layer, the cells can be separated well.

Furthermore, since such uneven portions are formed by utilizing the anisotropic etching characteristics of the crystal, there are advantages in that the manufacturing process is simplified and accuracy is high.

[Brief explanation of drawings]

FIG. 1A is a partial plan view showing an embodiment of the solid-state imaging device according to the present invention, FIG. 1B is a schematic end view seen from the arrow in FIG. 1A, and FIG. 3A is a perspective view showing a part of the semiconductor layer, FIG. 3B is a perspective view showing another shape of the semiconductor layer, and FIG. 4 shows the configuration of an equivalent electric circuit. FIG. 5 is a partially cutaway plan view showing an embodiment of the line sensor according to the present invention, and FIG. 6A is a partial plan view showing another embodiment of the solid-state imaging device according to the present invention. B is a schematic end view seen from the arrow in FIG. 6A, and FIGS. 7A to 7W are explanatory diagrams showing an example of the manufacturing process. Explanation of symbols of main parts: 12... Channel region, 14... First gate region, 16... Source region, 18... Second gate region, 18I... Insulating isolation region, PC... Cell.

Claims (1)

[Claims] 1. A plurality of cells each formed by an SIT in which a first gate region is formed on the surface of a semiconductor layer including a channel region are arranged, and each cell corresponds to the amount of light incident on each cell. In the solid-state imaging device in which the current flowing through the source region and the drain region changes due to the accumulation of carriers in the first gate region, an uneven portion is formed on the surface of the semiconductor layer, and the first gate region a region is formed in an inclined portion spanning the convex portion and the concave portion, and one of the source region and the drain region is partially formed in the convex portion near the periphery of the first gate region. , an insulation isolation region extending deep into the channel region forms isolation between at least the cells in the recess, and is of the same conductivity type as the first gate region and of the first gate region.
A solid-state imaging device characterized in that at least the cells in the convex portion are separated by a second gate region independent of the gate region. 2. In the device according to claim 1,
The cells are arranged in two dimensions, each cell forming one cell block for every two adjacent cells, and one
The two cell blocks are symmetrical across the convex portion, and include two first gate regions and a single cell block disposed between the two first gate regions and common to the two first gate regions. a second gate region, one of the source region and the drain region respectively disposed between the first and second gate regions, and an insulating isolation region surrounding these regions. A solid-state imaging device. 3. In the device according to claim 1 or 2, the surface of the semiconductor layer has a predetermined crystal plane, and the uneven portion is formed by anisotropic etching of the surface of the semiconductor layer. A solid-state imaging device characterized by: