JPS59158681A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To improve the degree of circuit integration by forming a gate region at a slant part of a rugged part and forming one of a source or a drain region to the circumference of the gate region in a device using an SIT. CONSTITUTION:The rugged part is formed on the surface of a semiconductor layer including a channel region 12, the gate region 14 is formed on the slant part over the rugged part and one of the source region 16 and the drain region is formed at a part of the circumference of the gate region 14. The isolation in at least the projected part among the isolations of the cell is performed by an insulating layer 18I. Thus, the photodetecting area of the cell is expanded effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a solid-state imaging device that uses SIT, that is, a static induction transistor.

As a solid-state imaging device using SIT, the most basic device is disclosed in Patent Application Publication No. 15229 of 1980 as a starting technology, and furthermore, more specific and improved versions of this device are disclosed. This has been proposed as patent application No. 204656 of 1982 and patent application No. 157693 of 1988.

The basic structure of the SIT is similar to that of a J-FET (junction field effect transistor), but it has the advantage that the impurity density of the semiconductor layer in which the channel region is formed is low. For example, in a general J-FET, the impurity density of the semiconductor layer in which the channel region is formed is 10 to 10177]'-', whereas in the SIT,
It is about 10 to 5 −2 10 Crn.

Therefore, the depletion layer formed in the channel region is formed over a wide range even in a state of thermal equilibrium where no voltage is applied from the outside, and furthermore, the channel region has a short length.

Due to the above features different from ordinary J-FETs, the channel enters a pinch-off state in a state of thermal equilibrium or with the gate slightly reverse biased, and a potential barrier appears just in front of the source electrode. This makes it possible to control the movement of carriers constituting the source-drain current flowing from the source electrode to the drain electrode. That is, the source-drain current is determined by the amount of carriers that cross the potential barrier and reach the drain electrode.

On the other hand, the degree of the potential barrier mentioned above also changes depending on the drain voltage applied to the drain electrode (with reference to the source electrode). Since the impurity density in the channel region is low, the height of the potential barrier changes, and furthermore, the peak point of the potential barrier shifts.

Indeed, the extent of the potential barrier also changes due to the accumulation of electron-hole pairs formed by light incident on the channel region. That is, electrons and holes generated near the depletion layer of the channel region move along the potential barrier, are separated, and are accumulated in the channel region. Therefore, the height of the potential barrier changes. The degree of this change corresponds to the amount of incident light. Therefore, by applying an appropriate drain voltage, the source-drain current that flows has a magnitude corresponding to the amount of incident light.

As described above, the degree of the potential barrier changes depending on the gate voltage-drain voltage or the incident light. Therefore,
For example, if a bias voltage is applied so that the channel maintains the r OFF J state even when light is incident, carriers due to the incident light are accumulated, and then an appropriate readout voltage is applied, non-destructive readout can be performed. In other words, it becomes possible to amplify and read image information, that is, the degree of incident light, without destroying the accumulated state of carriers.

A solid-state imaging device can be configured based on such a principle.

Furthermore, the degree of potential barrier varies greatly depending on dimensional accuracy. In SIT, a potential barrier is created by the diffusion potential between the source region and the gate or channel region. That is, the potential distribution is mainly determined by the boundary conditions of each region. Therefore, the characteristics are very sensitive to the arrangement or size of each region.

Therefore, the size of each cell, that is, the occupied area is
From the viewpoint of sensitivity, a certain amount of size is required.
It is said that it is difficult to improve the degree of integration by reducing the occupied area.

The present invention has been made in view of this point, and an object of the present invention is to provide a solid-state imaging device that can improve the degree of integration while maintaining sufficient sensitivity.

That is, the present invention forms uneven portions on the surface of a semiconductor layer including a channel region, forms a gate region in the raised portions and four sloped portions, and also forms a channel region in either the source or drain region. The purpose is to be achieved by forming the insulation layer on a portion of the periphery of the cell and performing isolation at least in the concave portion of the isolation between the cells using an insulating layer.

Hereinafter, the present invention will be described in detail according to embodiments shown in the accompanying drawings.

FIG. 1 shows an embodiment of a solid-state imaging device using 5IT- according to the present invention. Of this figure, (A)
is a partially cutaway plan view, and (B) is an end view seen from the direction of arrow I in the plan view of (A). In this ([3)], components for connecting each cell are omitted to avoid complicating the diagram. 1, the end face of a cell corresponding to one pixel, which corresponds to FIG. 1(B), is shown enlarged in FIG.

In these figures 1 (A), (B) and 2,
A channel region 12 made of an n-layer with a low impurity density is formed on a substrate 10 made of a material such as silicon (Si) and having a zero impurity density.

A valley-shaped recess is formed on the upper surface of the n-layer where the channel region 12 is formed, and a control gate region 14 made of a p-layer with a low impurity density is provided in this portion. On the side of this control case area 14,
A source region 16 made of a single layer of n4 with high impurity density is provided. These control key-1/area 1
4 and the source region 16 are arranged in a regular two-dimensional matrix at appropriate intervals, as shown in FIG. 1A). A cell corresponding to one pixel is formed by the source region 16 and the source region 16 .

The source regions 16 are not arranged at the same position in each cell, but are arranged so that the source regions 16 face each other in cells located in the left-right direction in FIG.

Further, a 70-ch gate region 18 made of a p layer with high impurity density is formed between the opposing source regions I6. In other words, this floating case
The control gate region 14 and the source region 16 are arranged symmetrically with respect to the gate region 18. As shown in FIG. 1(B), the cross-sectional shape is continuous and wavy.

The floating gate region 18 is provided commonly to the left and right cells, and is maintained at the same potential or a predetermined potential as the source region 18 by suitable electrode means (not shown).

As a result, a depletion layer or a potential barrier is formed in the channel region 12, and channels are separated between each cell.

In areas other than the area occupied by a pair of left and right cells (hereinafter referred to as "cell blocks") that share the floating case area 18, that is, between each cell block, an insulating isolation area 18I made of an insulating layer is provided as a controller area. 14. Since part of the insulation isolation region 18I is located at the bottom of the four parts of the semiconductor layer, each cell can be sufficiently isolated even if the layer is relatively thin. The insulating isolation region 18I has the same function as the region 18 in the cell blocks 70 to 70 in that it isolates each cell block, but it does not have the function of providing a potential or a potential reference.

The part of the semiconductor layer configured as described above is shown in Figure 3 (
Shown in A). As shown in this figure, the cell, particularly the control cell +-1 region 14, is formed on a slope centered on the bottom of a valley whose cross-sectional shape is approximately V-shaped. Therefore, compared to the case where the control gate region is formed in a planar shape without forming the valley, the boundary region between the control gate region 14 and the channel region 12 is expanded, and the junction capacitance formed at the junction is increased. As a result, the effective light-receiving area for incident light increases, and the sensitivity of the cell improves. If the cell is placed in a separate storage, the area occupied by the cell in the direction of the principal surface of the substrate 10 may be slightly smaller in order to obtain the same cell sensitivity as in the prior art, and the degree of integration can be improved.

Note that the arrangement shape of the cells may be a substantially U-shaped valley-like cross-sectional shape, as shown in FIG. 3 [F]).

The trough portion may be provided two-dimensionally. Note that instead of the valley-like shape, a convex part may be formed, and cells may be formed on the slope of the convex part, but from the viewpoint of separation between each cell and the manufacturing process described later, It is more advantageous to form the

Next, as shown in FIGS. 1(A) and 2(B) and FIG. Silicon oxide (S
i02) A membrane 20 is formed for surface protection. A source electrode 22 is formed in an exposed portion of the source region 16 to connect adjacent cells. The direction of this connection, as shown in FIG. 1(A), is the direction that intersects the connection direction of the gate electrodes, which will be described later.

Next, in the exposed portion of the control gate area 14,
A transparent gate electrode 24 is formed with an insulating layer 26 interposed therebetween. The insulating layer 26 is made of, for example, a SiO2 film, and is provided on the source electrode 22 (extending).

A cage 1 electrode 24 is formed along this insulating layer 26. That is, a capacitor is formed by the insulating layer 26 between the control I/roll gate region 14 and the gate electrode 24, and a capacitor is formed between the source electrode 22 and the gate electrode 24.
1. Insulation from the electrode 24 is performed. The direction in which the gate electrode 24 is connected intersects with the direction in which the source electrode 22 is connected, thereby making it possible to read out information stored in any cell. That is, by selecting any one of the plurality of source electrodes 22 and selecting any one of the plurality of gate electrodes 24, the cell at the intersection of both electrodes is selected.

A drain electrode 28 is formed on the side of the substrate 10 opposite to the n'' layer where the channel region 12 is formed.

Next, the connection between the electric value circuit of the solid-state imaging device having the above-described structure, the connection between each electrode, and the connection with one driving means will be explained.

FIG. 4 shows the electrical circuit and connections to external devices. Some of the connections to external devices are also shown in FIG. In these figures, a plurality of cells pc corresponding to pixel units are secondarily arranged in a square shape, as shown in FIG. 1(A). A readout address circuit 30 is connected to each of the plurality of case electrodes 24, and a readout voltage is sequentially applied thereto. On the other hand, multiple source voltages lf
j 22 (a) are each connected to the drain of the transistor 40 that performs a switching operation, and further, the source is each connected to the output terminal 38.

The 400 transistor gates are each connected to a video line selection circuit 32. The video line selection circuit 32 sequentially outputs selection voltages to the transistors 40, whereby the transistors 40 are sequentially driven by one.

The transformer 4o is constituted by, for example, an SIT which is normally in an "OFF" state, and the read address circuit 30 and the video line selection circuit 32 are constituted by, for example, a shift resistor.

The output terminal 38 and the ground, that is, the drain electrode 28.
A load resistor 34 and a power supply 36 are connected between the two, thereby forming a source-train current during reading, and further converting the source-drain current into a voltage.

In addition, in FIG. 4, the region IM indicated by a dashed line corresponds to the part of the structure shown in FIG. 1(A) and the like.

Next, the overall operation of the above embodiment will be explained.

First, when light is incident on each cell, electron-hole pairs are generated in the potential gradient portion formed from the control gate region 14 to the channel region 12. Specifically, the incident light mainly passes through the control gate region 14 and reaches the channel region 12, where electron-hole pairs are generated. Of the generated electron-hole pairs, tf- moves toward the drain electrode 28, and holes move toward the control gate region I4 and are accumulated. This accumulation of holes is caused by control group 1-1.
This is due to the fact that a capacitor is formed between the region 14 and the gate electrode 24. Furthermore, the amount of accumulated holes is larger than in the conventional case because the control gate region 14 is formed in an inclined shape. Particularly, when the incident light is not parallel and is incident from a random direction, the effect of accumulating holes with respect to the light incident from an oblique direction to the cell pc becomes remarkable.

Through the above operations, image information is accumulated in each cell PC. Next, a selection pulse voltage is sequentially applied by the video line selection circuit 32 to the plurality of transistors 40 connected to the plurality of source electrodes 22. As a result, the corresponding transistor 4o is driven, and the source electrode 22 and drain electrode 28 of a plurality of cell PCs arranged in the corresponding column direction among the cell PCs shown in FIG. and is connected to the power supply 36. Therefore, preparation for the flow of source-drain current is completed. In this state, for example, the voltage of the power supply 36 is adjusted so that each cell pc maintains a non-layered state.

Through the above operations, a video line from which image information is to be read is selected. Next, read address circuit 3o
A positive voltage is applied to the plurality of gate electrodes 24 in sequence.

As a result, the cells PC located on the selected video line become conductive one after another, and a source/drain current corresponding to the amount of holes accumulated in the control region 14, that is, the amount of incident light, flows through the resistor 34. Furthermore, resistance 3
4 is converted into a voltage and output from the output terminal 38.

Through the above-described operation, image information corresponding to the incident light is outputted as a voltage change at the output terminal 38.

FIG. 5 shows an embodiment in which the present invention is applied to a line sensor. Note that the same reference numerals are used for the same components as in the above-described embodiment, and the following description will be omitted.

In this embodiment, it is advantageous to form four parts in the left and right direction of force in the figure, and to provide the control case 1/region 14 on the slope of the recess.

The source region 16L of each cell is provided in common for all cells, and the floating gate region 18L is also provided in common. In the case of a line sensor, the above-mentioned video line selection is not required, so the source region 16L can be configured in common.

The floating key 1/region 18L does not necessarily have to be shared. Also, in the above-mentioned embodiments,
The floating gate region 18 and each cell may have a common structure.

The video line selection circuit 32L and the transistor 40L are shown for comparison with FIG. 4, although they are not necessarily necessary.

In the above embodiment, the floating gate area 1
As a result, holes are accumulated as well, and a problem arises in that a pair of cell PCs constituting a cell block cannot be well separated.

Another embodiment that eliminates such inconvenience will be described. FIG. 6(A), 03) shows another embodiment of the present invention, FIG. 6(A) is a plan view corresponding to FIG. 1(A), and FIG. 6(A) is a plan view corresponding to FIG. (B) is an end view corresponding to FIG. 1 (I3), and is a view taken from the arrow ■ in FIG. 6 (A). In addition, in this embodiment, FIGS. 1 to 4
Components similar to those in the embodiment shown in the drawings will be designated by the same reference numerals and their description will be omitted.

In the embodiment shown in FIGS. 6A and 6B, the source region 46 is connected to the floating gate region 1.
It is located close to 8. That is, source region 4
6 and floating key 1/region 18 is WA, and the distance between source region 46 and control key 1/region 14 is WB, then the relationship is WA(WB. , since the potential barrier formed on the 70-channel upper region 18 side is higher than the potential barrier formed on the control caper region 14 side, the isolation between the cells 26 in the cell block is improved. .

Furthermore, in this embodiment, an aluminum film 44 is formed on the source region 46 and the floating gate region 18 with an insulating film 42 interposed therebetween. No light enters into the region 18, and holes are not accumulated in the floating gate region 18. As a result, the separation between the cells 26 is good. 44 does not need to be provided below the gate electrode 24, and may be provided above it.

Such improved isolation between the cells 26 can also be achieved by forming the floating gate region 18 deeper than the control gate region 14 as well as with respect to the channel region 12. floating ke 8-
This can also be achieved by making the impurity density of the control case 1-region 18 higher than that of the control case 1-region 14.

By any one of the above configurations or a combination of multiple configurations, it is possible to improve the separation between the cells 26 constituting the cell processor, and the cells p arranged by unit area can be improved.
The degree of integration of c can be significantly improved.

Next, the manufacturing process of the solid-state imaging device described above will be explained with reference to FIGS. 7(A) to 5).

As the substrate 10, antimony (sb) is used as 101
An n+ type silicon substrate doped to about 8on-3 is used. n-layer 50 in which the channel region 12 is formed
is formed on the substrate lo by epitaxial growth. That is, since the n-layer 5o is a layer in which electron-hole pairs are formed and further separated by incident light and the channel region 12 is formed, it is necessary to sufficiently remove dislocations, defects, etc. It is from. This n layer 5
o is formed to have a thickness of 57) to 10 μm, and an impurity density of about 1013 to 10 Crn.

Incidentally, in order to prevent recombination of the gear in the n-layer 50 and extend the life of the separated carrier, scaling for heavy metals may be applied.

Next, an oxide film 52A is formed over the entire surface of the n-layer 50, and wet etching is performed using an appropriate mask to form a part of the control gate region 14 and the insulation isolation region I8I. Oxide film 5 of the part corresponding to
2A is removed. This state is shown in FIG. 7(A).

Next, etching is performed on the fc, n layer 50,
A V-shaped recess is formed in which the control area 14 and the like are formed.

The etching of the n-layer 50 is carried out, for example, by anisotropic etching in a crystalline material. In silicon crystals, for example, crystal plane (111,1) has a property that the etching rate with alkaline solutions such as sodium hydroxide, potassium hydroxide, hydranone, etc. is extremely slow compared to other crystal planes. ], ], ), the etching speed is 3 to 0 for the crystal plane (1001).
．． It is about 4%. By utilizing such properties, etching of the n-layer 50 can be performed satisfactorily.

After this etching, the oxide film 52A is once removed as shown in FIG. 7(B).

Next, an oxide film 90 is formed over the entire surface of the n-layer 50. This oxide film 90 has a thickness of about 400× and is formed by immersing it in an oxygen atmosphere for about 10,000,140 minutes.

A 513N4 coating 9 is formed over the entire oxide film 90.
2 is formed with a film thickness of about 1200λ by CVD (chemical vapor deposition). Formation is carried out by exposure to a reactive gas atmosphere for approximately 8001.40 minutes. This state is shown in FIG. 7(C).

Zolazm etching is then performed using a suitable mask to remove the coating 92 in the portions corresponding to the isolation regions 18I.
is etched. This operation is performed at an atmospheric pressure of 0-ITorr.
The test is carried out in a mixed gas atmosphere of CF4 and 02. The state after this operation is completed is shown in FIG. 7 (■).

In a similar operation, as shown in FIG. 7, the sea urchin oxide film 90 is also etched.

Oxidation is then performed to form S r 07 layer 94 corresponding to isolation region 18T. In this case, the n-layer 50 exposed by the etching may be etched by plasma to a thickness of about 1 μm. This plasma etching operation is performed, for example, on PCt3.
It is carried out in a gas atmosphere. The situation at the end of this operation is shown in FIG.

Next, using a suitable mask, plasma etching is performed to control the coating 92 in the control area I4.
The patterns of the p+ layers 54 and 56 corresponding to the floating case region 18 are formed as shown in FIG. impurities are injected. With this operation,
As shown in FIG. 7(J), the p+ layers 54, 5
6 is about 1 to 5 μm, preferably 1 to 3 μm.
It is formed to have a film thickness of approximately 100 m. The impurity injection method is as follows:
It may also be done by thermal diffusion after vapor deposition of impurities.
Alternatively, it may be done by the Aeon Otsu two person method. In the case of thermal diffusion, for example, impurities are implanted in an OOC oxygen or wet oxygen (or water vapor) atmosphere.

Next, 0.1. The film 92 is removed by plasma etching in a gas atmosphere of Torr, CF+4, and 02, and the oxide film 90 is removed by Gund oxidation deetching. This state is shown in FIG. 7(I).

Next, an oxide film 52 is formed over the entire surface of the n-layer 50. This operation is performed by immersing the film in an oxygen atmosphere of 1100 U for about 30 minutes, and the film thickness is, for example, about 5000×. (See Figure 7(J)).

Next, to form the r layer 60 corresponding to the source region 16, mask alignment is performed, and the source of the n+ layer 60 is formed in the oxide film 52 by wet etching (
(See Figure 7). In this state, an impurity that can serve as a donor, such as arsenic (AS), is implanted by thermal diffusion or ion implantation. Through this operation, an n+ layer 60 is formed as shown in FIG. 7(L).

Next, a DOPO8 (IJn-implanted polycrystalline silicon) layer 92 is formed over the entire surface as shown in FIG. 7(b). This DOPO8 layer 62 has S+T(4
It is formed by a CVD (chemical vapor deposition) method using a gas atmosphere of and PH3.

Next, a portion of the DOPO8 layer 62 is etched by plasma etching using a suitable mask to form an electrode layer 64 corresponding to the source electrode 22. This state is shown in FIG. For plasma etching, CF4°CF4 and 02 or pct3
A gas atmosphere such as

Next, over the entire surface, a PSG (phosphorus glass) layer 6
6 is formed as an interlayer insulating layer as shown in FIG. 7(0). This PSG layer 66 is formed by a CVD method, for example, by heating to about 400° C. in a gas atmosphere (of S+H4,02 and PH3). Alternatively, it is heated to about 750° C. in a gas atmosphere of S + H4 + H20 and PT (3).

Next, wet etching is performed using an appropriate mask to expose the surface of the p-soil layer 54, as shown in FIG. 7(P).

Next, an insulating layer 6 of Si3N4 is applied over the entire surface.
8 is formed as shown in FIG. 7(Q).

The insulating layer 68 is formed by CVD to a thickness of 400 to 700× in a gas atmosphere of SiH 4 and NI (3).

Next, a transparent electrode layer 70 made of SnO2 or DOPO8 is formed over the entire surface as shown in FIG. 7(R). This electrode layer 70 is formed by CVD using 5bCt5 or the like to a thickness of, for example, about 3000X.

Next, plasma etching is performed using a suitable mask, and the electrode layer 70 is etched except for the portion on the p-layer 54, as shown in FIG. 7(S). This operation is CCt4. CF4+CF4 and o2 or P
This is done using a gas such as Ct6.

Through the above operations, the solid-state imaging device in the embodiment shown in FIGS. 1 to 4 is manufactured. Note that, for the sake of explanation, only the main parts of the apparatus shown in FIGS. 1 and 2 are shown. Further, the position and shape of the n10 layer 60 corresponding to the source region 16 are shown in FIG.
This can be easily accomplished by appropriately changing the shape of the mask in step K).

Next, the formation of the light shielding film 44 explained in the embodiment shown in FIGS. 6(A) and 6(B) will be explained in FIG.
This will be explained with reference to T) to 5). The light shielding film formed in the following steps is provided parallel to the gate electrode 24, that is, the electrode layer 70 shown in FIG. 7(S).

First, a portion of the insulating layer 68 above the p-layer 56 is etched by plasma etching using a suitable mask. This operation is carried out using, for example, a CF4 gas atmosphere (see FIG. 7(T)).

Next, the exposed PSG layer 66 is wet-etched.
Then, the oxide film 52 is etched as shown in FIG. 7(b).

Next, as shown in FIG. 7(V), an aluminum light shielding layer 72 is formed over the entire surface with a thickness of about 10 μm. This light shielding layer 72 is formed by vacuum deposition using an electron beam or resistance heating, or by sputtering.

Next, a part of the light shielding layer 72 is etched using a suitable mask, and an electrode layer 80 made of aluminum is formed on the substrate IO. This state is shown in Figure 7 (6
) is shown. This electrode layer 80 is formed by, for example, a method such as sintering.

Note that the light shielding layer 72 has a 70-ting dart area 18.
It is connected to the p layer 56 corresponding to the p layer 56 and functions as an electrode for applying voltage to the floating gate region 18.

The manufacturing process described above is only an example, and other manufacturing processes may be used. Further, other materials may be used. For example, the n-layer 50 may be an intrinsic semiconductor layer into which no impurity is implanted. However, as the insulating layer 68, 5102. At203. Kuntal oxide or a composite film thereof may be used.

In any of the above embodiments, the channel is formed by this layer, but the channel may be formed by an intrinsic or p- semiconductor layer. Also,
Even if the source and drain correspond to each other in the opposite manner to those in the first embodiment, the same effect can be achieved. The same applies to the selection of the video line or the application of the voltage for reading, and the above embodiment may be reversed.

The driving transistor 40 may be a normal transistor, or the transistor 40, the read address circuit 30, and the video line selection circuit 32 may be integrated with the imaging device to form an integrated circuit. good. Although silicon is mainly used as the material, the present invention is not limited to this in any way, and kermanium, III-V group compound semiconductors, etc. can also be used.

Furthermore, in order to obtain color image information, the matrix of the cell PC is configured to correspond to, for example, red (R), green (G), and blue (B), and the incident light is filtered to color R, G, B
What is necessary is to separate the lights and make them incident on each corresponding cell PC.

As explained above, according to the solid-state imaging device according to the present invention, the uneven portion is formed on the surface of the semiconductor layer, and the cage region (particularly the control gate region where light enters) is provided in the depression, and Since the source region is placed only on one side of the control canid region, the light-receiving area of the cell can be effectively expanded, and the degree of integration can be improved while maintaining sufficient sensitivity. 4. Since the cells in the four parts are separated by an insulating layer, the cells can be separated well.

) However, since such uneven portions are formed by utilizing the anisotropy and tinging characteristics of the crystal, the manufacturing process is simplified and has the advantage of high precision.

[Brief explanation of the drawing]

FIG. 1(A) is a partial plan view showing an embodiment of a solid-state imaging device according to the present invention, FIG. 1(B) is a schematic end view as seen from the arrowhead in FIG. 1(A), and FIG. 3(A) is a perspective view showing a portion of the semiconductor layer, and FIG. 3(B) is a perspective view showing another shape of the semiconductor layer. 4 is a circuit diagram showing the configuration of an equivalent electric circuit, FIG. 5 is a partially cutaway plan view showing an embodiment of the line sensor according to the present invention, and FIG. 6 (A) is a solid-state imaging sensor according to the present invention. Another figure 6 (B) of the apparatus is a schematic end view seen from the direction of arrow V in figure 6 (, A), and figures 71 to 5) are explanatory diagrams showing an example of the manufacturing process. Explanation of symbols of main parts 12... Channel area, 14... First gate area, 16... Source area, 18... Second gate area, 18... ...insulation isolation region, pc...cell. Patent applicant Jun Nishizawa - Fuji Photo Film Co., Ltd.

Claims (1)

[Scope of Claims] 1. A plurality of cells configured by SIT are arranged in which a first gate region is formed on the surface of a semiconductor layer including a channel region, and each cell has a structure corresponding to the amount of light incident on each cell. In the solid-state imaging device in which the current flowing through the source region and the drain region changes due to the accumulation of carriers in the first gate region, an uneven portion is formed on the surface of the semiconductor layer, and the first gate region a region is formed in the convex portion and an inclined portion spanning four parts, and one of the source region and the drain region is located near the periphery of the first gate region and is formed in the convex portion;
isolation between the cells in at least the recess is formed by an insulating isolation region that is partially formed and extends deep into the channel region, and is of the same conductivity type as the first gate region and is of the same conductivity type as the first gate region. A solid-state imaging device characterized in that at least a separation between each cell in the convex portion is formed by a second case-1 region independent of the region. 2. In the device according to claim 1, the cells are arranged in two dimensions, each cell forms one cell block for every two cells, and one cell block has a convex portion. symmetrical across the two first case areas, and arranged between the two first case areas and in the two first case areas. a common single second gate region, one of the source region and the drain region respectively disposed between the first and second gate regions, and an insulator surrounding them; A solid-state imaging device comprising a separation region. 3. In the device according to claim 1 or 2, the semiconductor layer has a surface having a predetermined crystal plane,
A solid-state imaging device, wherein the uneven portion is formed by anisotropic etching of the semiconductor device.