JP2959460B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a charge-coupled (CCD) type two-dimensional solid-state imaging device.

[0002]

2. Description of the Related Art FIG. 7 is a plan view for explaining the overall structure of a solid-state image pickup device. Reference numeral 101 denotes a photodiode for performing photoelectric conversion; 102, a vertical CCD register for transferring electric charges in a vertical direction; A horizontal CCD register for transferring in the horizontal direction, 104 is a charge detection unit for detecting charges, 105 is an amplifier, and 110, 111, and 112 indicate the transfer direction of charges. The operation of this solid-state imaging device is roughly as follows. First, an image pattern is projected on a solid-state imaging device, and charges corresponding to the light intensity incident on the two-dimensionally arranged photodiodes are accumulated in each photodiode 101. After a lapse of a predetermined time, the accumulated charges are transferred to the vertical CCD register 102 as shown by an arrow 110. Subsequently, the charges are transferred to the vertical CCD register 102.
Are transferred downward as indicated by an arrow 111, and then transferred horizontally by a horizontal CCD register 103 as indicated by an arrow 112.
After being converted into a voltage, the voltage is output through an amplifier 105.

FIG. 8A shows a photodiode and a vertical CC.
FIG. 8B is an enlarged plan view for explaining the conventional structure of the D register, and FIG. 8B is a sectional view taken along line XX of FIG. 8A. Reference numeral 11 denotes an N-type semiconductor substrate made of single-crystal silicon, 21 denotes a P-type region (P-well) on the surface of the N-type semiconductor substrate 11, and 12 denotes an N-type region (formed on the surface of the P-type region 21) to become a photodiode. 13) is a region which is a transfer channel of the CCD register, and 22 is a P which is in contact with the bottom of the N-type region 13.
A high-concentration P-type region provided on the surface of the photodiode (12) for suppressing a current generated at the Si / SiO ₂ interface; Is a P-type region serving as a read channel of a transfer gate (MOS transistor); 31 is an insulating film;
2 is an interlayer insulating film, 41 and 42 are charge transfer electrodes made of polycrystalline silicon, 51 is a light shielding film provided to prevent light from entering the CCD register, and 61 and 62 are optical paths, respectively.

In this element, a photodiode having a PN junction is constituted by the N-type region 12 and the P well (21),
Electrons generated by photoelectric conversion by the light 61 incident on the mold region 12 are accumulated in the N-type region 12. The electrode 41 is N
A MOS transistor together with the pattern region 12, the transfer channel 13 of the vertical CCD register, and the P-type region 25;
By applying a voltage pulse of 10 to 15 V to the electrode 41, electrons accumulated in the photodiode (12) are converted into a vertical CCD.
Transfer to register. After that, -5 to -1 is applied to the electrode 41.
By applying a voltage pulse of 0 V, electrons are transferred in the vertical CCD channel in a direction perpendicular to the plane of FIG. 8B. At this time, since the P-type region 25 serving as the channel of the MOS transistor is cut off, the charge accumulated in the photodiode does not flow out.

In general, the sensitivity of a solid-state imaging device depends on the amount of electrons generated in a photodiode by photoelectric conversion. When the semiconductor substrate is silicon, the depth (absorption depth) at which the light incident on the photodiode surface is attenuated in the silicon and becomes 1 / e in intensity (absorption depth) is 5 for red at a wavelength of 700 nm.
μm, 2 μm for green at 550 nm, and 1.4 μm for blue at 450 nm. On the other hand, the depth of the photodiode (12) in a solid-state imaging device currently in practical use is about 1 μm, and a considerable amount of incident red and green light passes through the photodiode, so that the incident light is Is 1
It is not used effectively for 00%.

Therefore, in order to improve the sensitivity, the depth of the photodiode (12) is preferably formed to be as deep as 2 to 5 μm. As a result, the size of the photodiode is increased, and the 7 μm
It cannot be applied to a small pixel of × 7 μm. Further, it is impossible to cope with future miniaturization of pixels.

FIG. 8 shows the light incident on the solid-state imaging device.
As shown in (b), a light component 61 which is perpendicularly incident on the surface.
Then, there is a light component 62 incident from an oblique direction. The light 62 incident from an oblique direction reaches the P well 21 near the transfer channel 13 and generates electric charges in the corresponding region. Among them, electrons flow into the transfer channel 13. If there is a bright spot with a strong intensity in a part of the image pattern incident on the solid-state imaging device, a large amount of electrons generated by the oblique light 62 enter the CCD register at that part, so that a vertical stripe-like false signal appears on the imaging screen. (Smear) occurs. This needs to be reduced because it greatly degrades the image quality.

[0008]

As a method for improving the above-mentioned problem, there is a pixel structure described in Japanese Patent Application Laid-Open No. 64-33963. This is because, as shown in FIG. 9, a P well 21 formed on the surface of a P ⁺ type silicon substrate 211 is formed.
2. N ⁺ type region 2 formed on the surface of P well 212
13 (storage diode), an N ⁺ type region 214 which is a transfer channel of a vertical CCD register, a P ⁺ type region 215 for separating elements, and transfer electrodes 216a and 216b are an N ⁺ type polycrystalline silicon electrode 217, an insulating film 218, Cr Electrode 21
9, N ⁺ -type polycrystalline silicon film 220, i-type amorphous SiC: H film 221, high-resistance amorphous Si: H film 2
22, a transparent electrode 224 made of a P-type amorphous SiC: H film 223 and an ITO film.

In this device, light incident on the surface of the device is transmitted through the ITO film 224 and has high resistance amorphous Si:
The photoelectric conversion is performed by the H film 222. A negative voltage is applied to the ITO film 224 with respect to the P well 212, and the generated electrons are transferred to the Cr electrode 219 and the n + -type polycrystalline silicon film 220.
Flows into the lower electrode composed of
13 is stored. The stored electrons are transferred to the vertical CCD register (214) by applying a positive voltage pulse to the electrode 216a after a predetermined storage time, and then the CCs are transferred.
The data is transferred to the output section in the D register in a direction perpendicular to the page.

In the second conventional example, since the amorphous Si: H film 222 for performing photoelectric conversion can be formed as thick as several μm, there is a characteristic that the sensitivity is high. Note that the i-type amorphous SiC: H film 221 is provided to prevent holes from being injected from the lower electrode.
The film 223 is provided to prevent electron injection from the upper electrode 224. This is because the band gap of SiC is S
The advantage is that it is 2.1 eV, which is wider than 1.1 eV of i.

In the second conventional example, the light incident on the solid-state image pickup device is sufficiently attenuated and then the vertical CCD register (21) is turned off.
Since the method reaches 4), there is a feature that generation of smear is small. However, the structure is complicated and the number of manufacturing steps is large, and more electrons are generated in a dark state where light is blocked.
Was bad. On the other hand, the solid-state imaging device having the conventional structure shown in FIG. 8 (first conventional example) has a feature that the structure is relatively simple, the number of manufacturing steps is small, the number of electrons generated in the dark state is small, and the S / N is good. Therefore, there has been a demand for a method of increasing the sensitivity with such a structure.

An object of the present invention is to provide a solid-state imaging device having higher sensitivity and less generation of smear than the first conventional example and a simpler structure than the second conventional example.

[0013]

According to the present invention, there is provided a solid-state imaging device including a photoelectric conversion element array in which a plurality of photodiodes are arranged in a row and a vertical register coupled to each of the photodiodes. A second conductivity type region formed on the surface of the first conductivity type region on the surface of the single crystal semiconductor substrate made of the first material ;
Optical absorption coefficient large in the visible region than the second conductivity type region
And a second conductivity type single crystal semiconductor layer made of a second material and laminated on the second conductivity type region.

Here, the second conductivity type single crystal semiconductor layer can be provided in a convex shape with respect to the surface of the single crystal semiconductor substrate.

Further, a first conductivity type diffusion layer may be provided on the side face of the convex portion of the second conductivity type single crystal semiconductor layer.

Further, a first conductivity type diffusion layer may be formed on the surface of the convex portion of the second conductivity type single crystal semiconductor layer.

In the above, the first material is Si, the second material is Ge, Si _x Ge ₁ -x (0 <x <1), GaAs
s, GaP, InP, BP or _{In 1-y Ga y As Z} P
_1-Z (0 ≦ y <1, 0 ≦ z <1). It may be a multilayer film comprising a single crystal semiconductor layer of a second material phase Naru different. When both the first material and the second material are Si, the second conductivity type single crystal semiconductor layer is provided in a convex shape as described above.

The photoelectric conversion efficiency of the photodiode is increased by using a material having a large light absorption coefficient as the second material or by making the second material convex.

[0019]

FIG. 1A is a plan view showing a first embodiment of the present invention, and FIG. 1B is a sectional view taken along line XX of FIG. 1A.

This embodiment is directed to a solid-state imaging device including a photoelectric conversion element array in which a plurality of photodiodes (101 in FIG. 7) are arranged in a row and a vertical CCD register 102 coupled to each photodiode 101. Reference numeral 101 denotes an N-type region 12 formed on the surface of the P-type region 21 on the surface of the single crystal semiconductor substrate made of the first material (silicon), and a light absorption coefficient in a visible region larger than that of the N-type region 12. And a single-crystal semiconductor layer 71 made of a second material and laminated on the N-type region 12. As the second _{material, Ge, Si x Ge 1-} x (0
<X <1), GaAs, GaP, In _1-y Gay As _z
P _1-z (0 ≦ y <1, 0 ≦ x <1) and the like.

Since such a material has a large light absorption coefficient as its property, its absorption depth is 1/2 to that of silicon.
Can be shallow to 1/4. Therefore, 0.1 μm to 0.5 μm
By providing such a thickness, light incident on the solid-state imaging device can be efficiently captured. For this reason, the sensitivity to visible light, particularly red and green light, can be improved. Further, since light is sufficiently absorbed by the N-type single crystal semiconductor layer 71 which is the upper layer of the photodiode, the intensity of light transmitted through the N-type region 12 provided on the surface of the silicon substrate which is the lower layer of the photodiode is reduced. Therefore, there is an effect that smear is suppressed.

The N-type single-crystal semiconductor layer 71 is provided in a concave portion on the surface of the single-crystal semiconductor substrate, and the surface of the N-type single-crystal semiconductor layer 71 has a convex shape protruding from the surface of the single-crystal semiconductor substrate. I have. When the light absorption coefficient of the second material is larger than that of the first material (silicon), the second material does not necessarily have to be convex. The second material may be silicon, but in that case, a similar effect can be obtained by making the second material convex.

Next, the manufacturing method of the first embodiment will be described.

First, as shown in FIG. 2A, a P-type region 21 (P-well) is formed on the surface of an N-type silicon substrate 11, and then an N-type region 12, which is a lower layer of the photodiode, is formed.
In addition, the P-type region 22, the N-type region 13, the high-concentration P-type region 23 for separation, and the P-type region 25 are formed by using a known technique such as an ion implantation method. Next, as shown in FIG. 2B, a gate insulating film 31 of silicon oxide or the like is formed, and is formed of, for example, a transfer electrode 42 made of a first polysilicon film and a second polysilicon film 41. The transfer electrode 41 is formed. The transfer electrodes 42 and 41 is assumed to be insulated with a silicon oxide film or the like. Next, a P-type region 24 is formed using an ion implantation method.

Next, as shown in FIG. 2C, an interlayer insulating film 32 is formed on the surfaces of the transfer electrodes 41 and 42 by, for example, a thermal oxidation method.
Then, a refractory metal film 50 such as tungsten is formed, and an insulating film 33 such as silicon oxide is formed by a chemical vapor deposition method or the like. Next, the insulating film 33, the high-melting-point metal film 50, the interlayer insulating film 32, and the gate insulating film 31 are etched by photolithography, and FIG.
An opening 52 is formed as shown in FIG. The high melting point metal film 50 becomes the light shielding film 51. Next, as shown in FIG. 3A, an insulating film 34 such as a silicon oxide film is deposited on the entire surface, and is subjected to anisotropic etching, so that the side surface of the opening 52 is formed as shown in FIG. The spacer 34a is formed. next,
By etching the exposed P-type region 24 to expose the N-type region 12, as shown in FIG.
0 is formed. Next, an N-type single-crystal semiconductor layer 71 is formed in the recess 80 as shown in FIG. Next, an insulating film 35 is formed as shown in FIG.

As the N-type single crystal semiconductor layer 71, Ge or S
To grow i _X Ge _1-X (for example, x = 0.8)
800 using GeH ₄ or SiH ₄ -GeH ₄ mixed gas
The epitaxial growth is performed at a temperature of about ° C.

In the case of growing GaAs crystal, 700
By using a gas of GaCl ₅ and AsH ₃ at a temperature of about ° C., a crystal can be grown on silicon by a vapor phase epitaxial growth method.

When Ge or GaAs is grown on silicon, a single crystal cannot be obtained unless the lattice constants match.

For example, for a lattice constant of Si of 0.543 nm, Ge is 0.565 nm and GaAs is 0.565 nm.
And a thickness of about 0.1 μm allows a single crystal layer to be formed. To form a thicker single crystal layer, for example, after forming a Ge layer to a thickness of about 0.1 μm,
By repeatedly forming an i-layer of about 0.1 μm and forming a Ge layer again, a thick single-crystal semiconductor layer can be formed by forming a single-crystal semiconductor film having a stacked structure of Ge and Si.

When GaAs is used as the single crystal semiconductor layer, a laminated structure film of Si and GaAs may be used. However, a laminated structure film obtained by epitaxially growing a crystal film made of another material such as GaP on the GaAs layer may be used. You can do that, and you are free to choose. Note that, in a film in which materials such as Ge and GaAs are stacked, band discontinuity occurs at a junction, and therefore, it is necessary to consider a combination of materials. S
In the case of the combination of i and GaAs, band discontinuity does not occur for electrons, which is a preferable combination.

FIG. 4 is a sectional view showing a unit pixel portion according to a second embodiment of the present invention. In the figure, the same symbols as those in FIG. 1 have the same functions, 36 is a silicon oxide film (BSG film) containing boron at a high concentration, 37 is an insulating film such as silicon oxide, and 72 is a P-type diffusion layer. , 91 are transparent electrodes such as ITO. In the present embodiment, the portion in contact with the insulating film (36) at the side wall portion of the N-type single crystal semiconductor layer 71 is formed as a P-type, so that the current (dark current) generated at the interface between the crystal and the insulating film is formed. ) Can be reduced by about one digit. A transparent electrode 91 is provided above the N-type single-crystal semiconductor layer 71 with an insulating film 37 interposed therebetween. Is set to a state where holes are generated in the N-type single crystal semiconductor layer 7.
The current generated from the interface between the semiconductor device 1 and the insulating film 37 can be reduced.

As a method for converting the side wall of the N-type single crystal semiconductor layer 71 to P-type, for example, as shown in FIG. 3B, after forming a spacer 34a, a BSG film is provided on the entire surface, and then this is formed. The BSG film 36 may be left on the side wall of the opening by performing anisotropic dry etching. Thereafter, the high-concentration P-type impurity layer 24 in the opening is removed, and a structure similar to that of FIG. 3C is formed. Next, an N-type single-crystal semiconductor layer 71 is epitaxially grown, and by performing a heat treatment thereafter, boron contained in the BSG film is solid-phase diffused into the N-type single-crystal semiconductor layer 71 to form a P-type diffusion layer 72. .

FIG. 5 shows a sectional structure of a unit pixel portion according to a third embodiment of the present invention. In the drawing, the same symbols as those in FIG. 1 have the same functions. In the present embodiment, P-type diffusion layer 73 is formed not only on the side wall of N-type single-crystal semiconductor layer 71 but also on the upper part. Therefore, the portion of the N-type single-crystal semiconductor layer in contact with the insulating film is P-type on both the side wall and the upper portion, and the current generated from the interface between the crystal and the insulating film can be reduced. Such a structure is similar to that shown in FIG.
It can be formed by using the SG film 38. This structure has an advantage that the transparent electrode 91 used in the second embodiment and the application of a negative voltage are not required.

FIG. 6 shows a sectional structure of a unit pixel portion according to a fourth embodiment of the present invention. In the figure, the same symbols as those in FIG. 1 indicate the same functions, and reference numeral 41b denotes an electrode made of a compound (silicide) of a metal such as W, Mo or Ti and silicon.

In this embodiment, the transfer electrodes (4 in FIG. 1)
1, 42) are a polysilicon film 41a and a silicide film 41.
The silicide electrode has the advantage that the structure of the device can be simplified by also having the function of the light shielding film 51 in FIG. In this case, it is not necessary to adopt a structure in which the transfer electrode 41 partially overlaps with the transfer electrode 42 as in the case of FIG. 1, and the stacked film patterns of the same layer are separated and arranged at intervals of about 0.2 μm. You may. This is possible with microfabrication technology. In that case, the transfer electrode can be formed only of the tungsten film instead of the stacked film. In addition, the high-concentration P-type region 23 for isolation may be designed in a pattern such that the tungsten film is completely covered in a portion other than the above-mentioned interval portion.

[0036]

As described above, in the solid-state imaging device according to the present invention, the second conductivity type single crystal semiconductor layer having a larger light absorption coefficient in the visible region than the single crystal semiconductor substrate is selected on the surface of the single crystal semiconductor substrate. By forming the photodiode by growing it, the sensitivity to visible light, particularly red and green light, can be improved. Further, since the light is sufficiently absorbed by the second conductive type single crystal semiconductor layer in the upper layer of the photoelectric conversion portion, the intensity of light incident on the first conductive type region in the lower layer is reduced, so that smear is also suppressed. There is also an effect. Further, by providing the first conductivity type diffusion layer on the surface of the single crystal semiconductor layer in contact with the insulating film, the generated current in the dark can be reduced as much as the conventional structure device shown in FIG. 8 and a high S / N value is obtained. be able to.

[Brief description of the drawings]

FIG. 1 is a plan view (FIG. 1A) showing a pixel portion according to a first embodiment of the present invention, and a cross-sectional view taken along line XX of FIG. 1A.

FIGS. 2A to 2D are cross-sectional views illustrating the manufacturing method according to the first embodiment in the order of steps shown in FIGS.

FIG. 3 is a cross-sectional view in the order of steps, which is separated from (a) to (d) following FIG. 2;

FIG. 4 is a cross-sectional view illustrating a pixel unit according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a pixel unit according to a third embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a pixel unit according to a fourth embodiment of the present invention.

FIG. 7 is a plan view for explaining the overall structure of the solid-state imaging device.

8 is a plan view showing a pixel portion of a first conventional example (FIG.
(A)) and a sectional view taken along line XX of FIG.
(B)).

FIG. 9 is a cross-sectional view showing an image pixel section of a second conventional example.

[Explanation of symbols]

11 N-type semiconductor substrate 21, 22, 23, 24, 25 P-type region 31, 32, 33, 34, 35, 36, 37, 38
Insulating film 34a Spacer 41, 42 Transfer electrode 41a Polysilicon film 41b Silicide film 51 Light shielding film 52 Opening of light shielding film 61, 62 Optical path 71 N type single crystal semiconductor layer 72, 73 P type diffusion layer 80 Depression 101 Photo diode 102 Vertical CCD register 103 Horizontal CCD register 104 Charge detector 105 Amplifier 211 P ⁺ type silicon substrate 212 P well 213 N ⁺ type region 214 N ⁺ type region 215 P ⁺ type region 216 a, 216 b Transfer electrode 217 N ⁺ type polycrystalline silicon electrode 218 Insulating film 219 Cr electrode 220 N ⁺ -type polycrystalline silicon electrode 221 i-type amorphous SiC: H film 222 High-resistance amorphous Si: H film 223 Transparent electrode

Continuation of front page (56) References JP-A-58-12481 (JP, A) JP-A-2-14076 (JP, A) JP-A-3-25975 (JP, A) JP-A-4-113674 (JP) JP-A-5-347399 (JP, A) JP-A-9-172155 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/14-27/148 H01L 29/762-29/768 H04N 5/335

Claims (6)

(57) [Claims] 1. A solid-state imaging device including a photoelectric conversion element row in which a plurality of photodiodes are arranged in a row and a vertical register coupled to each of the photodiodes, wherein the photodiode is a single crystal semiconductor made of a first material. a second conductivity type region formed in a surface portion of the first conductivity type region of the surface portion of the substrate, made of a second material the optical absorption coefficient is large in the visible region than the second conductivity type region and the second conductivity type And a second conductivity type single crystal semiconductor layer stacked in the region. 2. The solid-state imaging device according to claim 1, wherein the second conductivity type single crystal semiconductor layer is provided in a convex shape with respect to a surface of the single crystal semiconductor substrate. 3. The solid-state imaging device according to claim 1, wherein a first conductivity type diffusion layer is provided on a side surface of the convex portion of the second conductivity type single crystal semiconductor layer. 4. The method according to claim 1, wherein the second conductive type single crystal semiconductor layer has
The solid-state imaging device according to claim 3, wherein a first conductivity type diffusion layer is formed. 5. The first material is Si, the second material is Ge,
Si _x Ge _1-x (0 <x <1), GaAs, GaP, I
nP, BP or _{In 1-y Ga y As Z} P 1-Z (0 ≦ y <
The solid-state imaging device according to claim 1, wherein any one of 1, 0 ≦ z <1) is satisfied. 6. The solid-state imaging device according to claim 1, wherein the single crystal semiconductor layer is a multilayer film made of different second materials.