KR100326267B1 - Image sensor and method for fabricating the same - Google Patents

Abstract

An object of the present invention is to provide an image sensor in which the capacitance of a photodiode is increased, the photosensitivity is improved with respect to a short wavelength, and the efficiency of transferring the photocharge generated in the photodiode to the floating diffusion is increased, and a method of manufacturing the same. the photodiode of the image sensor of the present invention is P- epi-layer and, N is formed in the P- epi ^layer and the ion implanted layer, ^{N-ion-implanted} layer inside the P- epitaxial layer on the ^{upper-ion-implanted} layer in contact with the N N ⁰ on the ion-implanted layer, and a P- epitaxial layer surface formed on the inner P- epi layer between the ion implanted layer and P ^0, P ⁰ P ⁰ in contact with the ion implanted layer and the ion implantation layer and the P- epitaxial layer surface formed And an epitaxially grown P ⁺ epilayer. In addition, the ^N-ion implantation layer and the N ⁰ ion implanted ^layer, the ion implantation layer and the N ⁰ ion implantation layer is formed that their side edges to the gate electrode edge of the transfer transistors are substantially aligned, the N , so as to be in contact with each other in the gate electrode edge portion of the transfer transistor and the P ⁰ ion implantation layer is formed, and spaced apart horizontally from the gate electrode edges, is also separated from said P ⁺ epitaxial layer also horizontally from the gate electrode edge do. Accordingly, the photodiode of the present invention forms a P / N / P / N / P diode in the active region of the photo sensing region and forms a PN diode at the gate electrode edge of the transfer transistor.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor having a photodiode having a large capacitance,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) image sensor, and more particularly, to a CMOS image sensor having a photodiode with a large capacitance and a manufacturing method thereof.

CCD is complicated in driving method, consumes a large amount of power, has a complicated process due to a large number of mask process steps, can not implement a signal processing circuit in a CCD chip, and has a drawback in that it is difficult to form one chip In order to overcome such drawbacks, the development of a CMOS image sensor using sub-micron CMOS manufacturing technology has been extensively studied. A CMOS image sensor forms a photodiode and a mos transistor in a unit pixel to detect an image sequentially by a switching method. Since a CMOS manufacturing technology is used, power consumption is low and the number of masks is about 20 to 30 to 40 Compared to a CCD that requires a single mask, the process is very simple, and it is possible to use several signal processing circuits and one chip, which is getting the spotlight as a next generation image sensor. However, since the image quality is lower than that of CCD until now, efforts are underway to improve it. That is, in a CCD or CMOS image sensor, a photodiode is an introduction part that converts incident light according to each wavelength into an electrical signal. In an ideal case, when the photomultiplier generation efficiency is 1 at all wavelength bands, This is an ongoing effort.

FIG. 1 is a circuit diagram of a typical CMOS image sensor unit pixel (unit pixel), which is composed of one photodiode PD and four MOS transistors. The four MOS transistors are composed of a transfer transistor Tx, a reset transistor Rx, A drive transistor MD, and a select transistor Sx. A load transistor is formed outside the unit pixel so as to read an output signal. Cfd represents the capacitance of the floating diffusion.

2 shows a layout of a photodiode PD, a transfer transistor Tx and a reset transistor Rx in a unit pixel of a CMOS image sensor according to the related art. In FIGS. 3A to 3D, A 'in Fig.

The photodiode manufacturing process according to the prior art will be described with reference to FIGS. 2 and 3A to 3D.

First, a wafer on which a low-concentration P-epi layer 1 is grown on a P ⁺ silicon substrate is prepared, and then a field oxide film 2 and a gate oxide film 3 and a gate electrode 4 of transistors are formed Reference). Only the gate electrode 204 of the transfer transistor Tx and the gate electrode 202 of the reset transistor Rx are shown. Subsequently, a mask pattern 5 is formed, and low-concentration high-energy ion implantation is performed to form an N ^- ion implantation region 6 in the P-epi layer 1 of the photodiode active region (see FIG. 3B). 2, the N ^- ion implantation mask pattern 5 is designed such that the open region 206 covers the active region edge edge, not the active region 205. And is designed to expose one side of the gate electrode 204 of the transfer transistor.

Subsequently, the mask pattern 5 is removed, a mask pattern 5 'is formed, and a high-concentration low-energy ion implantation is performed to form a P ⁰ ion implantation region 7 below the surface of the P-epi layer 1 (See FIG. 3C). 2, the P ⁰ ion implantation mask pattern 5 'is formed such that the open region 207 thereof is the entire active region 205 and the gate electrode 204 of the transfer transistor is exposed. do.

3D shows a state in which the gate sidewall spacer 8 and the source / drain junction 9 of the transistors are formed and then the interlayer insulating film 10 is formed. The source / drain junction connecting the transfer transistor and the reset transistor becomes the floating diffusion 203, and the other junction of the reset transistor becomes the drain junction 201 receiving the VDD.

As described above, the conventional photodiode P / N / P-type bar consisting of a photodiode, P / N / P-type photodiode and P- epi layer (1), N ^- ion implanted region 6 And a P ⁰ ion implantation region 7.

The N ^- ion implanted region 6 serves as a depletion region for collecting photogenerated charge generated by incident photons. And P ⁰ the ion implantation region 7 is N ^- ion implanted region 6 is fully serve to deplete, as well as by increasing the number under the photoelectric which may collect in the photo-sensing area to achieve an increase in the capacitance (Charge Capacity) light sensitivity to In order to increase the number. So P ⁰ ion implanted region 7 with the interior of the N ^- in order to fully deplete the ion-implanted region 6 and N ^- is the dopant concentration of the ion-implanted region 6 than P ⁰ ion implantation region 7 is relatively higher .

However, the conventional photodiodes having such a structure are confined to a limited wavelength band, increasing the capacitance and photosensitivity. That is, there is no problem in the case of a long wavelength of red light or green light, but since blue light of a short wavelength can not penetrate deeply into the silicon substrate (P-epi layer) The photogenerated charge generated by the photon is much reduced because the P ⁰ ion implanted region 7 exists on the surface, and the photosensitivity is relatively reduced. Therefore, a problem arises in implementing a color image due to a deficient blue color.

Further, in the prior art, are P ⁰ ion implantation region 7 are formed is ion-implanted so that the alignment to the gate electrode 204, the edge of the transfer transistor, and in a subsequent thermal process after the P ⁰ dopant ion implantation region 7 Not only the efficiency of transferring the generated photoelectrons to the floating diffusion 203 is reduced, but also the amount of photoelectrons that can overcome such a high potential barrier There is a problem in that it takes more time to collect enough photoelectrons to cause a problem in implementing a moving image.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image sensor in which the capacitance of a photodiode is increased and the photosensitivity is improved with respect to a short wavelength, and a method of manufacturing the same.

It is another object of the present invention to provide an image sensor that increases the efficiency of transferring light charges generated in a photodiode to floating diffusion, and a method of manufacturing the same.

1 is a circuit diagram of a typical CMOS image sensor unit pixel (unit pixel).

2 is a partial plan view of a unit pixel of a conventional CMOS image sensor.

FIGS. 3A to 3D are cross-sectional views showing a manufacturing process sequence according to A-A 'in FIG. 2; FIG.

4 is a partial plan view of a unit pixel of a CMOS image sensor according to the present invention.

5A to 5G are cross-sectional views illustrating a manufacturing process sequence according to A-A 'in FIG. 4;

DESCRIPTION OF THE REFERENCE NUMERALS

1: P-epi layer 6A: N ^- ion implanted layer

6B: N ⁰ ion implantation layer 7: P ⁰ ion implantation layer

11: P ⁺ epilayer

According to an aspect of the present invention, there is provided an image sensor having a photodiode and a transfer transistor, the photodiode including: a first conductive semiconductor layer; A first ion-implanted layer of a second conductivity type formed in the semiconductor layer; A third ion-implanted layer of a first conductivity type formed in the semiconductor layer in the upper region of the first ion-implanted layer in contact with the first ion-implanted layer; A second ion-implanted layer of a second conductivity type formed in the semiconductor layer between the third ion-implanted layer and the surface of the semiconductor layer in contact with the third ion-implanted layer; And an epi layer of a first conductivity type epitaxially grown on the surface of the semiconductor layer.

In the photodiode of the present invention having the above structure, in the reset process, the third ion-implanted layer and the semiconductor layer have a dopant concentration capable of completely depleting the first ion-implanted layer, Has a dopant concentration capable of completely depleting the third ion-implanted layer, and the epi-layer has a dopant concentration capable of completely depleting the second ion-implanted layer.

Preferably, the first ion-implanted layer and the second ion-implanted layer are formed by substantially aligning one side edge of the first ion-implanted layer and the second ion-implanted layer at the gate electrode edge of the transfer transistor, The second ion implantation layer is formed horizontally spaced apart from the gate electrode edge of the transfer transistor so that the second ion implantation layer is in contact with the gate electrode edge portion and the epi layer is also separated from the gate electrode edge of the transfer transistor And is horizontally spaced apart.

Preferably, a portion of the first and second ion-implanted layers is horizontally spaced apart from the edge of the field insulating film so that the semiconductor layer, the third ion-implanted layer, and the epi-layer contact each other at the edge portions of the field- .

According to another aspect of the present invention, there is provided a method of manufacturing an image sensor, including: forming a field insulating layer on a first conductive semiconductor layer; Patterning a gate electrode of the transfer transistor on the semiconductor layer separated from the field insulating film by a photo-sensing region where the photodiode is to be formed; Forming a first ion implantation mask to expose one edge of the gate electrode and cover a portion of the semiconductor layer of the photo-sensing area; Forming a first ion-implanted layer in the semiconductor layer by ion-implanting a second conductive impurity; Implanting a second conductive impurity to form a second ion-implanted layer in the semiconductor layer above the first ion-implanted layer; Removing the first ion implantation mask; Forming a second ion implantation mask so that the semiconductor layer of the photo-sensing region is exposed while covering the one edge of the gate electrode; Implanting a first conductive impurity to form a third ion-implanted layer at an interface between the first ion-implanted layer and the second ion-implanted layer; And growing an epitaxial layer of a first conductivity type on the semiconductor layer exposed by the second ion implantation mask.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do. The same reference numerals are given to the same constituent elements as those of the prior art.

4 shows the layout of the photodiode PD, the transfer transistor Tx and the reset transistor Rx in the unit pixels of the CMOS image sensor according to the present invention, A 'in Fig.

The photodiode fabrication process according to the present invention will be described with reference to FIGS. 4 and 5A to 5G.

First, a wafer on which a low-concentration P-epi layer 1 is grown on a P ⁺ silicon substrate is prepared, and then a field oxide film 2 and a gate oxide film 3 and a gate electrode 4 of transistors are formed Reference). Only the gate electrode 204 of the transfer transistor Tx and the gate electrode 202 of the reset transistor Rx are shown.

Subsequently, a mask pattern 5 is formed, and a low-concentration high-energy ion implantation is performed to form an N ^- ion implantation region 6A in the P-epi layer 1 of the photodiode active region. Subsequently, The implantation proceeds to form the N ⁰ ion implanted region 6B on the N ^- ion implanted region 6A (see FIG. 3B). 4, the N-type ion implantation mask pattern 5 is designed such that the open region 206 covers the active region edge edge, not the active region 205 as a whole. And is designed to expose one side of the gate electrode 204 of the transfer transistor.

Subsequently, the mask pattern 5 is removed and a gate sidewall spacer 8 and a source / drain junction 9 of transistors are formed to form a drain junction 201 to which the floating diffusion 203 and VDD are applied ( 5c).

Then, a planarized first insulating film 10 is formed, a mask pattern 20 is formed to form a P-type impurity layer, and the first insulating film 10 is etched. 4, the mask pattern 20 is designed such that the open region (207a in FIG. 4) is the entire active region 205 and completely covers the gate electrode 204 of the transfer transistor.

Then removing the mask pattern 20 and the N ^- forms an ion implanted region (6A), the ion implantation to P ⁰ ion implantation layer 7 a P- type impurity in the energy is less than the energy in the form (see Fig. 5e ). At this time, the impurity amount of the P ⁰ ion implantation layer 7 not only can completely deplete the N ^- ion implanted region 6A in the photo sensing region, but also allows the N ⁰ ion implantation layer 6B to perform the reset process Lt; RTI ID = 0.0 > depletion < / RTI >

Then, the P-epi layer 11 is grown on the substrate exposed by the first insulating film 10 (see FIG. 5F). At this time, the thickness of the epi layer 11 is formed to be very thin to about 0.01 to 0.05 μm And at the same time, it is necessary to maintain a high concentration of impurities so that the N ⁰ ion implantation layer 6B can be completely depleted in the reset process.

Next, as shown in FIG. 5G, rapid thermal annealing is performed to activate the p-type impurity by lattice defects of silicon and ion implantation, and the second insulating film 12 is deposited and planarized.

Hereinafter, the image sensor structure of the present invention manufactured by the above-described method and the characteristic effects of the structure will be described in detail with reference to FIG. 5G.

Referring to Figure 5g, the photodiode of the image sensor according to the present invention N is formed in the P- epitaxial layer 1 and the P- epitaxial layer ⁽¹⁾ ion-implanted layer (6A) and the ^N- ion-implanted layer (6A) and in contact with the ^N-ion implantation layer (6A) of the upper P- epitaxial layer (1), P ⁰ ion implantation layer formed therein (7) and P ⁰ the ion injection layer (7) An N ⁰ ion implantation layer 6 B formed inside the P-epi layer 1 between the P ⁰ ion implantation layer 7 and the surface of the P-epi layer 1 in contact with the P- And a P ⁺ epitaxial layer 11 epitaxially grown on the surface of the substrate 1.

The N ^- ion implanted layer (6A) and the N ⁰ ion implanted layer (6B) is formed that their side edges are substantially aligned to the gate electrode (204 in Figure 4) edge of the transfer transistor, the N ^- The P ⁰ ion implantation layer 7 is formed on the gate electrode 204 of the transfer transistor so that the ion implantation layer 6 A and the N ⁰ ion implantation layer 6 B are in contact with each other at the edge portion of the gate electrode 204. And the P ⁺ epi layer 11 is horizontally spaced apart from the edge of the gate electrode 204 of the transfer transistor. Accordingly, the photodiode of the present invention includes a P / N / P / N / P diode in the active region of the photo sensing region, and a PN diode at the edge of the gate electrode 204 of the transfer transistor.

On the other hand, the P- epi-layer (1) and P ⁰ the ion injection layer 7 and the N said P ⁺ epitaxial layer 11 is in contact with each other at an edge of the field insulation film ⁽²⁾ ion-implanted layer (6A And the N ⁰ ion implantation layer 6B are formed so that a part thereof is horizontally spaced from the edge of the field insulating film 2. In addition, the P ⁰ ion injection layer 7 and the P- epitaxial layer 1 is the N ^- has a dopant concentration that can be fully depleted by the ion implantation layer (6A), the N ⁰ ion implanted layer (6B) Has a dopant concentration capable of completely depleting the P ⁰ ion implantation layer 7 and the P ⁺ epi layer 11 has a dopant concentration capable of completely depleting the N ⁰ ion implantation layer 6B. Accordingly, the photodiode of the present invention sufficiently connects the p-type conductive layers 1, 7 and 11 to each other in the reset process to completely deplete the n-type conductive layers 6A and 6B. That is, as is well known, in a diode having a plurality of vertically P / N junctions, the doping concentration must be reduced from the surface layer to the inner layer of the substrate to enable complete depletion. Further, a depletion layer can be formed deeply on the substrate, The P ⁺ epitaxial layer 11 has the largest doping concentration and the N ⁰ ion implantation layer 6 B, the P ⁰ ion implantation layer 7, the N ^- ion implantation layer 6 A, Layer (1).

The P ⁺ epitaxial layer 11 has a thickness of 0.01 to 0.05 탆 to increase the sensitivity to short-wavelength light.

Furthermore, when the N ^- ion implanted layer 6A is completely depleted, the P-epi layer is lower than the P ⁰ ion implanted layer 7 so that a depletion layer of the photodiode is deeply formed in the P- Dopant concentration.

When the photodiode structure of such a photodetecting region is formed, the electrostatic capacity of the photodiode is greatly increased because it has a P / N / P / N / P junction structure, thereby greatly increasing the photoconductive efficiency of the photodiode do.

Further, since the P ⁺ epitaxial layer 11 expands the depletion layer to the silicon surface and the P ⁺ epitaxial layer 11 having a thickness of 0.01 to 0.05 탆 is present, the photosensitivity to blue light having a short wavelength Can be increased. As a result, it is possible to realize a clearer color in implementing a color image and increase the margin of time for collecting light charges.

Furthermore, since the photodiode of the present invention is formed in the NP-type at the transfer gate edge portion, the potential barrier is suppressed and the N-type conductive layer partially increases the potential well, so that the photocharge is more easily directed toward the floating diffusion .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

Since the image sensor of the present invention has the P / N / P / N / P junction structure under a limited area and the photodiode having the NP junction structure at the gate edge of the transfer transistor, , The photoelectric charge generating efficiency is greatly increased, the photoelectric charge transfer efficiency is increased, and the photosensitivity to short wavelength light is greatly improved.

Claims (11)

1. An image sensor having a photodiode and a transfer transistor, The photodiode includes: A semiconductor layer of a first conductivity type; A first ion-implanted layer of a second conductivity type formed in the semiconductor layer; A third ion-implanted layer of a first conductivity type formed in the semiconductor layer in the upper region of the first ion-implanted layer in contact with the first ion-implanted layer; A second ion-implanted layer of a second conductivity type formed in the semiconductor layer between the third ion-implanted layer and the surface of the semiconductor layer in contact with the third ion-implanted layer; And An epi layer of a first conductivity type epitaxially grown on the surface of the semiconductor layer . The method according to claim 1, Wherein the first ion-implanted layer and the second ion-implanted layer are formed by substantially aligning one side edge thereof with the gate electrode edge of the transfer transistor. 3. The method of claim 2, Wherein the third ion-implanted layer is horizontally spaced from the gate electrode edge of the transfer transistor so that the first ion-implanted layer and the second ion-implanted layer are in contact with each other at the gate electrode edge portion. sensor. The method of claim 3, Wherein the epi layer is horizontally spaced from the gate electrode edge of the transfer transistor. 5. The method according to any one of claims 1 to 4, The first and second ion-implanted layers are formed so that a part of the first and second ion-implanted layers are horizontally spaced from the edge of the field insulating film so that the semiconductor layer, the second ion-implanted layer, and the epi- Features an image sensor. 6. The method of claim 5, Wherein the doping concentration is the highest in the epitaxial layer, and gradually decreases in the order of the second ion-implanted layer, the third ion-implanted layer, the first ion-implanted layer, and the semiconductor layer. The method according to claim 6, Wherein the epi layer has a thickness of 0.01 to 0.05 占 퐉. The method according to claim 6, Wherein the semiconductor layer has a lower dopant concentration than the third ion-implanted layer such that a depletion layer is formed deeply into the semiconductor layer when the first ion-implanted layer is fully depleted. A method of manufacturing an image sensor, Forming a field insulating film on the first conductive semiconductor layer; Patterning a gate electrode of the transfer transistor on the semiconductor layer separated from the field insulating film by a photo-sensing region where the photodiode is to be formed; Forming a first ion implantation mask to expose one edge of the gate electrode and cover a portion of the semiconductor layer of the photo-sensing area; Forming a first ion-implanted layer in the semiconductor layer by ion-implanting a second conductive impurity; Implanting a second conductive impurity to form a second ion-implanted layer in the semiconductor layer above the first ion-implanted layer; Removing the first ion implantation mask; Forming a second ion implantation mask so that the semiconductor layer of the photo-sensing region is exposed while covering the one edge of the gate electrode; Implanting a first conductive impurity to form a third ion-implanted layer at an interface between the first ion-implanted layer and the second ion-implanted layer; And Growing an epitaxial layer of a first conductivity type on the semiconductor layer exposed by the second ion implantation mask The method comprising the steps of: 10. The method of claim 9, In the resetting process, the third ion-implanted layer and the semiconductor layer may have a dopant concentration capable of completely depleting the first ion-implanted layer, and the second ion-implanted layer may completely deplete the third ion- Wherein the epitaxial layer has a dopant concentration such that the epitaxial layer has a dopant concentration capable of completely depleting the second ion implanted layer. The method according to claim 9 or 10, Wherein the epitaxial layer is formed to a thickness of 0.01 to 0.05 mu m.