JPH09213923A - Solid-state image pickup apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high sensitivity, reduce the occurrence of smear and simplify the structure by comprising photo diodes, each having a second conductivity type region formed on the surface of a first conductivity type region of a first material-made single crystal semiconductor substrate and second material-made second conductivity type single crystal semiconductor layer laminated on the second conductivity type region. SOLUTION: A photo diode has an n-type region formed on the surface of a p-type surface region of a first material (Si)-made single crystal semiconductor substrate and single crystal semiconductor layer which is made of a second material having a higher photo absorption coefficient in visible range than that of the region 12 and laminated on this region 12. The second material has a high optical absorption coefficient and hence the absorption depth can be as shallow as 1/2-1/4 of that of Si. By setting the depth to about 0.1-0.5 microns, a light incident on a solid-stage image pickup apparatus can be efficiently caught to improve the sensitivity to the visible light. The light is absorbed enough by the semiconductor layer 71 to reduce the intensity of the light passing through the region 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a charge coupled (CCD) type two-dimensional solid-state image pickup device.

[0002]

2. Description of the Related Art FIG. 7 is a plan view for explaining an overall structure of a solid-state image pickup device. Reference numeral 101 is a photodiode for photoelectric conversion, 102 is a vertical CCD register for vertically transferring charges, and 103 is a charge. A horizontal CCD register that transfers charges in the horizontal direction, a charge detection unit 104 that detects charges, an amplifier 105, and 110, 111, and 112 indicate charge transfer directions. The operation of this solid-state imaging device is as follows. First, an image pattern is projected on the solid-state image pickup device, and charges corresponding to the light intensity incident on the two-dimensionally arranged photodiodes are accumulated in each photodiode 101. After a lapse of a predetermined time, the accumulated charge is transferred to the vertical CCD register 102 as shown by an arrow 110. Then, the charge is applied to the vertical CCD register 102.
Of the charge detector 104 is transferred downward as indicated by an arrow 111, and then horizontally by the horizontal CCD register 103 as indicated by an arrow 112.
After being converted into a voltage by, it is output through the amplifier 105.

FIG. 8A shows a photodiode and a vertical CC.
8B is an enlarged plan view for explaining the conventional structure of the D register, and FIG. 8B is a cross-sectional view taken along line XX of FIG. 8A. Reference numeral 11 is an N-type semiconductor substrate made of single crystal silicon, 21 is a P-type region (P well) on the surface of the N-type semiconductor substrate 11, and 12 is an N-type region (a surface of the P-type region 21) to be a photodiode. 13 is an area which is a transfer channel of the CCD register, and 22 is P which is in contact with the bottom surface of the N-type area 13.
23 is a high-concentration P-type region for separating elements, 24 is a high-concentration P-type region provided on the surface of the photodiode (12) to suppress the current generated at the Si / SiO ₂ interface, 25 Is a P-type region serving as a read channel of a transfer gate (MOS transistor), 31 is an insulating film, 3
Reference numeral 2 is an interlayer insulating film, 41 and 42 are charge transfer electrodes made of polycrystalline silicon, 51 is a light shielding film provided to prevent light from entering the CCD register, and 61 and 62 are optical paths.

In this element, the N-type region 12 and the P well (21) form a PN junction photodiode,
Electrons generated by photoelectric conversion by the light 61 incident on the mold region 12 are accumulated in the N-type region 12. Electrode 41 is N
A MOS transistor is formed with the mold region 12, the transfer channel 13 of the vertical CCD register, and the P-type region 25,
Electrons stored in the photodiode (12) are applied to the vertical CCD by applying a voltage pulse of 10 to 15 V to the electrode 41.
Transfer to register. After that, the electrode 41 is -5 to -1.
By applying a voltage pulse of 0 V, electrons are transferred in the vertical CCD channel in the vertical direction to the paper surface of FIG. At this time, since the P-type region 25 serving as the channel of the MOS transistor is under the cut-off condition, the outflow of the charges accumulated in the photodiode does not occur.

In general, the sensitivity of a solid-state image pickup device depends on the amount of electrons generated in a photodiode by photoelectric conversion. When the semiconductor substrate is silicon, the depth (absorption depth) at which the light incident on the photodiode surface is attenuated in the silicon and becomes 1 / e intensity (absorption depth) is 5 for a red wavelength of 700 nm.
The thickness is 2 μm for green of 550 nm and 1.4 μm for blue of 450 nm. On the other hand, the depth of the photodiode (12) in the solid-state imaging device which is currently put into practical use is about 1 μm, and a considerable amount of incident red or green light passes through the photodiode, so that the incident light Is 1
Not being used 00% effectively.

Therefore, in order to improve the sensitivity, it is preferable to make the depth of the photodiode (12) as deep as 2 to 5 μm, but on the other hand, forming the PN junction deeply spreads widely in the lateral direction at the time of manufacturing. As a result, the size of the photodiode is increased, and it is now in practical use at 7 μm.
It cannot be applied to a small pixel of × 7 μm. In addition, it will not be possible to cope with future miniaturization of pixels.

The light incident on the solid-state image pickup device is shown in FIG.
As shown in (b), the light component 61 incident perpendicularly on the surface
Then, there is a light component 62 incident from an oblique direction. The light 62 incident from an oblique direction reaches the P well 21 near the transfer channel 13 and generates charges in the region, of which electrons flow into the transfer channel 13. When a part of the image pattern incident on the solid-state imaging device has a bright spot with high intensity, a large number of electrons generated by the oblique light 62 enter the CCD register at the part, so that a vertical stripe-shaped false signal appears on the imaging screen. (Smear) occurs. This significantly deteriorates the image quality and therefore needs to be reduced.

[0008]

As a method for improving the above-mentioned problems, there is a pixel structure described in JP-A-64-33963. As shown in FIG. 9, this is the P well 21 formed on the surface of the P ⁺ type silicon substrate 211.
2. N ⁺ type region 2 formed on the surface of the P well 212
13 (storage diode), an N ⁺ type region 214 which is a transfer channel of a vertical CCD register, a P ⁺ type region 215 for separating elements, transfer electrodes 216a and 216b are N ⁺ type polycrystalline silicon electrode 217, an insulating film 218, and Cr. Electrode 21
9, N ⁺ type polycrystalline silicon film 220, i type amorphous SiC: H film 221, high resistance amorphous Si: H film 2
22, a P-type amorphous SiC: H film 223, and a transparent electrode 224 made of an ITO film.

In this device, light incident on the surface of the device is transmitted through the ITO film 224, and high resistance amorphous Si:
The H film 222 is photoelectrically converted. A negative voltage is applied to the ITO film 224 with respect to the P well 212, and the generated electrons are generated by the Cr electrode 219 and the n + -type polycrystalline silicon film 220.
The storage diode 2 flows into the lower electrode composed of
It is accumulated in 13. The accumulated electrons are transferred to the vertical CCD register (214) by applying a positive voltage pulse to the electrode 216a after a predetermined accumulation time, and then this CC
The data is transferred in the D register to the output section in the direction perpendicular to the paper surface.

The second conventional example is characterized by high sensitivity because the amorphous Si: H film 222 for photoelectric conversion can be formed as thick as several μm. The i-type amorphous SiC: H film 221 is provided to prevent the injection of holes from the lower electrode.
The film 223 is provided to prevent injection of electrons from the upper electrode 224. This is because the band gap of SiC is S
It uses 2.1 eV, which is wider than 1.1 eV of i.

In the second conventional example, the light incident on the solid-state image pickup device is sufficiently attenuated and then the vertical CCD register (21
Since it reaches 4), there is a characteristic that smear is less likely to occur. However, since the structure is complicated and there are many manufacturing processes, many electrons are generated in a dark state where light is blocked, and S / N
It had the drawback of being bad. On the other hand, the solid-state imaging device having the conventional structure shown in FIG. 8 (first conventional example) has a relatively simple structure, few manufacturing steps, few electrons generated in a dark state, and good S / N. Therefore, a method of increasing the sensitivity with such a structure has been desired.

It is an object of the present invention to provide a solid-state image pickup device having higher sensitivity than the first conventional example, less smear generation, and a simpler structure than the second conventional example.

[0013]

A solid-state imaging device according to the present invention is a solid-state imaging device including a photoelectric conversion element array in which a plurality of photodiodes are arranged in a row and a vertical register coupled to each of the photodiodes. The diode has a light absorption coefficient in the visible region smaller than that of the second conductivity type region and the second conductivity type region formed on the surface part of the first conductivity type region of the surface part of the single crystal semiconductor substrate made of the first material. And a second conductivity type single crystal semiconductor layer which is made of a second material and is laminated on the second conductivity type region.

Here, the second conductivity type single crystal semiconductor layer may be provided in a convex shape on the surface of the single crystal semiconductor substrate.

A first conductivity type diffusion layer may be provided on the side surface of the convex portion of the second conductivity type single crystal semiconductor layer.

Furthermore, an inversion layer may be formed on the surface of the convex portion of the second conductivity type single crystal semiconductor layer.

In the above, the first material is Si, the second material is Ge, Si _x Ge _1-x (0 <x <1), GaA.
s, GaP, InP, BP or _{In 1-y Ga y As z} P
It can be any of _1-z (0 ≦ y <1, 0 ≦ z <1). The single crystal semiconductor layer can be a multilayer film made of a different second material. When both the first material and the second material are Si, the second conductivity type single crystal semiconductor layer is provided in a convex shape as described above.

The photoelectric conversion efficiency of the photodiode is increased by using a material having a large light absorption coefficient as the second material or by making the second material convex.

[0019]

1 (a) is a plan view showing a first embodiment of the present invention, and FIG. 1 (b) is a sectional view taken along line XX of FIG. 1 (a).

This embodiment is a solid-state image pickup device including a photoelectric conversion element array in which a plurality of photodiodes (101 in FIG. 7) are arranged in a row and a vertical CCD register 102 coupled to each photodiode 101. 101 is an N-type region 12 formed on the surface of the P-type region 21 on the surface of the single crystal semiconductor substrate made of the first material (silicon), and the light absorption coefficient in the visible region is larger than that of the N-type region 12. The single crystal semiconductor layer 71 made of the second material and stacked in the N-type region 12 is included. As the second material, Ge, Si _x Ge _1-x (0
<X <1), GaAs, GaP, In _1-y Gay As _z
P _1-z (0 ≦ y <1, 0 ≦ x <1) and the like can be mentioned.

Since such a material has a large light absorption coefficient as a property, it has an absorption depth of 1/2 to 0.5 as compared with silicon.
Can be made as shallow as 1/4. Therefore, 0.1 μm to 0.5 μm
By providing the light emitting device with a certain thickness, light incident on the solid-state imaging device can be efficiently captured. Therefore, the sensitivity of visible light, especially to red or green light, can be improved. Further, since light is sufficiently absorbed by the N-type single crystal semiconductor layer 71 which is the upper layer of the photodiode, the light intensity transmitted through the N-type region 12 provided on the surface of the silicon substrate which is the lower layer of the photodiode is reduced. Therefore, there is an effect that smear is also suppressed.

The N-type single crystal semiconductor layer 71 is provided in a concave portion of the surface portion of the single crystal semiconductor substrate, and the surface of the N-type single crystal semiconductor layer 71 has a convex shape protruding from the surface of the single crystal semiconductor substrate. There is. When the light absorption coefficient of the second material is larger than that of the first material (silicon), it does not necessarily have to be convex. The second material may be silicon, but in that case, the same effect can be obtained by making it convex.

Next, the manufacturing method of the first embodiment will be described.

First, as shown in FIG. 2A, a P-type region 21 (P-well) is formed on the surface of the N-type silicon substrate 11, and then an N-type region 12, which is a lower layer of the photodiode,
The P-type region 22, the N-type region 13, the high-concentration P-type region 23 for separation, and the P-type region 25 are formed by a well-known technique such as an ion implantation method. Next, as shown in FIG. 2B, a gate insulating film 31 made of silicon oxide or the like is formed, and is made of, for example, a transfer electrode 42 made of a first-layer polysilicon film and a second-layer polysilicon film 41. The transfer electrode 41 is formed. The transfer electrodes 42 and 41 are insulated by a silicon oxide film or the like. Next, using the ion implantation method, P
The mold region 24 is formed.

Next, as shown in FIG. 2C, for example, by a thermal oxidation method, the interlayer insulating film 32 is formed on the surfaces of the transfer electrodes 41 and 42.
Then, a refractory metal film 50 of tungsten or the like is formed, and an insulating film 33 of silicon oxide or the like is formed by a chemical vapor deposition method or the like. Next, the insulating film 33, the refractory metal film 50, the interlayer insulating film 32, and the gate insulating film 31 are etched by the photolithography method, and then, as shown in FIG.
The opening 52 is formed as shown in FIG. The refractory metal film 50 becomes the light shielding film 51. Next, as shown in FIG. 3A, an insulating film 34 such as a silicon oxide film is deposited on the entire surface, and anisotropic etching is performed to form a side surface of the opening 52 as shown in FIG. 3B. The spacer 34a is formed. next,
By etching the exposed P-type region 24 to expose the N-type region 12, as shown in FIG.
Form 0. Next, in this recess 80, as shown in FIG. 3D, an N-type single crystal semiconductor layer 71 is formed. Next, as shown in FIG. 1, the insulating film 35 is formed.

As the N-type single crystal semiconductor layer 71, for example, Si
When growing, use SiCl ₄ -based gas to
If epitaxial growth is performed at a temperature of about 000 ° C., a silicon layer having a thickness of about 0.5 μm can be selectively grown. Further, in order to grow Ge or Si _x Ge _1-x (for example, x = 0.8), epitaxial growth is performed at a temperature of about 800 ° C. by using GeH ₄ or SiH ₄ —GeH ₄ mixed gas.

When GaAs is crystal-grown, 700
Crystals can be grown on silicon by a vapor phase epitaxial growth method by using a gas of GaCl ₅ and AsH ₃ at a temperature of about ° C.

When crystallizing Ge or GaAs on silicon, a single crystal cannot be obtained unless the lattice constants match.

For Si lattice constant of 0.543 nm, for example, Ge has 0.565 nm and GaAs has 0.565 nm.
The single crystal layer can be formed with a thickness of about 0.1 μm. To form a single crystal layer thicker than this, for example, after forming a Ge layer of about 0.1 μm, S
A thick single crystal semiconductor layer can be formed by forming an i layer of about 0.1 μm and forming a Ge layer again to form a single crystal semiconductor film having a stacked structure of Ge and Si.

When GaAs is used as the single crystal semiconductor layer, a laminated structure film of Si and GaAs may be used, but a laminated structure film obtained by epitaxially growing a crystal film made of another material such as GaP on the GaAs layer. You can also make choices at your discretion. In a film in which materials such as Ge and GaAs are laminated, band discontinuity occurs at the junction, so it is necessary to consider the combination of materials. S
In the case of the combination of i and GaAs, band discontinuity does not occur for electrons, which is a preferable combination.

FIG. 4 is a sectional view showing a unit pixel portion according to the second embodiment of the present invention. In the figure, the same symbols as those in FIG. 1 have the same function, 36 is a silicon oxide film (BSG film) containing a high concentration of boron, 37 is an insulating film such as silicon oxide, and 72 is a P-type diffusion layer. , 91 are transparent electrodes such as ITO. In the present embodiment, a portion of the sidewall of the N-type single crystal semiconductor layer 71 that is in contact with the insulating film (36) is formed to be P-type, which causes a current (dark current) generated at the interface between the crystal and the insulating film. ) Can be reduced by about an order of magnitude. Further, a transparent electrode 91 is provided above the N-type single crystal semiconductor layer 71 via an insulating film 37, and a negative voltage is applied to the transparent electrode with respect to the P-type region 21 so that the surface of the N-type single crystal semiconductor layer 71 is covered. By setting the state in which holes are generated in the N-type single crystal semiconductor layer 7
It is possible to reduce the current generated from the interface between the insulating film 37 and the insulating film 37.

As a method of converting the side wall portion of the N-type single crystal semiconductor layer 71 into P-type, for example, as shown in FIG. 3B, after forming the spacer 34a, a BSG film is provided on the entire surface, and then this is performed. The BSG film 36 may be left on the sidewall of the opening by performing anisotropic dry etching. After this, the high-concentration P-type impurity layer 24 in the opening is removed, and a structure similar to that shown in FIG. 3C is formed. Next, the N-type single crystal semiconductor layer 71 is epitaxially grown, and by performing heat treatment thereafter, boron contained in the BSG film is solid-phase diffused into the N-type single crystal semiconductor layer 71, and a P-type diffusion layer 72 is formed. .

FIG. 5 shows a sectional structure of a unit pixel portion according to the third embodiment of the present invention. In the figure, the same symbols as those in FIG. 1 have the same functions. In the present embodiment, the P-type diffusion layer 73 is formed not only on the side wall of the N-type single crystal semiconductor layer 71 but also on the upper side thereof. Therefore, the side wall and the upper portion of the N-type single crystal semiconductor layer in contact with the insulating film are all P-type, and the current generated from the interface between the crystal and the insulating film can be reduced. This structure has a structure of B as the insulating film 37 in FIG.
It can be formed by using the SG film 38. This structure has an advantage that the transparent electrode 91 used in the second embodiment and the application of a negative voltage are unnecessary.

FIG. 6 shows a sectional structure of a unit pixel portion according to the fourth embodiment of the present invention. In the figure, the same symbols as those in FIG. 1 indicate those having the same function, and 41b is an electrode made of a compound (silicide) of a metal such as W, Mo or Ti and silicon.

In this embodiment, the transfer electrode (4 in FIG.
1, 42) is a polysilicon film 41a and a silicide film 41.
The silicide electrode is composed of the laminated film of b and has the advantage that the structure of the device can be simplified by having the function of the light shielding film 51 in FIG. In this case, it is not necessary to adopt a structure in which the transfer electrode 41 partially overlaps with the transfer electrode 41 as in the case of FIG. 1, and the laminated film patterns of the same layer and the next layer may be arranged at intervals of about 0.2 μm. May be. This is possible with fine processing technology. In that case, the transfer electrode can be formed only by the tungsten film instead of the laminated film. Further, the separation high-concentration P-type region 23 may be designed in such a pattern that the portion other than the above-mentioned spacing portion is completely covered with the tungsten film.

[0036]

As described above, in the solid-state image pickup device of the present invention, the second conductivity type single crystal semiconductor layer in which the light absorption coefficient in the visible region is not small (same or larger) on the surface portion of the single crystal semiconductor substrate. By selectively growing and forming a photodiode, the sensitivity of visible light, particularly red and green light, can be improved. Further, since light is sufficiently absorbed by the second conductivity type single crystal semiconductor layer that is the upper layer of the photoelectric conversion unit, the intensity of light that enters the first conductivity type region that is the lower layer is reduced, and smear is also suppressed. There is also the effect. By providing the first conductivity type diffusion layer on the surface of the single crystal semiconductor layer in contact with the insulating film, the generated current in the dark can be reduced to the same level as that of the conventional structure device shown in FIG. 8, and a high S / N value can be obtained. be able to.

[Brief description of drawings]

FIG. 1 is a plan view (FIG. 1A) showing a pixel portion according to a first embodiment of the present invention and a sectional view taken along line XX of FIG. 1 (a).

2A to 2D are cross-sectional views in order of the processes, which are divided into (a) to (d) for describing the manufacturing method according to the first embodiment.

3A to 3D are sectional views in order of the processes, which are illustrated in FIGS.

FIG. 4 is a sectional view showing a pixel portion according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a pixel portion according to a third embodiment of the present invention.

FIG. 6 is a sectional view showing a pixel portion according to a fourth embodiment of the present invention.

FIG. 7 is a plan view for explaining the overall structure of the solid-state imaging device.

FIG. 8 is a plan view showing a pixel portion of a first conventional example (FIG. 8).
(A)) and a sectional view taken along line XX of FIG.
(B)).

FIG. 9 is a sectional view showing an image pixel portion of a second conventional example.

[Explanation of symbols]

11 N-type semiconductor substrate 21, 22, 23, 24, 25 P-type region 31, 32, 33, 34, 35, 36, 37, 38
Insulating film 34a Spacer 41, 42 Transfer electrode 41a Polysilicon film 41b Silicide film 51 Light-shielding film 52 Light-shielding film opening 61, 62 Optical path 71 N-type single-crystal semiconductor layer 72, 73 P-type diffusion layer 80 Recess 101 Photodiode 102 Vertical CCD register 103 Horizontal CCD register 104 Charge detection unit 105 Amplifier 211 P ⁺ type silicon substrate 212 P well 213 N ⁺ type region 214 N ⁺ type region 215 P ⁺ type region 216a, 216b Transfer electrode 217 N ⁺ type polycrystalline silicon electrode 218 Insulating film 219 Cr electrode 220 N ⁺ type polycrystalline silicon electrode 221 i type amorphous SiC: H film 222 High resistance amorphous Si: H film 223 Transparent electrode

Claims (7)

[Claims] 1. In a solid-state imaging device including a photoelectric conversion element array in which a plurality of photodiodes are arranged in a row and a vertical register coupled to each of the photodiodes, the photodiode is a single crystal semiconductor made of a first material. The second conductivity type region formed on the surface part of the first conductivity type region of the surface part of the substrate and the second material having a light absorption coefficient in the visible region which is not smaller than that of the second conductivity type region. A solid-state imaging device comprising: a second conductivity type single crystal semiconductor layer laminated in a mold region. 2. The solid-state imaging device according to claim 1, wherein the second conductivity type single crystal semiconductor layer is provided in a convex shape on the surface of the single crystal semiconductor substrate. 3. The solid-state imaging device according to claim 1, wherein the first conductivity type diffusion layer is provided on the side surface of the convex portion of the second conductivity type single crystal semiconductor layer. 4. The solid-state imaging device according to claim 3, wherein an inversion layer is formed on the surface of the convex portion of the second conductivity type single crystal semiconductor layer. 5. The first material is Si, the second material is Ge,
Si _x Ge _1-x (0 <x <1), GaAs, GaP, I
nP, BP or _{In 1-y Ga y As z} P 1-z (0 ≦ y <
5. The solid-state imaging device according to claim 1, wherein any of 1,0 ≦ z <1) is satisfied. 6. The solid-state imaging device according to claim 1, wherein the single crystal semiconductor layers are multilayer films made of different second materials. 7. The solid-state imaging device according to claim 2, wherein both the first material and the second material are silicon.