JPS60167366A - Manufacture of solid-state image pickup device - Google Patents
Manufacture of solid-state image pickup deviceInfo
- Publication number
- JPS60167366A JPS60167366A JP60001826A JP182685A JPS60167366A JP S60167366 A JPS60167366 A JP S60167366A JP 60001826 A JP60001826 A JP 60001826A JP 182685 A JP182685 A JP 182685A JP S60167366 A JPS60167366 A JP S60167366A
- Authority
- JP
- Japan
- Prior art keywords
- photoelectric conversion
- conversion section
- switching element
- charge storage
- signal charge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 49
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000003860 storage Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 18
- 238000003384 imaging method Methods 0.000 claims description 17
- 238000005224 laser annealing Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000000969 carrier Substances 0.000 abstract 1
- 229920006395 saturated elastomer Polymers 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000009825 accumulation Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14665—Imagers using a photoconductor layer
- H01L27/14669—Infrared imagers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体基板上に走査同時及び光電変換素子を集
積化した固体撮像装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a solid-state imaging device in which simultaneous scanning and photoelectric conversion elements are integrated on a semiconductor substrate.
第３図は従来のＭＯＳ型固体撮像装置の一画素の断面を
示す。図において、１はｐ型半導体基板、２はＭＯＳ）
ランジスタ１４のソース、３．４゜７はそれぞれ上記Ｍ
Ｏ３）ランジスタ１４のドレイン、チャネル、ゲート、
５はフィールド酸化膜、６は垂直信号線、８は透明絶縁
膜である。また９は表面平坦化膜、１０は色フィルタ、
１１は保護膜、１２は遮光膜である。なお本装置ではＭ
ＯＳトランジスタ１４のソース２が光電変換部、ソース
２と基板１との接合面１３に形成された接合キャパシタ
ンスが信号電荷蓄積部となっており、以下この光電変換
部２及び信号電荷蓄積部１３を合わせて単に光電変換部
６０と呼称する。そしてスイッチング機能を有する上記
トランジスタ１４及び垂直信号線６によって、当該画素
の蓄積電荷量を外部に読出すようになっている。FIG. 3 shows a cross section of one pixel of a conventional MOS type solid-state imaging device. In the figure, 1 is a p-type semiconductor substrate, 2 is a MOS)
The source of transistor 14, 3.4°7, is the M
O3) drain, channel, gate of transistor 14,
5 is a field oxide film, 6 is a vertical signal line, and 8 is a transparent insulating film. Further, 9 is a surface flattening film, 10 is a color filter,
11 is a protective film, and 12 is a light shielding film. In this device, M
The source 2 of the OS transistor 14 is a photoelectric conversion section, and the junction capacitance formed at the junction surface 13 between the source 2 and the substrate 1 is a signal charge storage section. Together, they will be simply referred to as a photoelectric conversion section 60. The amount of charge accumulated in the pixel is read out to the outside by the transistor 14 having a switching function and the vertical signal line 6.
第３図は固体撮像装置の一画素の断面構造を示すもので
あるが、これを配列した装置全体の回路図を第４図に示
す。第４図において、２１は水平走査回路、２２は垂直
走査回路、２３は垂直信号線、２４は水平信号線であり
、これは各ＭＯＳトランジスタ１４のゲートに接続され
ている。また上記トランジスタ１４を含む破線で囲まれ
た部分２５が第３図でその断面を示した画素単位に相当
する。FIG. 3 shows the cross-sectional structure of one pixel of the solid-state imaging device, and FIG. 4 shows a circuit diagram of the entire device in which this is arranged. In FIG. 4, 21 is a horizontal scanning circuit, 22 is a vertical scanning circuit, 23 is a vertical signal line, and 24 is a horizontal signal line, which is connected to the gate of each MOS transistor 14. Further, a portion 25 surrounded by a broken line including the transistor 14 corresponds to a pixel unit whose cross section is shown in FIG.
従来の固体撮像装置は以上のように構成されており、そ
の製造は従来広く行なわれているＭＯＳトランジスタ形
成プロセスによってなされる。しかし、受光部がＭＯ３
Ｉ−ランジスタのソース部のみであるということから、
遮光膜がない場合は、他の部分に入射した光はＭＯＳト
ランジスタのスイッチング動作にかかわらない擬信号と
なってしまう等の悪影響を及ぼすことになる。このため
に部分的に遮光膜を設けているのであるが、同時にこれ
は光の利用率を低くしていることにもつながる。即ち、
第３図に示すような従来装置では、有効に光電変換され
る光量の割合を示す開口率が２０％〜３０％と大変低く
、またキャリアの蓄積部がソース部の下のｐｎ接合容量
だけであるので、飽和信号量が低いという欠点があった
。A conventional solid-state imaging device is constructed as described above, and is manufactured by a MOS transistor forming process that has been widely used in the past. However, the light receiving part is MO3
Since it is only the source part of the I-transistor,
If there is no light-shielding film, light incident on other parts will have an adverse effect, such as turning into a pseudo signal that is not related to the switching operation of the MOS transistor. For this reason, a light-shielding film is partially provided, but this also leads to a lower light utilization rate. That is,
In the conventional device shown in Fig. 3, the aperture ratio, which indicates the proportion of the amount of light that is effectively photoelectrically converted, is very low at 20% to 30%, and the carrier accumulation region is limited to only the pn junction capacitance under the source region. Therefore, there was a drawback that the saturation signal amount was low.
この発明は、かかる点に鑑みてなされたもので、遮光膜
が不要となると同時に光電変換部を著しく広くすること
ができ、開口率及びキャリアの蓄積能力、即ち飽和光量
が大幅に向上する固体撮像装置を得ることのできる固体
撮像装置の製造方法を提供することを目的としている。This invention was made in view of the above points, and at the same time eliminates the need for a light-shielding film, the photoelectric conversion section can be made significantly wider, and the aperture ratio and carrier accumulation ability, that is, the saturation light amount, can be greatly improved. It is an object of the present invention to provide a method for manufacturing a solid-state imaging device, which makes it possible to obtain a solid-state imaging device.
この発明に係る固体撮像装置の製造方法は、半導体基板
内に画素毎に第１の光電変換部及び読出しスイッチング
素子を形成する工程と、上記読出しスイッチング素子上
に絶縁膜を介して半導体層を形成し、該半導体層をレー
ザアニールにより再結晶化した後イオン注入及び熱アニ
ールを行なうことによって、上記読出しスイッチング素
子上に隣接する画素の上記第１の光電変換部に電気的に
接続された第２の光電変換部を形成する工程とからなる
ものである。The method for manufacturing a solid-state imaging device according to the present invention includes the steps of forming a first photoelectric conversion section and a readout switching element for each pixel in a semiconductor substrate, and forming a semiconductor layer on the readout switching element via an insulating film. Then, by recrystallizing the semiconductor layer by laser annealing and then performing ion implantation and thermal annealing, a second photoelectric conversion section electrically connected to the first photoelectric conversion section of the pixel adjacent to the readout switching element is formed. The process consists of a step of forming a photoelectric conversion section.
この発明においては、基板内に第１の光電変換部と読出
しスイッチング素子を形成した後、隣接画素上に形成さ
れた半導体層にレーザアニールを施すことによって、該
隣接画素上に上記第１の光電変換部の単結晶層に連続す
る単結晶シリコン層が形成され、さらに該単結晶層にイ
オン注入及び熱アニールを行なうことによって、上記第
１の光電変換部のｐｎ接合面と連続するｐｎ接合面を有
する第２の光電変換部が形成される。In the present invention, after forming the first photoelectric conversion section and the readout switching element in the substrate, laser annealing is performed on the semiconductor layer formed on the adjacent pixel, so that the first photoelectric conversion section and the readout switching element are formed on the adjacent pixel. A single crystal silicon layer continuous with the single crystal layer of the conversion section is formed, and by further performing ion implantation and thermal annealing on the single crystal layer, a pn junction surface continuous with the pn junction surface of the first photoelectric conversion section is formed. A second photoelectric conversion section is formed.
以下、本発明の実施例を図について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
ここで、本実施例の固体撮像装置の製造方法は、特に第
２の光電変換部の製造方法に特徴を有しており、これは
絶縁膜上に単結晶シリコンを形成する方法として最近そ
の手法が確立されてきたレーザアニール法を用いるもの
である。レーザアニールによる単結晶成長技術としては
文献（Ｊ、Ｐ、Ｇｏｌｉｎｇｅ 。Here, the manufacturing method of the solid-state imaging device of this embodiment is particularly characterized by the manufacturing method of the second photoelectric conversion section, which is a method that has recently been adopted as a method of forming single crystal silicon on an insulating film. This method uses the well-established laser annealing method. A single crystal growth technique using laser annealing is described in the literature (J. P. Golinge).
ｅｔ ａｌ ；Ａｐｐｌ、Ｐｈｙｓ、Ｌｅｔｔ、、４１
（１９８２） ３４６．）がある。そしてレーザアニ
ールによって単結晶化された領域に更にイオン注入を行
ない、熱アニールを加えることにより、光電変換領域及
び信号電荷蓄積領域を形成するものである。et al; Appl, Phys, Lett, 41
(1982) 346. ). Then, ions are further implanted into the region made into a single crystal by laser annealing, and thermal annealing is applied to form a photoelectric conversion region and a signal charge storage region.
第１図は本発明の一実施例による製造方法により得られ
た固体撮像装置を示し、図において、３１はｐ型半導体
基板、３２はＭＯ３Ｉ−ランジスタ５０のソース、３３
は同じくドレイン、３４．３５は同じくチャネル、ゲー
トである。３６は垂直信号線であり、画素の信号を外部
へ読出すための配線である。この配線には、ドープポリ
シリコン５モリブデン、タングステン等、高融点の材料
を用いる。３７はトランジスタ５０及び垂直信号線３６
を覆う絶縁膜である。FIG. 1 shows a solid-state imaging device obtained by a manufacturing method according to an embodiment of the present invention. In the figure, 31 is a p-type semiconductor substrate, 32 is a source of an MO3I transistor 50, and 33
is also the drain, and 34 and 35 are the channel and gate. A vertical signal line 36 is a wiring for reading out pixel signals to the outside. For this wiring, a high melting point material such as doped polysilicon 5 molybdenum or tungsten is used. 37 is a transistor 50 and a vertical signal line 36
It is an insulating film that covers the
そして本装置ではＭＯＳ）ランジスタ５０のソース３２
が第１の光電変換部、ソース３２と基板３１との接合面
５１が第１の信号電荷蓄積領域となっており、以下光電
変換部３２及び信号電荷蓄積領域５１を合わせて単に第
１の５光電変換部６０と呼称する。またスイッチング機
能を有するトランジスタ５０全体が上記第１の光電変換
部６０の電荷を読み出すスイッチング素子となっており
、このスイッチング素子と垂直信号線３６とにより走査
回路部が構成されている。In this device, the source 32 of the transistor 50 (MOS)
is the first photoelectric conversion section, and the bonding surface 51 between the source 32 and the substrate 31 is the first signal charge accumulation region. It is called a photoelectric conversion section 60. Further, the entire transistor 50 having a switching function serves as a switching element for reading out the charge of the first photoelectric conversion section 60, and this switching element and the vertical signal line 36 constitute a scanning circuit section.
また３８．３９は上記走査回路部上に絶縁膜３７を介し
て形成されたｐ型半導体層、及びｎ型半導体層で、ｎ型
半導体層３９は第２の光電変換部を、両半導体層３８．
３９の接合面５２は第２の信号電荷蓄積領域を形成して
いる。以下光電変換部３９及び信号電荷蓄積領域５２を
合わせて単に第２の光電変換部７０と呼称する。また４
０はフィールド酸化膜、４１は絶縁膜、４２は平用化膜
、４３は色フィルタ、４４は保護膜である。Reference numerals 38 and 39 denote a p-type semiconductor layer and an n-type semiconductor layer formed on the scanning circuit section with an insulating film 37 interposed therebetween. ．．
The bonding surface 52 of 39 forms a second signal charge accumulation region. Hereinafter, the photoelectric conversion section 39 and the signal charge storage region 52 will be simply referred to as a second photoelectric conversion section 70. Also 4
0 is a field oxide film, 41 is an insulating film, 42 is a flattening film, 43 is a color filter, and 44 is a protective film.
このように、本実施例における１画素は、各色フイルタ
下方のＭＯＳ）ランジスタ５０及び第１の光電変換部６
０と、その隣の色フイルタ下方の第２の光電変換部７０
により構成されており、また第１図に示した従来装置の
遮光膜は形成されていない。In this way, one pixel in this embodiment consists of the MOS transistor 50 below each color filter and the first photoelectric conversion unit 6.
0 and the second photoelectric conversion unit 70 below the color filter next to it.
Furthermore, the light shielding film of the conventional device shown in FIG. 1 is not formed.
このような構成になる本装置では、ＭＯＳトランジスタ
５０のソース３２と基板３１とのｐｎ接合面５１に逆バ
イアス電圧をかけておくが、絶縁いる。これは半導体層
３９がソース３２と同じｎ型導電性を示す領域であり、
半導体層３８が基板３１と同じｐ型導電性を示すからで
ある。そして、入射した光は、ソース３２近傍及び半導
体領域３８．３９で吸収され、このとき発生した電子正
孔対が、ｐｎ接合面５１及び５２に拡散し、蓄積電荷と
再結合を行なうことにより、逆バイアス電圧の大きさを
減少させることになる。即ち、光信号が蓄積される時間
は、ＭＯＳ）ランジスタ５０が非導通状態にある時間で
あり、基板３１及びｐ型半導体層３８の一定電位に対し
てフローティング状態のｎ型半導体領域３２及び３９の
電位が変化した大きさが、蓄積時間内の入射光総量に対
応する。この蓄積信号量は、信号読出し時にＭＯＳ）ラ
ンジスタ５０が導通状態となり、信号線３６から流れ込
んでくる電荷量と等しいので、外部で電流値を測定する
ことによって入射光信号の大きさがめられる。In this device having such a configuration, a reverse bias voltage is applied to the pn junction surface 51 between the source 32 of the MOS transistor 50 and the substrate 31, but insulation is required. This is a region where the semiconductor layer 39 exhibits the same n-type conductivity as the source 32,
This is because the semiconductor layer 38 exhibits the same p-type conductivity as the substrate 31. Then, the incident light is absorbed in the vicinity of the source 32 and the semiconductor regions 38 and 39, and the electron-hole pairs generated at this time diffuse to the pn junction surfaces 51 and 52 and recombine with the accumulated charges, so that This will reduce the magnitude of the reverse bias voltage. That is, the time during which the optical signal is accumulated is the time during which the MOS transistor 50 is in a non-conducting state, and when the n-type semiconductor regions 32 and 39 are in a floating state with respect to a constant potential of the substrate 31 and the p-type semiconductor layer 38. The magnitude of the change in potential corresponds to the total amount of incident light within the accumulation time. This accumulated signal amount is equal to the amount of charge that flows in from the signal line 36 when the MOS transistor 50 becomes conductive during signal reading, so the magnitude of the incident optical signal can be determined by measuring the current value externally.
以上述べた動作を行なう固体撮像装置の製造方法を第２
図（ａ）〜（ｈ）に示したプロセスフロー図を用いて説
明する。第２図（ａ）ではＭＯＳ）ランジスタ５０のゲ
ート３５．ソース３２．ドレイン３３が形成されており
、同図中）で第一層配線、即ち垂直走査線３６が高融点
材料を用いてドレイン３３側に形成される。次に絶縁膜
（例え、ば５ｉ０２）３７を減圧ＣＶＤ法等により全面
に形成し、そののちＭＯＳ）ランジスタ５０のソース３
２上部の絶縁膜のみを同図（Ｃ）に示すようにエツチン
グ除去する。このエツチング除去の時点において、ソー
ス３２と基板３１間のｐｎ接合は外表面に露出している
必要がある。これにｐ型のポリシリコン４５を堆積する
と同図（ｄ）に示すような構造になる。このｐ型ポリシ
リコン４５は、例えば減圧ＣＶＤ法によって形成できる
。更にポリシリコン４５を部分的にエツチングし、同図
（ｅ）に示すような構造にする。なおこのときｐ型ポリ
シリコン４５とｎ型のソース３２とは接触せずに離れて
いる方が好ましい。また、このポリシリコン４５のエツ
チングを行なう際、例えばＣＦａプラズマを用いること
ができるが、下地のＳｉが露出した時点でエツチングを
止める必要がある。同図（Ｐｉ）の状態でレーザアニー
ルによりｐ型ポリシリコン４５をｐ型車結晶シリコンに
再結晶化する。このとき、ｐ型ポリシリコン４５は基板
３１と接触しているために、基板３１の面方位を保って
再結晶化が行なわれる。The second method for manufacturing a solid-state imaging device that performs the operations described above is described below.
This will be explained using process flow diagrams shown in FIGS. (a) to (h). In FIG. 2(a), the gate 35 of a MOS transistor 50. Source 32. A drain 33 is formed, and a first layer wiring, that is, a vertical scanning line 36 (in the figure) is formed on the drain 33 side using a high melting point material. Next, an insulating film (for example, 5i02) 37 is formed on the entire surface by low pressure CVD, and then the source 3 of the MOS transistor 50 is formed.
Only the insulating film on top of 2 is removed by etching as shown in FIG. 2(C). At the time of this etching removal, the pn junction between the source 32 and the substrate 31 must be exposed to the outer surface. When p-type polysilicon 45 is deposited on this, a structure as shown in FIG. 2(d) is obtained. This p-type polysilicon 45 can be formed by, for example, a low pressure CVD method. Furthermore, the polysilicon 45 is partially etched to form a structure as shown in FIG. 4(e). Note that at this time, it is preferable that the p-type polysilicon 45 and the n-type source 32 be separated from each other without being in contact with each other. Further, when etching the polysilicon 45, for example, CFa plasma can be used, but it is necessary to stop the etching when the underlying Si is exposed. In the state shown in the figure (Pi), the p-type polysilicon 45 is recrystallized into p-type wheel crystal silicon by laser annealing. At this time, since the p-type polysilicon 45 is in contact with the substrate 31, recrystallization is performed while maintaining the plane orientation of the substrate 31.
またレーザアニールの際は、レーザビームの制御によっ
て、ｎ型半導体領域３２には照射されないようにしたほ
うが、ｎ型不純物の再拡散を抑える上で好ましい。次に
ひ素等のｎ型不純物の注入及び熱アニールによって、再
結晶化したシリコン層４５の表面及び９表面に露出して
いるｐ型半導体部６１の表面をｎ型半導体に変化させる
。この時の断面図が同図（ｆ）である。同図（ｆ）では
、ｎ型半導体層３２とｎ型半導体層３９とが電気的に接
続され、またｐ型半導体層３８は、再結晶化によって基
板３１のｐ型半導体と電気的に接続される。従ってそれ
らの界面であるｐｎ接合面５１及び５２は連続して形成
されている。これにバンシベーション膜４１を形成した
ものが同図（旬であり、平坦化膜４２９色フィルタ４３
．保護膜４４を形成すると同図（ｈ）に示す完成した構
造となる。Further, during laser annealing, it is preferable to control the laser beam so that it does not irradiate the n-type semiconductor region 32, in order to suppress re-diffusion of n-type impurities. Next, by implanting an n-type impurity such as arsenic and thermal annealing, the surface of the p-type semiconductor portion 61 exposed on the surface of the recrystallized silicon layer 45 and 9 is changed into an n-type semiconductor. The cross-sectional view at this time is shown in FIG. In FIG. 3F, the n-type semiconductor layer 32 and the n-type semiconductor layer 39 are electrically connected, and the p-type semiconductor layer 38 is electrically connected to the p-type semiconductor of the substrate 31 by recrystallization. Ru. Therefore, the pn junction surfaces 51 and 52, which are the interfaces between them, are formed continuously. The same figure shows the one on which a bancivation film 41 is formed (currently, a flattening film 429 and a color filter 43 are shown).
．． After the protective film 44 is formed, the completed structure shown in FIG. 4(h) is obtained.
ここで上記ＭＯ３）ランジスタ５０のゲート３５、ドレ
イン３３．フィールド酸化膜４０の上層に絶縁膜３７を
介して形成されている第２の光電変換部７０は、可視光
を十分吸収できるように厚くつくられている。例えば、
光電変換部の材料が上に示したような単結晶シリコンの
場合、その禁制帯幅以上のエネルギーの光に対する吸収
係数の値は１０４ｃｍ”以上であるので、１μｍの厚さ
で６０％以上、２μｍの厚さで９０％以上の光を吸収で
きる。Here, the MO3) gate 35, drain 33 . The second photoelectric conversion section 70, which is formed on the field oxide film 40 with the insulating film 37 in between, is made thick so that it can sufficiently absorb visible light. for example,
If the material of the photoelectric conversion part is single crystal silicon as shown above, the value of the absorption coefficient for light with energy above the forbidden band width is 104 cm or more, so it is 60% or more at a thickness of 1 μm, and 2 μm can absorb more than 90% of light with a thickness of .
このように、本実施例では画素毎に形成される光電変換
部を当該画素に隣接する画素の読み出しスイッチング素
子上にもレーザアニール法を利用して形成するようにし
たので、有効に光電変換される光量の割合を示す開口率
及びキ中リアの蓄積能力が大幅に向上した固体撮像装置
を再現性良く製造できる。In this way, in this example, the photoelectric conversion section formed for each pixel is also formed on the readout switching element of the pixel adjacent to the pixel using the laser annealing method, so that photoelectric conversion can be performed effectively. It is possible to manufacture a solid-state imaging device with high reproducibility in which the aperture ratio, which indicates the proportion of the amount of light that is generated, and the storage capacity of the central rear are significantly improved.
なお、上記実施例では、再結晶化させる材料として多結
晶シリコンを用いたが、これはアモルファスシリコンを
用いてもよい。In the above embodiment, polycrystalline silicon was used as the material to be recrystallized, but amorphous silicon may also be used.
また、上記実施例ではｐ型基板上に撮像装置を形成する
場合について説明したが、これはｎ型半導体でもよく、
この場合は形成する半導体領域の導電性を上記実施例の
場合とすべて逆にすればよい。Further, in the above embodiment, the case where the imaging device is formed on a p-type substrate has been described, but this may also be an n-type semiconductor.
In this case, the conductivity of the semiconductor region to be formed may be reversed from that in the above embodiment.
以上のように、この発明に係る固体撮像装置の製造方法
によれば、基板内に第１の光電変換部と読出しスイッチ
ング素子を形成した後、隣接画素上に形成された半導体
層をレーザアニールによって再結晶化し、該再結晶化層
にイオン注入及び熱アニールを行なって、隣接画素上に
上記第１の光電変換部に連続する第２の光電変換部を形
成したので、開口率の大きい高感度のものを再現性良く
製造できる効果がある。As described above, according to the method for manufacturing a solid-state imaging device according to the present invention, after forming the first photoelectric conversion section and the readout switching element in the substrate, the semiconductor layer formed on the adjacent pixel is removed by laser annealing. The recrystallized layer is then subjected to ion implantation and thermal annealing to form a second photoelectric conversion section continuous with the first photoelectric conversion section on an adjacent pixel, resulting in high sensitivity with a large aperture ratio. This has the effect of making it possible to manufacture products with good reproducibility.
第１図は本発明の一実施例により製造された固体撮像装
置を示す断面図、第２図（ａ）〜（ｈｌは本発明の一実
施例による固体撮像装置の製造方法を示すプロセスフロ
ー図、第３図は従来の固体撮像装置の一画素を示す断面
図、第４図は第３図の一画素を配列してなる従来装置の
全体構成を示す回路図である。
３１・・・ｐ型半導体基板、３２・・・ソース、３３・
・・ドレイ、ン、３４・・・チャネル、３５・・・ゲー
ト、３６・・・垂直信号線、３７・・・絶縁膜、３８・
・・ｐ型半導体層、３９・・・ｎ型半導体層、５１．５
２・・・接合面、５０・・・ＭＯＳ）ランジスタ（読出
しスイッチング素子）、６０・・・第１の光電変換部、
７０・・・第２の光電変換部。
代理人 早 瀬 憲 −
第２図
第２Ｗｉ
第２図
第３図
９FIG. 1 is a sectional view showing a solid-state imaging device manufactured according to an embodiment of the present invention, and FIGS. 2(a) to (hl are process flow diagrams showing a method for manufacturing a solid-state imaging device according to an embodiment of the present invention , FIG. 3 is a cross-sectional view showing one pixel of a conventional solid-state imaging device, and FIG. 4 is a circuit diagram showing the overall configuration of a conventional device formed by arranging one pixel of FIG. 3. 31...p type semiconductor substrate, 32...source, 33.
...Dray, N, 34...Channel, 35...Gate, 36...Vertical signal line, 37...Insulating film, 38...
...p-type semiconductor layer, 39...n-type semiconductor layer, 51.5
2... Junction surface, 50... MOS) transistor (readout switching element), 60... First photoelectric conversion unit,
70...Second photoelectric conversion section. Agent Ken Hayase - Figure 2 Figure 2Wi Figure 2 Figure 3 Figure 9
Claims (1)
該第１の光電変換部より入射光量に応じた電荷を読み出
す読出しスイッチング素子を形成する第１の工程と、上
記読出しスイッチング素子上にこれと絶縁してかつ隣接
−する画素の上記第１の光電変換部に電気的に接続して
第２の光電変換部を形成する第２の工程とを備えた固体
撮像装置の製造方法であって、上記第２の工程は、上記
読出しスイッチング素子上の第２の光電変換部となるべ
き部分に絶縁膜を介して半導体層を形成する工程。 該半導体層をレーザアニールにより再結晶化する工程、
及び該再結晶化層にイオン注入及び熱アニールを行ない
光電変換領域、信号電荷蓄積領域のそれぞれを上記第１
の光電変換部のそれと接続して形成する工程を含むもの
であることを特徴ζする固体撮像装置の製造方法。(1) A first step of forming a first photoelectric conversion section for each pixel in a semiconductor substrate and a readout switching element for reading out charges according to the amount of incident light from the first photoelectric conversion section, and forming a readout switching element on the readout switching element. and a second step of electrically connecting to the first photoelectric conversion section of an adjacent pixel to form a second photoelectric conversion section. The second step is a step of forming a semiconductor layer via an insulating film on a portion of the readout switching element that is to become a second photoelectric conversion section. recrystallizing the semiconductor layer by laser annealing;
Then, ion implantation and thermal annealing are performed on the recrystallized layer to form each of the photoelectric conversion region and the signal charge storage region as described above.
A method for manufacturing a solid-state imaging device, comprising the step of forming a photoelectric conversion section connected to the photoelectric conversion section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60001826A JPS60167366A (en) | 1985-01-08 | 1985-01-08 | Manufacture of solid-state image pickup device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60001826A JPS60167366A (en) | 1985-01-08 | 1985-01-08 | Manufacture of solid-state image pickup device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58192878A Division JPS6084870A (en) | 1983-10-14 | 1983-10-14 | Solid-state image pickup device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60167366A true JPS60167366A (en) | 1985-08-30 |
Family
ID=11512364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60001826A Pending JPS60167366A (en) | 1985-01-08 | 1985-01-08 | Manufacture of solid-state image pickup device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60167366A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5670382A (en) * | 1992-07-29 | 1997-09-23 | Nikon Corporation | Method for producing a solid state imaging device |
-
1985
- 1985-01-08 JP JP60001826A patent/JPS60167366A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5670382A (en) * | 1992-07-29 | 1997-09-23 | Nikon Corporation | Method for producing a solid state imaging device |
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