JPS624340A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a thick epitaxial layer, by growing the epitaxial layer including its portion surrounding an island region, on the surface of a semiconductor substrate, in several separate processes. CONSTITUTION:A substrate having a first type conductivity 1 is provided with diffused layers 2a and 2b having the first type conductivity and with a diffused layer 3 having the second type conductivity. An epitaxial layer 4 having the second type conductivity is then deposited by means of the epitaxy technique. The layer 4 is then provided with diffused layers 5a and 5b having the first type conductivity by means of the boron diffusion technique. Subsequently, an epitaxial layer 6 having the second type conductivity is deposited by means of the epitaxy technique. This process is repeated until the thickness of the epitaxial layer 6 attains a predetermined value. After that, diffused layers 7a and 7b having the first type conductivity and a dielectric film 9 are provided.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a semiconductor element is provided in a PN isolated island region, and is particularly suitable for manufacturing a high voltage semiconductor integrated circuit. 〇〇〇〇Conventional technology regarding methods　 Conventionally, the high-voltage field was not compatible with semiconductor integrated circuits, so commercialization of the field was delayed. However, recently, the field of application of integrated circuits has expanded, and there has been a growing demand for the integration of semiconductor circuits in the high voltage field.

By the way, when attempting to utilize semiconductor integrated circuit technology in the field of high breakdown voltages, the first problem is the separation between the two. This is especially true in bipolar IC systems suitable for power applications.

The device isolation method used for manufacturing high-voltage integrated circuits is as follows:
A typical example is the dielectric separation method. Various methods have been proposed for ultimate body separation, but so far the main methods have all involved an inefficient and expensive process for forming a thick polycrystalline semiconductor of 11,400 to 500 μm.
) A delicate processing process that polishes away 300 to 400 μm and finishes with a high precision of 1 to 2 μm required for device design. (1v) Since the monocrystal and polycrystal have a bimetallic pi-material structure, there are factors that hinder its widespread use, such as frequent production problems such as thermal stress, wafer warpage, and crystal defects. I'm here.

The normal PN separation method does not have the drawbacks of the dielectric separation method and has extremely high production efficiency for integrated circuits with a withstand voltage of about 80 V or less, but it cannot be used at high withstand voltages of 8 OV or more.

[Problems partially addressed by the invention]

When attempting to obtain high breakdown voltage using the PN separation method, wafer curling occurs when forming a thick epitaxial layer, and it is difficult to make a cylindrical shape to create deep islands with a large distance from the surface. It is necessary to solve problems such as the widening of the area. Furthermore, in the case of integration, it is common to combine a high-voltage semiconductor element with a low-voltage semiconductor element that controls it, but the problem with low-voltage semiconductor elements on the same substrate is that the vertical section of the element is over-designed. be.

Therefore, one object of the present invention is to provide a manufacturing method that can increase the thickness of the epitaxial layer without warping the semiconductor wafer or excessively widening the cross-sectional area of the isolation island. Another objective is to provide a manufacturing method that allows high-voltage semiconductor devices and low-voltage semiconductor devices to be produced on the same wafer in the same manufacturing process, and to keep the vertical cross-sectional area of the low-voltage semiconductor devices within the required area. .

[Problem (Means to solve)]

In the manufacturing method of the present invention, a first conductivity type diffusion layer I is formed on the main surface of a first conductivity type semiconductor substrate at a portion planned as the periphery of an island, and a second conductivity type epitaxial layer I is formed on the main surface. A first step of forming.

a second step of forming a first conductivity type epitaxial layer II on the main surface of the epitaxial layer I directly above the diffusion layer (1), and then further forming a second conductivity type epitaxial layer II; By repeating the process multiple times and finally diffusing the first conductivity type diffusion layer N from the epitaxial layer N, the first conductivity type regions of each process are connected to form a PN isolation island, and a semiconductor element is placed within the island. It was established.

By the above manufacturing method, it is possible to obtain a thick epitaxial layer including a PN separation layer of a required thickness.

Furthermore, as will be explained in detail in the examples, a part of the area of the first conductivity type diffusion layer (2) formed in the first step is expanded,
By treating this part as a semiconductor substrate and applying the above manufacturing method on it, a main island with a deep distance from the surface to the bottom and a secondary island with a distance gth are simultaneously formed, and the former is a power element. By incorporating a high breakdown voltage semiconductor element into the latter and a low breakdown voltage semiconductor element serving as a control element, the following can be achieved.

[Effect]

In the present invention, the epitaxial layer is grown on the semiconductor substrate including the Takaoka edge portion in several batches. The Takaoka edges are connected and formed on the semiconductor substrate as if they were building blocks. Therefore, no matter how thick the epitaxial layer is, it does not affect the large area, so the thickness can be determined only from the breakdown voltage design of the semiconductor element. In addition, as described in the embodiment, deep islands and shallow islands can be formed in the same process, and high breakdown voltage semiconductor elements for power and low breakdown voltage semiconductor elements for control can be incorporated into six islands.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. In order to explain the formation of a PN isolated type high breakdown voltage semiconductor element according to the first embodiment, cross-sectional views are shown in the order of steps in FIG.

In FIG. 1(a), first conductivity type diffusion layers 2a, 2b and a second conductivity type diffusion layer 3 are provided at predetermined portions, that is, the portions planned as Takaoka edges, by the first conductivity type substrate IK selective diffusion method. Indicates the condition. Incidentally, when the diffusion layers 2a and 2b are formed by connecting all the Takaoka edges, they become cross sections of the same diffusion layer. It is also possible that the Takaoka edge is partially open and the diffusion layers 2a and 2b are formed separately. 0 The present invention includes both of the cases described below. In the embodiment, the first conductivity type is P type, the second conductivity type is N type, and the P type portion is shown as a hatch and the N type portion is shown as an outline. The semiconductor substrate 1 has a diameter of 4IO9 and a thickness of 500 mm.
μm.

A P-type silicon wafer with a resistivity of 15Ω was used, and the first
The conductivity type diffusion layers 2a and 2b were formed using boron diffusion technology, and the second conductivity type diffusion layer 3 was formed using antimony diffusion technology. The diffusion layer 3 becomes a buried layer.

FIG. 1(b) shows a state in which a second conductivity type epitaxial layer 4 is formed by epitaxial technology. Since the epitaxial growth is performed at high temperatures, the diffusion layers 2&, 2b, and 3 expand as shown in the figure on the semiconductor substrate 1 side and the epitaxial layer 4, respectively, due to thermal diffusion. Above, FIGS. 1(a) and 1(b) are the first step. In the example, the epitaxial layer 4 was formed by a CVD (chemical paper deposition) method using a combination of monosilane and tetrachlorosilane. The epitaxial layer 4 was N-type doped with phosphorus and had a resistivity of 20Ω. The thickness is 30 μm.

In FIG. 1C, a first conductivity type diffusion layer 5m is formed in a predetermined portion of the epitaxial layer 4 by a selective diffusion method.

5b is provided using boron diffusion technology.

FIG. 1(d) is a cross-sectional view showing that the second conductivity type epitaxial layer 6ik is formed by epitaxial technology. The thermal diffusion phenomenon of impurities explained in Fig. 1(b) occurs, and as shown in the figure, the diffusion layers 5m and 5b
expands. Further, the diffusion layers 2a, 2b and the diffusion layer 3
also expands due to the same diffusion phenomenon, although there is a difference in quantity.

Specifically, the epitaxial layer 6 in the example is of N type doped with phosphorus, has a resistivity of 20Ω, and a thickness of 20 μm. As with the epitaxial layer 4, the manufacturing method is a CVD (chemical paper deposition) method using a combination of monosilane and tetrachlorosilane.

As mentioned above, Figure 1 (cl (d)) shows the second step. In this step, the thickness of the epitaxial layer as a whole, that is, the sum of the thicknesses of the epitaxial layer in each step, is This process is repeated until a predetermined value is reached.Assuming that a predetermined thickness is obtained, the first conductivity type diffusion layers 7a and 7b are formed by selective diffusion technology as shown in FIG. 1(e).
Furthermore, a dielectric film 9 is formed on the main surface. In the example, the diffusion layers 7a and 7b were formed by poron diffusion. Dielectric film 9
is a 5loz film with a thickness of 0.5 to 1.5 μm formed by thermal oxidation. Due to the heat treatment during diffusion and thermal oxidation, all the first conductivity type regions intersect with each other, and the first conductivity type regions form the periphery that limits the island 8. If a semiconductor element is manufactured within the island 8 by a diffusion method, a high voltage semiconductor integrated circuit can be obtained.

In the second embodiment, a part of the separation periphery is shared by a deep island (referred to as the main island) into which a high-voltage power semiconductor element is installed and a shallow island (referred to as machine height) into which a low-voltage control semiconductor element is installed. In this embodiment, a shallow island forming step is superimposed on a deep island forming step. FIG. 2 is a sectional view showing the state of each step in the order of the steps.

In the first step, the difference from the first embodiment is that the first conductivity type diffusion layer 2b is diffused widely. This widely diffused area becomes the bottom of the machine height after the entire process is completed.

In FIG. 2(0), the first conductivity type diffusion layers 5b and 5c are formed on the diffusion layer 2b at the same time as the diffusion layer 5a so that they are formed at a high height. In this case, the diffusion layer 5b is formed on the main island and the A second conductivity type diffusion layer 3', which forms a common periphery at the height, is also formed at the same time, and this diffusion layer 3' becomes a buried layer at the machine height. Second
Figures (C) and (d) are cross-sectional views showing the second step, in which the second conductivity type epitaxial layer 6 is formed on the main surface. Figure 2 (e
) is the final step of island formation, and the first conductivity type diffusion layer 7a.

7b and 7c are formed, and a dielectric film 9 is formed on the surface.

In this step, all the first conductivity type regions are connected, and the deep islands 10. A shallow island 11 for a low breakdown voltage element is formed.

A portion of a deep island 10, which is part of an integrated circuit formed in accordance with the present invention, is now shown in FIG. As shown in FIG. 2(e), the semiconductor element in this part is assembled into the second conductivity type diffusion layer 1.
2 is formed by a selective diffusion technique, then a first conductivity type diffusion layer 13 is formed, and a second conductivity type diffusion layer 14 with a higher concentration is formed.
m and 14b, where the diffusion layer 14a is formed in the diffusion layer 13, and the diffusion layer 14b is formed in the diffusion layer 12, respectively. When completed, the diffusion layer 14a is the emitter, the diffusion layer 13 is the base, and the diffusion layers 14b and 1
2 is a high concentration layer drawn out from the collector. In Figure 3,
A state in which a diffusion layer 17 is formed in contact with the diffusion layer 12 is shown, but this is provided to reduce the collector series resistance, and is provided at the same time as the buried layer 3' of the shallow island 11 is formed. .

Furthermore, holes are provided at predetermined positions in the dielectric material [9, and metal wirings are formed in ohmic contact with predetermined diffusion layers. it is,
It is a two-layer wiring, and the first-layer wiring 15 is used not only for the normal inter-element connection function, but also for fields such as a field plate for increasing voltage resistance, and an electric field electrode constituting a surface channel stopper. The two-layer wiring 16 is particularly used for drawing out overlapping electric field electrodes, and when completed, the wiring 16a will be the emitter electrode, the wiring 16b will be the paste electrode wiring, and the wiring 16c will be the collector electrode wiring. As is clear from Figure 3, the separation width is the same as that of the diffusion layers 7a and 7b.
It is good if the spread is small and narrow. One-dot chain line 18 in Figure 3
The figure shown in the figure shows the shape of the island in the case of the dielectric separation method.

It can be seen that the size increases by the lateral inward expansion of the diffusion layers 7a and 7b and the extension of the depletion layer of the isolated PN junction.

The diffusion layers 3 and 3' shown in FIG. 2 formed as high-concentration collector buried layers in this process will be explained. Main island 1 with high pressure resistance
Since the dielectric isolation breakdown voltage of 0 is required to be a high breakdown voltage, the diffusion layer 3 is separated from the diffusion layer 2a or 2b by an appropriate distance in consideration of the extension of the depletion layer of the isolated PN junction and the alignment margin. There is a need. In the example, by designing a distance of 50 ttm on the mask, an insulation breakdown voltage of 400 V or more could be obtained. On the other hand, the machine height 11 with low withstand voltage is the diffusion layer 5b or the diffusion layer 5.
The dielectric strength may be lowered by contacting with C. Diffusion layer 3
By bringing 2' into contact with each other, it is possible to improve the integration density of the low voltage device portion.

〔Effect of the invention〕

Specific examples compared with the dielectric separation method of the present invention are shown in Table 1.

Table 1 This example has a breakdown voltage of 300V, a number of elements of approximately 300 (of which approximately 50 are high voltage elements), and a pellet size of 10 x 3.
It can be seen that this is the case of an integrated circuit with a size of Owm (the size in the case of the present invention), and is excellent in terms of total cost ratio. The case of the normal PN separation method is also an example. As mentioned above, in the present invention, the dielectric separation method requires a complicated and highly accurate process, and also has a structure in bimetallic pimateria of single crystals and polycrystals. There are no production problems due to thermal stress or wafer warping. The process is an extension of the conventional diffusion technology and epitaxial technology and has high production efficiency. In the normal PN separation method, the islands are formed in a thick epitaxial layer, so the cross section of the islands is wide.

In contrast, in the present invention, the Takaoka edge is formed by repeating stepwise formation of the epitaxial layer and formation of the diffusion layer that will become the Takaoka edge, and connecting the diffusion layers in the vertical direction. The position of is limited from the first step. Therefore, the cross-sectional area of the island can be reduced to the limit required by the characteristics, so that the degree of integration can be increased. In addition, if the epitaxial process is divided into several steps, the time during which the epitaxial layer is held at a high temperature will be shortened and the time required for each process to be kept at high temperatures will be shortened, and furthermore, if a control semiconductor element is incorporated at the same time, the entire depth of the epitaxial layer will be reduced. As shown in the second embodiment, by forming an island from the middle of forming a deep island, for example, the thickness of the collector region can be reduced and high performance characteristics can be achieved. can be obtained.

[Brief explanation of drawings]

The drawings relate to an embodiment of the present invention; FIGS. 1 and 2 are cross-sectional views showing the process of forming an island, and FIG. 3 is a view showing an assembled high-voltage semiconductor element. l...first conductivity type semiconductor substrate, 2 a , 2 b , 5 a , 5 b , 5
C---First conductivity type diffusion layer 11 3.3'... Second conductivity type diffusion layer, 4.6... Second conductivity type epitaxial layer, 7a, 7b
, 7c...first conductivity type diffusion layer, 8...(PN separation)
Island, 9...Dielectric film, lO... Main island (deep island), 11... Machine height (shallow island).

Claims (4)

[Claims] (1) A first conductivity type diffusion layer on the main surface of the first conductivity type semiconductor substrate.
A first step of forming a second conductivity type epitaxial layer I on the main surface of the island, and forming the diffusion layer I on the main surface of the epitaxial layer I.
a second step of further forming a second conductivity type epitaxial layer II after forming a first conductivity type diffusion layer II directly above the first conductivity type diffusion layer II;
The second step is repeated multiple times, and finally the first conductivity type diffusion layer N is diffused from the epitaxial layer N, thereby connecting the first conductivity type regions of each step to form a PN isolation island, and forming a PN isolation island within the island. A method for manufacturing a semiconductor integrated circuit, characterized in that a semiconductor element is provided. (2) In the first step of item 1 above, when forming the first conductivity type diffusion layer I, a second conductivity type diffusion layer is formed surrounded by the diffusion layer I, and the diffusion layer is divided into PN parts. A method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the buried layer is formed on a remote island. (3) In a method for manufacturing a semiconductor integrated circuit having a main PN isolation island and a secondary PN isolation island adjacent to the island and sharing a part of its periphery, and in which semiconductor elements are provided on both islands, A first conductivity type diffusion layer I is formed on the main surface of the first conductivity type semiconductor substrate at a portion planned as the periphery of the main island and the bottom surface of the subsidiary island, and a second conductivity type epitaxial layer I is formed on the main surface. After forming the first conductivity type diffusion layer II on the main surface of the epitaxial layer I at planned locations around the periphery of the main island and the periphery of the secondary island, a second conductivity type diffusion layer II is formed. The second step of forming a type epitaxial layer II and the second step are repeated multiple times, and finally the first conductivity type region in each step is diffused from the epitaxial layer N by diffusing the first conductivity type diffusion layer N. 1. A method of manufacturing a semiconductor integrated circuit, characterized in that a plurality of PN isolation islands are connected to each other in a master-slave relationship, and a semiconductor element is provided within the islands. (4) In the first step of item 3 above, when forming the first conductivity type diffusion layer I, a second conductivity type diffusion layer is formed surrounded by the planned peripheral area of the main island, and a second conductivity type diffusion layer I is formed. When forming the first conductivity type diffusion layer II in the process, a second conductivity type diffusion layer is formed surrounded by the diffusion layer II of the slave island, and the second conductivity type diffusion layer is connected to the master and slave PN isolation islands. 4. The method of manufacturing a semiconductor integrated circuit according to claim 3, wherein each of the buried layers is a buried layer.