JPS5890760A - Lamination type semiconductor device - Google Patents

Abstract

PURPOSE:To fit the titled device for multi functions and large capacity, by forming it into vertical type. CONSTITUTION:P, As or B is previously introduced into the lower electrode 8. The insulation film for an element isolation layer 2 is formed thereon, the part except for the layer 2 is removed, and an N<+> layer, an N<-> layer, a P layer and an N<+> layer which serve as active layers 3-6 are formed on this removed part. Next, a metallic layer is formed on layers 3-6, accordingly it is decided as the upper electrode layer 1. When forming other active layers than the layers 3-6 which necessitate a high temperature treatment thereon, a high melting point metallic silicide is used. In the device of this constitution, the device dimension is determined by the area of the active region, and, compared with one wherein input-output parts are arranged in the transversal direction of the active layers, the area of the input part is not influenced. Therefore, a number of elements can be accommodated into a limited area.

Description

[Detailed Description of the Invention] It was a so-called horizontal device in which the current is applied very close to the surface and the force is applied from the surface again.

In this method, to configure one device,
They require a large area, and it is becoming difficult to incorporate more multi-functional and large-capacity devices into the limited chip area.

The present invention has been made to eliminate the drawbacks of such conventional methods, and provides a stacked semiconductor device that can satisfy the demands for multi-function and large capacity by making the device vertical (three-dimensional). The details of the present invention are as follows. #E will be explained with reference to the drawings.

The figure shows an example of an embarrassing configuration. A high melting point metal silicide into which impurities have been introduced in advance is formed on a support substrate, and this is used as a wiring layer. An active layer such as 81 is formed on this. The heat treatment temperature at this time or the formation method (CVD
This layer is made into an amorphous layer, a polycrystalline layer, or a single crystal layer by a method (e.g., a polycrystalline method or a radar annealing method), and the layer properties vIt can be selected depending on the purpose. As an example of an active layer device, a bipolar transistor will be described with reference to the drawings.

The lower electrode (8) is coated with phosphorus or hin (np) in advance.
n) for transistors) or boron (for pnp transistors). On top of this is an element isolation layer (2)
An insulating film (e.g. 8102 layer) is formed for the purpose, the parts other than the element isolation layer (2) are removed, and the removed parts are covered with an n-soil layer, an n-single layer, and a p-layer, which will become the active layers (3) to (6). Form a layer and a soil layer. At this time, the active)Wit r/iM resistance layer is formed, but due to the heat and treatment during formation, the lower part
The impurities therein are autodoped into the active layer to form a highly concentrated layer, and ohmic contact between the oily layer and the lower electrode 1-(1) can be easily formed. Impurities can be introduced into the P layer (5), which will become the base region, and the N-soil layer (6), which will become the emitter region, by a conventional method such as a diffusion method or an ion injection method. Active layer (3
) to (6), a single layer is formed on top of the upper electrode layer (υ
shall be. This upper electrode layer (1) is used when an active layer other than the above-mentioned active layers (3) to (6) that requires high-temperature treatment is formed on top of the upper electrode layer (1) in order to fabricate a stacked semiconductor device. A high melting point metal silicide may be used, or a low melting point metal such as aluminum may be used if it is not necessary, such as when used simply as a surface electrode.

Human output to the stacked semiconductor device is performed through the upper and lower electrode layers (1) and (8) sandwiching the active layer, but either one may be the input end or the output side. In the figure, the upper electrode layer (8) is manually operated, and the lower electrode layer (1) is
is an example of the output. In a device with this configuration, the device dimension is determined by the area of the active region, and compared to the conventional method in which the human output section is arranged in four horizontal directions of the active layer, the area of the human output section does not affect the area, so the area is limited. It is therefore possible to accommodate more elements than the conventional method. Therefore, a stacked semiconductor device with more functions and capacities than the conventional method can be realized.

Further, by stacking active regions with increased functionality and increased capacity in this way, further increased functionality and increased capacity can be achieved.

[Brief explanation of drawings]

The figure is a sectional view showing one embodiment of the present invention. (1) t/″i lower electrode layer, (2) element isolation layer, (
3) is n soil layer, (4) is n single layer, (5) IiP layer, (
6) a silica layer, (7) an insulating layer, and (8) an upper electrode layer.

Claims (1)

[Claims] A first dovetail melting point metal silicide layer into which impurities have been introduced in advance, an active layer formed on this first high melting point metal silicide layer, and a %2 which is formed on this active layer and into which impurities have been introduced in advance. A high melting point metal silicide layer of 1. 1. A stacked semiconductor device comprising a plurality of stacked active regions each made of a high melting point metal silicide layer having a VG2.