JPS61252644A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To shorten the width of an element isolating region, by coating a part other than the bottom part of a recess at a part, where the element isolating region is formed, with an insulating film, and forming a semiconductor region having high impurity concentration by diffusion from a single crystal material or a polycrystalline material, which is filled in the recess and includes impurities. CONSTITUTION:On a silicon substrate 101, a silicon oxide film 102 is formed. A silicon nitride film 103 and a silicon oxide film 104 are further formed thereon. Photoresist at a position, where an element isolating region is to be formed, is removed, and the oxide film 102 and 104 and the nitride film 103 are removed. Then with the oxide film 104 as a mask, the substrate 101 is vertically removed, and a recess 109 is formed. Thereafter, an oxide film 105 is formed at the bottom surface and the side surface of the recess 109. Then, a silicon nitride film 106 is formed. The nitride film 106 only on the bottom part of the recess 109 and on the surface part of the silicon substrate 101 is removed. The nitride film 106 on the side surface part of the recess 109 and the oxide film 105 are made to remain. Thereafter, the nitride film 103 is removed by anisotropic etching having a high selecting ratio. After a single-crystal or polycrystalline silicon region 107 is selectively formed, a diffused region 108 is formed. Thus the width of the element isolating region can be made short, and the depth of the element isolating region can be made sufficiently large.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having an element isolation region for electrically isolating each element.

[Prior Art] As semiconductor devices become more highly integrated, it has become an important issue to reduce the width of element isolation regions that electrically isolate each element as small as possible. To address these issues, conventional element isolation methods include pn reverse junction isolation and LOCO.
S method etc.

However, in the pn reverse junction isolation method, since the element isolation region is formed by impurity diffusion, the diffusion progresses laterally, increasing the isolation width, making it unsuitable for high integration. .

In addition, since the LOCOS method selectively forms a thick oxide film, if an attempt is made to reduce the isolation width, a sufficient depth cannot be obtained, which causes the problem of insufficient isolation, especially in the case of bipolar devices. had further LOC
In the OS method, unnecessary parts called bird's beaks are formed at both ends of a thick oxide film, so there is a limit to the high integration of devices.

[Problems to be Solved by the Invention] As described above, in the conventional semiconductor device manufacturing method, the width of the element isolation region can be made small and the element isolation region can have a sufficient depth. could not provide a manufacturing method.

[Means for solving the problem] The above problem is solved by the method of manufacturing a semiconductor device in which each element formed in a semiconductor layer of one conductivity type is electrically isolated by an element isolation region. A first step of forming a recess in a portion where an element isolation region is to be formed, and a second step of covering the portion except the bottom of the recess with an insulating film.

a third step of filling the recess with a single-crystalline or polycrystalline material containing impurities of one conductivity type; The problem is solved by the method of manufacturing a semiconductor device of the present invention, characterized in that the element isolation region is formed by: a fourth step of forming a one-conductivity type semiconductor region with a high impurity concentration.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of an element isolation region of a semiconductor device manufactured by an embodiment of the semiconductor device manufacturing method according to the present invention.

A silicon oxide film 105 is formed on the surface of the silicon substrate 101 and the element isolation region 2, and a silicon nitride film 10B and a single crystal or polycrystalline silicon region 107 are formed on the silicon oxide film 105 in the element isolation region 2. A diffusion region 108 is formed under the single crystal or polycrystalline silicon region 107.

Next, the first method for manufacturing a semiconductor device according to the present invention will be described.
A detailed explanation will be given using schematic cross-sectional views of each manufacturing process of the semiconductor device shown in the figures.

First, as shown in FIG. 2(A), a silicon substrate 101
A silicon oxide film 102 with a thickness of about 500 ml is formed thereon by a thermal oxidation method, etc., a silicon nitride film 103 with a thickness of about 2500 ml is formed on top of it by a CVD method, etc., and a silicon nitride film 103 with a thickness of about 1.7 JLm is formed thereon. Oxide films 104 are respectively formed.

Next, as shown in FIG. 2(B), the photoresist is removed by photolithography at the location where the element isolation region is to be formed, and the oxide films 102, 104 and nitride film 103 are removed using the photoresist as a mask. Remove by directional dry etching method. However, oxide film 10
A mixed gas of CF4+H2 is used for etching 2 and 104, and CF4+O2 is used for etching the nitride film 103.
A mixed gas was used.

Next, as shown in FIG. 2(C), using the oxide film 104 as a mask, anisotropic dry etching (for example, reactive ion etching using CCl4 gas or CI2 gas) is performed to remove the substrate +01. Remove vertically to the desired depth (e.g. 5 gm) to remove the four sections 108.
form. The depth of the four portions 109 formed by this etching removal approximately determines the depth of the element isolation region.

Next, as shown in FIG. 2(D), thermal oxidation is performed to form an oxide film 105 with a thickness of about 2,500 on the bottom and side surfaces of the recess 109.

Next, as shown in FIG. 2(E), a silicon nitride film 10B with a thickness of 1,500 nm is formed by CVD or the like, and then, as shown in FIG. 2(F), anisotropic dry etching is performed. Only the nitride film 108 on the bottom of the recess 109 and the surface of the silicon substrate 101 is removed using CF44 H2 gas or active ion etching, and the nitride film 10B and oxide on the side surfaces of the recess 109 are removed. The film 105 is left behind. Thereafter, the nitride film 103 on the silicon substrate 101 is removed by anisotropic etching with a high selectivity (for example, using CH2F2 gas or active ion etching).

Next, as shown in Figure 2 ((i), SiC+4-HC
I-H2 system, Sin 4-HCI-H2 system, or Si8
2. A single crystal or polycrystalline silicon region (herein referred to as a polycrystalline silicon region) 107 is selectively produced using a gas such as 2G+2-HCl-H2 system. At this time, on the oxide film 102 on the surface of the silicon substrate 101, due to the nature of the oxide film, the equilibrium state between the etching by HCI and the deposition of Si by the Si source is closer to the etching side.
does not accumulate. Finally, a diffusion region 108 is formed. There are three methods for forming this. The first method is to contain PH3 during selective deposition of the polycrystalline silicon region 107 to form polycrystalline silicon containing P, and then diffuse P to form the diffusion region. 108 is formed. The second method is to re-oxidize the oxide film 102 to about 3000 layers, then pattern the oxide film on the polycrystalline silicon, and use POCl3 etc. to form the diffusion region 108 by thermal diffusion through the polycrystalline silicon region 107. Form. The third method is the above poc+3
The ion implantation method is used without using a gas such as, and then the diffusion region 108 is formed by thermal diffusion.

According to the semiconductor device using the semiconductor device manufacturing method of the present invention described above, lateral diffusion can be suppressed by the silicon nitride film lOB and the silicon oxide film 105 provided on the side surfaces of the recess 109. The depth can be set arbitrarily by controlling dry etching which has anisotropy.

Further, by applying a voltage to the diffusion region 1087 using the single crystal or polycrystalline silicon region 107 in FIG. 1 as a wiring, a potential wall can be locally created in the vertical direction of the substrate 101. If the thickness of the nitride film 10B is 2,500 Å or more and the thickness of the nitride film 10B is 1,500 Å or more, a potential wall can be formed without significantly affecting the potential of the lateral element region. This potential wall is particularly important as shown in FIG.
It is very effective when used for electrical isolation of the sensor cell disclosed in Japanese Patent No. 127E15. Hereinafter, a sensor cell using the method of manufacturing a semiconductor device of the present invention will be explained using FIG.

In FIG. 3, an n- region 3 with a low impurity concentration is formed on an n+ silicon substrate l, and a p-region 4 is formed on the n- region 3 by doping p-type impurities. An n+ region 5 is formed by an impurity diffusion technique, an ion implantation technique, or the like. p region 4 and n
The middle regions 5 are the base and emitter of a bipolar transistor, respectively. Note that 2 is an element isolation region in the present invention.

An oxide film 6 is formed on the n- region 3 in which each region is formed in this manner, and a capacitor electrode 7 having a predetermined area is formed on the oxide M6.

Capacitor electrode 7 faces p-region 4 with oxide film 8 in between, and applies a pulse voltage to capacitor electrode 7 to control the potential of p-region 4 in a floating state.

In addition, the emitter electrode 8 connected to the n-middle region 5, the wiring 8 for reading out signals from the emitter electrode 8 to the outside, the n-1 region 11 with high impurity concentration on the back surface of the substrate l, and the collector of the bipolar transistor are connected to a potential. electrode 12 for giving
are formed respectively.

Light 13 enters the p-region 4, which is the base of the bipolar transistor, and a charge corresponding to the amount of light is accumulated in the p-region 4. The base potential changes due to the 0M multiplied charges, and the emitter changes the potential change into a floating state. By reading from the electrode 8, an electrical signal corresponding to the amount of incident light can be obtained.

In the above sensor cell, when a positive voltage is applied to the n-type silicon substrate 1 and the element isolation region 2, a high potential wall is formed in the direction A in FIG. This potential wall prevents holes generated by incident light from flowing into the p-regions of adjacent cells, achieving complete electrical isolation between cells. It has been confirmed that complete separation between cells is achieved even when the thickness of the n layer 3 is 4 JLrn, and deep separation that cannot be achieved with the prior art LOCO9 method is possible.

In addition, this separation method does not require special planarization techniques such as etch-back, and the manufacturing process is simple. The buried single-crystalline or polycrystalline silicon region can be used as a wiring area, so when making wiring contacts. , no special contact forming process is required.

[Effects of the Invention] As explained in detail above, according to the method of manufacturing a semiconductor device according to the present invention, the width of the element isolation region can be made small and the depth of the element isolation region can be made sufficient. It is possible to provide a method of manufacturing a semiconductor device that is suitable for integration, has a simple manufacturing process, and provides more complete electrical isolation because a potential wall is provided in the element isolation region.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of an element isolation region of a semiconductor device manufactured by an embodiment of the method for manufacturing a semiconductor device according to the present invention. FIG. 3 is a manufacturing process diagram showing one embodiment of a method for manufacturing a semiconductor device, and is a schematic cross-sectional view of a sensor cell manufactured by applying the method for manufacturing a semiconductor device of the present invention. 2-...Element isolation region 101...Silicon substrate 102, 105...Silicon oxide film 108...Silicon nitride film 107...Single crystal or polycrystalline silicon region 10B
...Diffusion area agent Patent attorney Jo Taira Yamashita Figure 1 Figure 2

Claims (1)

[Claims] (1) In a method for manufacturing a semiconductor device in which each element formed in a semiconductor layer of one conductivity type is electrically isolated by an element isolation region, a recess is formed in a portion of the semiconductor layer where the element isolation region is to be formed. a first step of forming the recess, a second step of covering the recess except for the bottom with an insulating film, and a third step of filling the recess with a single crystal or polycrystalline material containing the impurity of one conductivity type; a fourth step of forming a one conductivity type semiconductor region with an impurity concentration higher than that of the semiconductor layer directly under the single crystal or polycrystalline material by impurity diffusion from the single crystal or polycrystalline material; and forming the element isolation region by: A method for manufacturing a semiconductor device, characterized in that: