JPH02105572A - Solid state image pickup device - Google Patents

Solid state image pickup device

Info

Publication number
JPH02105572A
JPH02105572A JP63258425A JP25842588A JPH02105572A JP H02105572 A JPH02105572 A JP H02105572A JP 63258425 A JP63258425 A JP 63258425A JP 25842588 A JP25842588 A JP 25842588A JP H02105572 A JPH02105572 A JP H02105572A
Authority
JP
Japan
Prior art keywords
region
type
channel region
semiconductor substrate
charge transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63258425A
Other languages
Japanese (ja)
Inventor
Koichi Fujii
浩一 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63258425A priority Critical patent/JPH02105572A/en
Publication of JPH02105572A publication Critical patent/JPH02105572A/en
Pending legal-status Critical Current

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Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Picture Signal Circuits (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To prevent charge created in a region other than a photodetecting part from being transferred to a charge transfer part and suppress smear even if an intense light or a light refracted by an upper layer film on the photodetecting part is applied by a method wherein an insulating wall is provided between a photoelectric transducer region and a channel region. CONSTITUTION:In a solid state image pickup device, the photoelectric transducer region (photodiode region) 105 of a photodetecting part and the N-type channel region 106 of a charge transfer part are provided on a semiconductor substrate 101 with a reading part region between them. An insulating wall 103 having an aperture 113 is buried in the reading part region between the photodiode region 105 and the N-type channel region 106. The N-type channel region 106, therefore, is surrounded by an insulating silicon oxide film except the aperture 113. With this constitution, charge created in a P-type region 102 is almost drained into the N-type semiconductor substrate 101 and smear can be avoided.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は固体撮像装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a solid-state imaging device.

〔従来の技術〕[Conventional technology]

従来の固体撮像装置は、第3図に示す縦型オーバフロー
ドレイン構造の固体撮像装置のように、−導電形の半導
体基板(N型半導体基板1)の−主面に逆導電形のウェ
ル(P壁領域2)が形成され、受光部のホトダイオード
領域5と電荷転送部のN型チャネル領域6が同じ上記逆
導電形のウェル内に、二次元的に配列されており、受光
部の周囲は読み出し部領域7を除いてチャンネルストッ
パ8が形成されていた。さらに酸化、CVD等をくり返
し薄い酸化シリコン膜9、ゲート電極10、M間M、l
l、遮光アルミニウム[12を形成し、固体撮像素子を
形成していた。
A conventional solid-state imaging device, like the solid-state imaging device with a vertical overflow drain structure shown in FIG. A wall region 2) is formed, and the photodiode region 5 of the light receiving section and the N-type channel region 6 of the charge transfer section are two-dimensionally arranged in the same well of opposite conductivity type, and the area around the light receiving section is a readout area. A channel stopper 8 was formed except for the area 7. Furthermore, oxidation, CVD, etc. are repeated to form a thin silicon oxide film 9, a gate electrode 10, and a space between M and l.
1, light-shielding aluminum [12] was formed to form a solid-state image sensor.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の固体撮像装置では強い光が入射したり、
受光部の上層の膜で屈折した光が入射した場合、受光部
位外の領域で電荷が発生し、その電荷が電荷転送部へ移
動した時、スミアの原因になるなどの欠点がある。
In the conventional solid-state imaging device described above, strong light may be incident,
When light that is refracted by the film on the upper layer of the light-receiving section is incident, charges are generated in a region outside the light-receiving section, and when the charges move to the charge transfer section, there are drawbacks such as causing smear.

本発明の目的は、受光部の近辺で発生する電荷によるス
ミアのない固体撮像装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device that is free from smear caused by charges generated near a light receiving section.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の固体撮像装置は、受光部の光電変換素子領域と
、電荷転送部のチャネル領域とが、間に読み出し部領域
を挟んで半導体基板に設けられてなる固体撮像装置にお
いて、前記光電変換素子領域と前記チャネル領域との間
に前記読み出し部領域に開孔を有する絶縁性壁が埋め込
まれているというものである。
A solid-state imaging device of the present invention is a solid-state imaging device in which a photoelectric conversion element region of a light receiving section and a channel region of a charge transfer section are provided on a semiconductor substrate with a readout section region sandwiched therebetween. An insulating wall having an opening in the reading region is embedded between the region and the channel region.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)及び(b)は本発明の一実施例の縦型オー
バフロードレイン構造を有するCCD固体撮像装置を示
すそれぞれ半導体チップの断面図及び半導体基板の平面
図である。
FIGS. 1A and 1B are a cross-sectional view of a semiconductor chip and a plan view of a semiconductor substrate, respectively, showing a CCD solid-state imaging device having a vertical overflow drain structure according to an embodiment of the present invention.

この実施例は、受光部の光電変換素子領域(ホトダイオ
ード領域105)と、電荷転送部のN型チャネル領域1
06とが、間に読み出し部領域を挟んで半導体基板(N
型半導体°基板101にウェル(P壁領域102)を設
けたもの)に設けられてなる固体撮像装置において、ホ
トダイオード領域105とN型チャネル領域106との
間に前述の読み出し部領域に開孔113を有する絶縁性
壁が103が埋め込まれているというものである。
In this embodiment, a photoelectric conversion element region (photodiode region 105) of a light receiving section and an N-type channel region 1 of a charge transfer section are used.
06 and the semiconductor substrate (N
In a solid-state imaging device provided in a type semiconductor substrate 101 with a well (P wall region 102), an opening 113 is formed in the above-mentioned readout region between the photodiode region 105 and the N-type channel region 106. 103 is embedded in the insulating wall having the following characteristics.

次に、この実施例の製造方法について説明する。Next, the manufacturing method of this example will be explained.

シリコンからなるN型半導体基板101にP壁領域10
2を形成する。さらに、将来電荷転送領域となる領域に
溝を形成する。さらに、異方性エツチングによるホトリ
ソグラフィー技術により、将来読み出し部となる領域を
残して溝の表面に酸化シリコン膜を設ける。さらにP型
シリコン層104を成長し清を完全に埋める。
A P wall region 10 is formed on an N type semiconductor substrate 101 made of silicon.
form 2. Furthermore, a groove is formed in a region that will become a charge transfer region in the future. Furthermore, a silicon oxide film is formed on the surface of the groove, leaving a region that will become a readout section in the future, using a photolithography technique using anisotropic etching. Furthermore, a P-type silicon layer 104 is grown to completely fill the void.

そしてP壁領域102には受光部のホトダイオード領域
105としてN型拡散層を、P型シリコン、Ill 0
4には電荷転送部のN型チャネル領域106をそれぞれ
形成する。そして受光部の周囲の領域には読み出し部領
域以外のところにチャンネルストッパ108となるP型
拡散層を形成する。
In the P-wall region 102, an N-type diffusion layer is formed as a photodiode region 105 of the light-receiving section, and a P-type silicon, Ill 0
4, an N-type channel region 106 of a charge transfer portion is formed, respectively. Then, a P-type diffusion layer serving as a channel stopper 108 is formed in a region around the light receiving section other than the readout region.

さらには酸化、CVD等をくり返し薄い酸化シリコン[
109、ゲート電極110. J1間膜111、遮光ア
ルミニウム膜112を形成する。
Furthermore, thin silicon oxide [
109, gate electrode 110. A J1 interlayer film 111 and a light-shielding aluminum film 112 are formed.

N型チャネル領域106は、開孔113を除き、絶縁性
の酸化シリコン膜で囲まれているので、P壁領域102
で発生した電荷は殆んど全てN型半導体基板101に排
出され、スミアは防止される。
Since the N-type channel region 106 is surrounded by an insulating silicon oxide film except for the opening 113, the P-wall region 102
Almost all of the generated charges are discharged to the N-type semiconductor substrate 101, and smear is prevented.

第2図は第2の実施例を示す半導体チップの断面図であ
る。
FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment.

第1の実施例と異なる点は溝の底に酸化シリコン膜がな
いこと、絶縁性壁203bのチャネルストッパ206部
にも開孔213bもしくはスリットが設けられているこ
とである。
The difference from the first embodiment is that there is no silicon oxide film at the bottom of the groove, and that an opening 213b or slit is also provided in the channel stopper 206 portion of the insulating wall 203b.

スミアの発生はホトダイオード領域205の近辺で発生
した電荷であるから、N型チャネル領域206の下方に
絶縁膜を埋め込む必要はあまりない。チャネルストッパ
はP+型なので、そこで発生した電荷も殆んどスミアの
原因とはならない。
Since the smear is caused by charges generated in the vicinity of the photodiode region 205, there is no need to bury an insulating film under the N-type channel region 206. Since the channel stopper is of P+ type, the charge generated there hardly causes smear.

次に、この実施例の製造方法について説明する。Next, the manufacturing method of this example will be explained.

第1の実施例と同様にN型半導体基板201にP壁領域
202を形成する。そして将来電荷転送領域となる領域
に清を形成しN型半導体基板201の主表面及び清の表
面(側面及び底面)に酸化シリコン膜又は窒化シリコン
膜を形成する。
A P wall region 202 is formed in an N type semiconductor substrate 201 as in the first embodiment. Then, a layer is formed in a region that will become a charge transfer region in the future, and a silicon oxide film or a silicon nitride film is formed on the main surface of the N-type semiconductor substrate 201 and the surface (side surface and bottom surface) of the layer.

そして異方性エツチングし図のように絶縁膜を形成する
。さらにエピタキシャル成長によりP型シリコン膜20
4を成長し溝を完全に埋める。そしてP壁領域102に
は受光部となるホトダイオード領域205を、P型シリ
コン膜204には電荷転送部となりN型チャネル領域2
06をそれぞれ形成する。また受光部の周囲の領域には
読み出し部領域以外のことろにチャネルストッパ208
となるP型拡FII1.fr!Iを形成する。さらに酸
化、CVD等をくり返し薄い酸化膜209.ゲート電極
210層間膜211.アルミ212を形成する。
Then, an insulating film is formed by anisotropic etching as shown in the figure. Furthermore, by epitaxial growth, a P-type silicon film 20 is formed.
Grow 4 and completely fill the gap. The P wall region 102 has a photodiode region 205 which becomes a light receiving part, and the P type silicon film 204 has an N type channel region 2 which becomes a charge transfer part.
06 respectively. In addition, there are channel stoppers 208 in the area around the light receiving area other than the readout area.
P-type expanded FII1. fr! Form I. Furthermore, oxidation, CVD, etc. are repeated to form a thin oxide film 209. Gate electrode 210 interlayer film 211. Aluminum 212 is formed.

溝底部に酸化シリコン膜がなのでP型シリコン膜は単結
晶となり易く、電荷転送部の性能は、絶縁性壁を設ける
ことにより悪くなる恐れはない。
Since there is a silicon oxide film at the bottom of the groove, the P-type silicon film tends to be a single crystal, and the performance of the charge transfer section is not likely to be deteriorated by providing an insulating wall.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は受光部と読み出し部と電荷
転送部が二次元的に配列された固体撮像装置において、
光電変換素子領域とチャネル領域との間の領域に絶縁性
壁を設けであるので、強い光や受光部上の上層の膜で屈
折した光が入射した場合、受光部以外の領域で発生した
電荷が電荷転送部へ移動するのを防止でき、スミアを抑
制できる効果がある コン層、5,105,205・・・ホトダイオード領域
、6,106,206・・・N型チャネル領域、7・・
・読み出し部領域、8.108,208・・・チャンネ
ルストッパ、9,209.309・・・薄い酸化シリコ
ン膜、10,110,210・・・ゲート電極、1.1
,111.211・・・層間膜、12,112゜212
・・遮光アルミニウム膜、113,213a、213b
・・・開孔。
As explained above, the present invention provides a solid-state imaging device in which a light receiving section, a reading section, and a charge transfer section are arranged two-dimensionally.
An insulating wall is provided in the region between the photoelectric conversion element region and the channel region, so when strong light or light refracted by the upper layer film on the light receiving section enters, charges generated in areas other than the light receiving section are removed. 5, 105, 205... Photodiode region, 6, 106, 206... N-type channel region, 7...
・Readout region, 8.108,208...Channel stopper, 9,209.309...Thin silicon oxide film, 10,110,210...Gate electrode, 1.1
, 111.211... interlayer film, 12,112°212
...Light-shielding aluminum film, 113, 213a, 213b
...Open hole.

Claims (1)

【特許請求の範囲】[Claims] 受光部の光電変換素子領域と、電荷転送部のチャネル領
域とが、間に読み出し部領域を挟んで半導体基板に設け
られてなる固体撮像装置において、前記光電変換素子領
域と前記チャネル領域との間に前記読み出し部領域に開
孔を有する絶縁性壁が埋め込まれていることを特徴とす
る固体撮像装置。
In a solid-state imaging device in which a photoelectric conversion element region of a light receiving section and a channel region of a charge transfer section are provided on a semiconductor substrate with a readout section region in between, there is a gap between the photoelectric conversion element region and the channel region. A solid-state imaging device characterized in that an insulating wall having an opening is embedded in the readout region.
JP63258425A 1988-10-14 1988-10-14 Solid state image pickup device Pending JPH02105572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63258425A JPH02105572A (en) 1988-10-14 1988-10-14 Solid state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63258425A JPH02105572A (en) 1988-10-14 1988-10-14 Solid state image pickup device

Publications (1)

Publication Number Publication Date
JPH02105572A true JPH02105572A (en) 1990-04-18

Family

ID=17320036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63258425A Pending JPH02105572A (en) 1988-10-14 1988-10-14 Solid state image pickup device

Country Status (1)

Country Link
JP (1) JPH02105572A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07183481A (en) * 1993-12-22 1995-07-21 Nec Corp Solid-state image sensing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07183481A (en) * 1993-12-22 1995-07-21 Nec Corp Solid-state image sensing device

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