JPH07176758A - Insulated gate type field effect semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a good switching characteristic in a high-frequency by providing an I-type non-single crystalline semiconductor layer having an extreme ly less amount of oxygen, carbon and nitrogen on the surface of the insulated substrate and promoting crystallization only of a doped region in this layer. CONSTITUTION:A source region 7 and a drain region 8 are formed by doping an I-type non-single crystal semiconductor layer 2 of less than 5X10<18>cm<-3> of hydrogen, carbon and nitrogen formed on a substrate 1 having an insulated surface together with promoting crystallization of the doped region. A channel formation region is formed on the I-type non-single crystal semiconductor layer 2 to which hydrogen or a halogen element and aforesaid impurities are added and gate electrode 4 is provided through a gate insulating film 3. The source region 7 and the drain region 8 are desirable to be a polycrystalline semiconductor whereto hydrogen or a halogen element is added to the density of one atom % or more. This constitution allows it to obtain a good switching characteristic in a high frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect semiconductor device used in semiconductor integrated circuits, liquid crystal display panels and the like.

[0002]

2. Description of the Related Art In a field effect transistor described in Japanese Patent Laid-Open No. 58-2073, a source region and a drain region are selectively annealed to form a polycrystalline region and a channel forming region is formed into an amorphous region. There is. That is, the field effect transistor shown in the publication is
Part of the amorphous region is selectively annealed to form a polycrystalline region.

[0003]

As described above, the channel forming region in the conventional insulated gate field effect semiconductor device contains oxygen, carbon and nitrogen in an amount of 1 to 3 × 10 ²⁰ cm ^-3. It was composed of a non-single crystal semiconductor layer. When all of oxygen, carbon, and nitrogen are contained in such a high concentration, the insulated gate field effect semiconductor device has “ON” and “OF” when switching.
The "F" characteristic was bad. For example, in an insulated gate field effect semiconductor device using a non-single-crystal semiconductor containing oxygen, carbon, and nitrogen at such high concentrations as described above, good "ON" and "OFF" The frequency characteristic showing the characteristic was about 1 KHz.

Further, in the conventional insulated gate field effect semiconductor device, since the source region and the drain region are selectively annealed, an uncrystallized portion always remains in the non-single crystal semiconductor layer. When an uncrystallized region remains in the insulated gate field effect semiconductor device as described above, a part of the current also flows in this amorphous portion when operating as an insulated gate field effect semiconductor device. Since the amorphous portion has a higher resistance than the crystallized portion,
It is difficult for current to flow, and once it flows in, it accumulates and then slowly flows out. That is, the insulated gate field effect semiconductor device in the conventional example has a long lifetime in which a current flows and has a hysteresis characteristic.

In order to solve the above problems, it is an object of the present invention to provide an insulated gate field effect semiconductor device which has good switching characteristics and can be used at high frequencies.

[0006]

In order to achieve the above object, an insulated gate field effect semiconductor device of the present invention is formed on a substrate (1) having an insulating surface and contains oxygen, carbon or nitrogen. × 10 ¹⁸ cm ^-3 or less of type I non-single-crystal semiconductor layer
(2) and the P type or N type in the I type non-single crystal semiconductor layer (2).
Source region and drain region (7), (8) formed by promoting the crystallization of the region to which the impurity is added, and the source region and drain region (7), (8) between the channel formation region formed in the I-type non-single-crystal semiconductor layer (2) to which hydrogen or a halogen element and the impurity are added, and a gate insulating film (3 And a gate electrode (4) formed via In addition, the pair of impurity regions (7) and (8) composed of the source region and the drain region contain 1 atom% of hydrogen or a halogen element.
It is characterized by being composed of a polycrystalline semiconductor added to the above concentration.

The insulated gate field effect semiconductor device of the present invention comprises a channel forming region for selectively forming an insulated gate field effect semiconductor device on a substrate (1) having an insulating surface,
Non-single crystal semiconductor layer (2) consisting only of source and drain regions (7) and (8), and substrate (1) having an insulating surface
Formed on top of 5 × 10 ¹⁸ c of oxygen, carbon, or nitrogen
m ⁻³ or less channel formation region, and the non-single-crystal semiconductor layer
Source and drain regions (7) and (8) formed by adding P-type or N-type impurities to (2) and promoting crystallization, and a gate insulating film on the channel forming region. Gate electrode formed via (3) (4)
It is characterized by having and.

[0008]

[Operation] The insulated gate field effect semiconductor device of the present invention contains 5 × 10 ¹⁸ c of oxygen, carbon and nitrogen.
m ^-3 or less, that is, I in which the above elements are reduced as much as possible
A P-type or N-type impurity is added to the non-single-crystal semiconductor layer, and a source region and a drain region are formed by promoting crystallization of only the region to which the impurity is added. The feature is that hydrogen, or a halogen element is added. The insulated gate field effect semiconductor device having such a structure is a non-single crystal semiconductor in the conventional example, for example, an I-type non-single crystal in which each of oxygen, carbon and nitrogen is 1 to 3 × 10 ²⁰ cm ^−3. While the semiconductor had such a switching characteristic that it could follow the frequency of 1 KHz, a good switching characteristic was obtained even at the frequency of 1 MHz.

In the insulated gate field effect semiconductor device, oxygen, carbon, and nitrogen in the I-type non-single-crystal semiconductor layer are all extremely reduced to 5 × 10 ¹⁸ cm ⁻³ or less, and the channel formation region is reduced. Since all the non-single-crystal semiconductor layers except the one were formed from the source region and the drain region which promoted crystallization by light irradiation, the switching characteristics at higher frequencies were improved. In particular, since the source region and the drain region are not selectively annealed, crystallization can be promoted in all the I-type non-single-crystal semiconductor layers other than the channel formation region. That is, in the insulated gate field effect semiconductor device according to the present invention, no amorphous portion having high resistance is left in the source region and the drain region. In addition, since the source region and the drain region do not have an amorphous portion in which a current does not easily flow, a current easily flows, and the current does not dangle during switching.
Therefore, the insulated gate field effect semiconductor device of the present invention has a short lifetime in which a current flows and does not exhibit hysteresis characteristics. That is, the insulated gate field effect semiconductor device of the present invention has a small off current and is "ON" or "O".
It was possible to perform "FF" with a high-speed response.

[0010]

Embodiments FIGS. 1A to 1C are vertical sectional views of an insulated gate field effect semiconductor device according to an embodiment of the present invention. In FIG. 1, the substrate (1) is made of quartz glass, for example, and has a thickness of 1.1 m as shown in FIG. 1 (A).
m and the size was 10 cm × 10 cm. This board (1)
Silane (SiH ₄ ) plasma CVD (high frequency 13.5
At 6 MHz and a substrate temperature of 210 ° C., a non-single-crystal semiconductor (2) containing an amorphous structure to which hydrogen was added at a concentration of 1 atomic% or more was formed to a thickness of 0.2 μm. Further, a gate insulating film (3) made of, for example, a silicon nitride film was laminated on the upper surface of the non-single crystal semiconductor (2) by a photo CVD method.
That is, the gate insulating film (3) is composed of disilane (Si ₂ H ₆ ) and ammonia (NH ₃ ), or hydrazine (N ₂ H ₄ ).
Reaction with (low-pressure mercury lamp including wavelength of 2537Å, substrate temperature 25
(0 ℃), Si ₃ N ₄ without using mercury sensitization
It was made to a thickness of 1000Å.

Thereafter, the portion except the region (5) forming the insulated gate field effect semiconductor device was removed by the plasma etching method. The plasma etching reaction is CF
Introducing a reactive gas of ₄ + O ₂ (5%) and applying a frequency of 13.56 MHz to a parallel plate electrode (not shown),
Done at room temperature. On the gate insulating film (3), N ⁺ conductive type microcrystalline or polycrystalline semiconductor was laminated to a thickness of 0.3 μm. An undesired part of the N ⁺ semiconductor film was removed by photoetching using the resist film (6). After that, this resist film (6) and the gate electrode (4) of N ⁺ semiconductor
By using the gate part consisting of and as a mask, the region which becomes the source and the drain is 1 × 10 ²⁰ cm ⁻³ by the ion implantation method.
As shown in FIG. 1 (B), phosphorus was added to the concentration of 1 to form a pair of impurity regions (7) and (8).

Furthermore, after the resist film (6) of the gate electrode (4) is removed, the substrate (1) is exposed to strong light (1
The optical annealing of 0) was performed. That is, for the ultra-high pressure mercury lamp (output 5KW, wavelength 250 to 600 nm, light diameter 15 mm, length 180 mm), the back side uses a parabolic reflector and uses a quartz cylindrical lens (focal length 150 cm,
The light-collecting part has a width of 2 mm and a length of 180 mm) to form a linear irradiation part. The irradiation surface of the substrate (1) is 5
The whole surface of the substrate 10 cm × 10 cm was irradiated with intense light (10) by scanning at a speed of cm / min to 50 cm / min. As a result, the gate electrode (4) was sufficiently polycrystallized by absorbing light because a large amount of phosphorus was added to the gate electrode (4) side.

Further, the impurity regions (7) and (8) are melted and recrystallized once, so that the scanning direction, that is, X
The melting and recrystallization were shifted (moved) in the direction. As a result, the crystal grain size could be increased because a growth mechanism was added as compared with the case where the entire surface was uniformly heated or irradiated with light. The region polycrystallized by this strong light anneal is
It is not necessary to reach the entire area below the impurity regions (7) and (8). As shown by broken lines (11) and (11 ') in FIG. 1, only the upper layer is crystallized and the impurity region
It is important to activate (7) and (8).

Further, the ends (15) and (15 ') of the source region and the drain region are connected to the ends (16) and (1
6 ') is provided so as to enter the channel region side. Then, the channel forming region including the N-type impurity regions (7) and (8), the I-type non-single crystal semiconductor region (2), the junction interfaces (17) and (17 ') is a non-single crystal region in the I-type semiconductor region. It has a hybrid structure composed of a semiconductor and a crystallized semiconductor that enters from an impurity region. The degree of crystallized semiconductor in the I-type semiconductor region is determined by the scanning speed and intensity (illuminance) of the optical anneal.

After the step of FIG. 1B, the polyimide resin is coated on the entire surface to a thickness of 2 μm. Then, in the polyimide resin, after the electrode holes (13) and (13 ') are formed,
Aluminum om contact and its lead (1
4) and (14 ') are formed. This second layer lead (14), (1
4 ′) may be connected to the gate electrode (4) when formed. The result of this optical annealing is that the sheet resistance is 4 × 10 ^-3 (ohm cm) ^-1 to 1 × 10 ⁺² (ohm cm) before light irradiation.
It became ^-1 , and the electric conductivity characteristics were improved compared to before the photo-annealing.

FIG. 2 is a graph showing characteristics of drain current-gate voltage according to an embodiment of the present invention. When the length of the channel formation region is 3 μm and 10 μm, the channel width is 1
Under the condition of mm, the sign (2
1), (22), V _th = + 2V, V _DD =
A current of 1 × 10 ^-5 A and 2 × 10 ^-5 A was obtained at 10V. In addition,
The off-state current was (V _GG = 0V) 10 ⁻¹⁰ to 10 ⁻¹¹ (A), which was 10 ⁻⁴ times smaller than that of the single crystal semiconductor, 10 ⁻⁶ (A). This embodiment employs a manufacturing process in which a coating film is gradually formed and processed from the lower side, so that large area and large scale integration can be performed. Therefore, a large area such as 30
It is possible to fabricate 500 × 500 insulated gate field effect semiconductor devices in a panel of 30 cm × 30 cm, and it can be applied as an insulated gate field effect semiconductor device for controlling liquid crystal display elements. It was

Since the low temperature treatment is performed at 400 ° C. or lower by the photo anneal process, it is possible to prevent the polycrystallized or single crystallized semiconductor from releasing hydrogen or halogen element therein. Further, the optical annealing was performed not from the entire surface of the substrate at the same time, but from one end to the other end. Therefore, the light emitted from the cylindrical ultra-high pressure mercury lamp was linearly condensed by the parabolic mirror and the quartz lens. The linearly condensed light was able to optically anneal the surface of the non-single-crystal semiconductor by scanning the substrate in a direction orthogonal to this.

Since this optical annealing is performed by ultraviolet rays,
Crystallization was promoted from the surface of the non-single crystal semiconductor toward the inside. Therefore, the sufficiently polycrystallized or single-crystallized impurity region near the surface can control the current flowing in the channel formation region in the immediate vicinity of the gate insulating film without any trouble. Light irradiation annealing - Upon le step, hydrogen or a halogen element added to the channel formation region is not affected at all, since it is possible to hold the non-single-crystal semiconductor state, the off-current to 1/10 ^{3 to} the single crystal semiconductor
It can be 1/10 ⁵ . Since the source region and the drain region are formed by optical annealing after forming the gate electrode, the characteristics are stabilized without depositing dirt on the interface of the gate insulator.

Further, as compared with the conventionally known method, not only quartz glass is used as a substrate material, but also a so-called arbitrary substrate is used.
Douglas and heat resistant organic films can also be used. The formation of non-single-crystal semiconductors-gate insulators-gate electrodes that make up the channel formation region, which is the interface of different materials, can be done without exposing them to the atmosphere by the process in the same reaction furnace. It has the feature that

In this embodiment, it is important that the non-single crystal semiconductor in the channel formation region has an impurity concentration of 5 × 10 ¹⁸ cm ^-3 or less for all of oxygen, carbon and nitrogen. That is, in the conventionally known insulated gate field effect semiconductor device, the channel layer has 1 to 3 ×.
It is mixed at a concentration of 10 ²⁰ cm ^-3 . The P channel type insulated gate field effect semiconductor device using the non-single crystal semiconductor in the conventional example flows only a current which is ⅓ or less of the characteristic of the insulated gate field effect transistor device in this example. The hysteresis characteristic of the insulated gate field effect semiconductor device using the non-single crystal semiconductor in the above-mentioned conventional example has the drain electric field of 2 × 10 5 in addition to the I _DD ─V _GG characteristic.
It was observed when ⁶ V / cm or more was applied. Also,
As in this embodiment, the oxygen in the non-single crystal semiconductor is adjusted to 5 × 10 ^18.
When it was set to be cm ⁻³ or less, no hysteresis was observed even at a voltage of 3 × 10 ⁶ V / cm.

[0021]

According to the present invention, since an extremely small amount of oxygen, carbon, and nitrogen of 5 × 10 ¹⁸ cm ⁻³ or less is provided on the surface of the insulating substrate, the I-type non-single-crystal semiconductor layer is provided. In addition, the I-type non-single-crystal semiconductor layer may have a P-type or N-type
Since the crystallization is promoted only in the region to which the impurity of the type is added, the gate voltage-drain current characteristic has no hysteresis and good switching characteristics at a high frequency are obtained. According to the present invention, I
In order to promote crystallization of all the non-single-crystal semiconductor layer, the switching characteristics of the insulated gate field effect semiconductor device are
Even better at higher frequencies.

[Brief description of drawings]

1A to 1C are vertical sectional views of an insulated gate field effect semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a drain current-gate voltage characteristic according to an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Non-single-crystal semiconductor layer 3 ... Gate insulating film 4 ... Gate electrode 5 ... Area | region which forms an insulated gate field effect semiconductor device 6 ... Resist film 7, 8 ... Impurity region 10 ... Strong light 11, 11 '... Broken line 13, 13' ... Hole 14, 14 '... Lead 15, 15' ... End of source region and drain region Part 16, 16 '... Edge of gate electrode 17, 17' ... Bonding interface

Claims (3)

[Claims] 1. An I-type non-single-crystal semiconductor layer, which is formed on a substrate having an insulating surface and contains oxygen, carbon, or nitrogen of 5 × 10 ¹⁸ cm ⁻³ or less, and an I-type non-single-crystal semiconductor layer having P -Type or N-type impurities are added, and hydrogen or halogen is provided between the source region and the drain region and the source region and the drain region formed by promoting crystallization of the region added with the impurities. A channel forming region formed in the I-type non-single-crystal semiconductor layer to which the element and the impurity are added; and a gate electrode formed on the channel forming region via a gate insulating film. Insulated gate type field effect semiconductor device. 2. The pair of impurity regions formed of a source region and a drain region according to claim 1,
An insulated gate field effect semiconductor device comprising a polycrystalline semiconductor to which hydrogen or a halogen element is added at a concentration of 1 atomic% or more. 3. A channel formation region for selectively forming an insulated gate field effect semiconductor device on a substrate having an insulating surface, a non-single-crystal semiconductor layer consisting only of a source region and a drain region, and an insulating surface. A channel formation region formed on a substrate, in which oxygen, carbon, or nitrogen is 5 × 10 ¹⁸ cm ⁻³ or less, and P-type or N-type impurities are added to the non-single-crystal semiconductor layer, and crystallization is performed. An insulated gate field effect semiconductor device, comprising: a source region and a drain region formed by promoting the formation of a gate electrode; and a gate electrode formed on the channel formation region via a gate insulating film.