JPH0697812A - プッシュプルカスコード論理 - Google Patents

プッシュプルカスコード論理

Info

Publication number
JPH0697812A
JPH0697812A JP2418596A JP41859690A JPH0697812A JP H0697812 A JPH0697812 A JP H0697812A JP 2418596 A JP2418596 A JP 2418596A JP 41859690 A JP41859690 A JP 41859690A JP H0697812 A JPH0697812 A JP H0697812A
Authority
JP
Japan
Prior art keywords
transistors
circuit
coupled
logic
voltage supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2418596A
Other languages
English (en)
Japanese (ja)
Inventor
Bruce A Gieseke
エイ ギーセック ブルース
Robert A Conrad
エイ コンラード ロバート
James J Montanaro
ジェイ モンタナロ ジェイムズ
Daniel W Dobberpuhl
ダブリュー ドーバープール ダニエル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of JPH0697812A publication Critical patent/JPH0697812A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356104Bistable circuits using complementary field-effect transistors
    • H03K3/356113Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356147Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • H03K19/1738Controllable logic circuits using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
JP2418596A 1990-01-04 1990-12-27 プッシュプルカスコード論理 Pending JPH0697812A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/460,818 US5023480A (en) 1990-01-04 1990-01-04 Push-pull cascode logic
US460818 1990-01-04

Publications (1)

Publication Number Publication Date
JPH0697812A true JPH0697812A (ja) 1994-04-08

Family

ID=23830189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2418596A Pending JPH0697812A (ja) 1990-01-04 1990-12-27 プッシュプルカスコード論理

Country Status (7)

Country Link
US (1) US5023480A (cg-RX-API-DMAC7.html)
EP (1) EP0440514A3 (cg-RX-API-DMAC7.html)
JP (1) JPH0697812A (cg-RX-API-DMAC7.html)
KR (1) KR910015122A (cg-RX-API-DMAC7.html)
AU (1) AU639517B2 (cg-RX-API-DMAC7.html)
CA (1) CA2033490A1 (cg-RX-API-DMAC7.html)
TW (1) TW197533B (cg-RX-API-DMAC7.html)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5382843A (en) * 1990-02-02 1995-01-17 Gucyski; Jeff One or two transistor logic with temperature compensation and minimized supply voltage
JP2975122B2 (ja) * 1990-12-26 1999-11-10 富士通株式会社 レベル変換回路
EP0505653A1 (en) * 1991-03-29 1992-09-30 International Business Machines Corporation Combined sense amplifier and latching circuit for high speed ROMs
US5490156A (en) * 1993-03-05 1996-02-06 Cyrix Corporation Cross-coupled parity circuit with charging circuitry to improve response time
US5508640A (en) * 1993-09-14 1996-04-16 Intergraph Corporation Dynamic CMOS logic circuit with precharge
US5455528A (en) * 1993-11-15 1995-10-03 Intergraph Corporation CMOS circuit for implementing Boolean functions
US5608741A (en) * 1993-11-23 1997-03-04 Intel Corporation Fast parity generator using complement pass-transistor logic
JP2947042B2 (ja) * 1993-12-28 1999-09-13 日本電気株式会社 低位相差差動バッファ
SE503568C2 (sv) * 1994-03-23 1996-07-08 Ericsson Telefon Ab L M Signalmottagande och signalbehandlande enhet
JP3204848B2 (ja) * 1994-08-09 2001-09-04 株式会社東芝 レベル変換回路及びこのレベル変換回路を用いてレベル変換されたデータを出力する方法
US5568069A (en) * 1995-02-27 1996-10-22 Hughes Aircraft Company High speed, low power pipelined logic circuit
US5841298A (en) * 1996-04-25 1998-11-24 Industrial Technology Research Institute Locally asynchronous, pipeline-able logic circuits for true-single-phase synchronous logic circuit
US5815006A (en) * 1996-04-25 1998-09-29 Industrial Technology Research Institute Single transition per evaluation phase latch circuit for pipelined true-single-phase synchronous logic circuit
US5886540A (en) 1996-05-31 1999-03-23 Hewlett-Packard Company Evaluation phase expansion for dynamic logic circuits
US6069495A (en) * 1997-11-21 2000-05-30 Vsli Technology, Inc. High-speed logic embodied differential dynamic CMOS true single phase clock latches and flip-flops with single transistor clock latches
US6144228A (en) * 1999-02-01 2000-11-07 Compaq Computer Corporation Generalized push-pull cascode logic technique
US6463548B1 (en) 1999-05-10 2002-10-08 Compaq Information Technologies Group, L.P. Method and apparatus to enforce clocked circuit functionality at reduced frequency without limiting peak performance
WO2001047112A2 (en) * 1999-12-13 2001-06-28 Broadcom Corporation High speed flip-flop
US20020070782A1 (en) 1999-12-13 2002-06-13 Afghahi Morteza Cyrus High speed flip-flop
US6580296B1 (en) 2000-09-22 2003-06-17 Rn2R, L.L.C. Low power differential conductance-based logic gate and method of operation thereof
US6433601B1 (en) 2000-12-15 2002-08-13 Koninklijke Philips Electronics N.V. Pulsed D-Flip-Flop using differential cascode switch
US6441648B1 (en) * 2001-05-09 2002-08-27 Intel Corporation Double data rate dynamic logic
US6777992B2 (en) 2002-04-04 2004-08-17 The Regents Of The University Of Michigan Low-power CMOS flip-flop
DE10217375B4 (de) 2002-04-18 2006-08-24 Infineon Technologies Ag Schaltungsanordnung und Verfahren zur Erzeugung eines Dual-Rail-Signals
RU2258303C1 (ru) * 2003-12-15 2005-08-10 Институт проблем управления им. В.А. Трапезникова РАН Парафазный логический элемент на кмдп транзисторах
US7227383B2 (en) * 2004-02-19 2007-06-05 Mosaid Delaware, Inc. Low leakage and data retention circuitry
US7622977B2 (en) * 2005-10-27 2009-11-24 The Regents Of The University Of Michigan Ramped clock digital storage control
US7692466B2 (en) * 2006-08-18 2010-04-06 Ati Technologies Ulc Sense amplifier based flip-flop
US7973565B2 (en) * 2007-05-23 2011-07-05 Cyclos Semiconductor, Inc. Resonant clock and interconnect architecture for digital devices with multiple clock networks
WO2011046977A2 (en) * 2009-10-12 2011-04-21 Cyclos Semiconductor, Inc. Architecture for controlling clock characteristics

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2934599C3 (de) * 1979-08-27 1982-04-08 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur Bildung von Prüfbits in einer Fehlerkorrektureinrichtung
JPS58170120A (ja) * 1982-03-30 1983-10-06 Nec Corp 半導体集積回路
JPS6010816A (ja) * 1983-06-27 1985-01-21 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション 差動論理回路
US4570084A (en) * 1983-11-21 1986-02-11 International Business Machines Corporation Clocked differential cascode voltage switch logic systems
US4739198A (en) * 1985-03-11 1988-04-19 Nec Corporation Signal output circuit of a push-pull type
US4695744A (en) * 1985-12-16 1987-09-22 Rca Corporation Level shift circuit including source follower output
US4833347A (en) * 1986-02-28 1989-05-23 Honeywell, Inc. Charge disturbance resistant logic circuits utilizing true and complement input control circuits
GB2209104A (en) * 1987-08-26 1989-04-26 Philips Nv An amplifier load circuit and an amplifier including the load circuit
US4816706A (en) * 1987-09-10 1989-03-28 International Business Machines Corporation Sense amplifier with improved bitline precharging for dynamic random access memory
JPH0716158B2 (ja) * 1988-05-13 1995-02-22 日本電気株式会社 出力回路およびそれを用いた論理回路
KR910005609B1 (ko) * 1988-07-19 1991-07-31 삼성전자 주식회사 복수전압 ic용 입력신호 로직 판별회로
DE68927005T2 (de) * 1988-10-11 1997-02-20 Oki Electric Ind Co Ltd Schaltung für einen differentiellen kreisverstärker

Also Published As

Publication number Publication date
AU639517B2 (en) 1993-07-29
CA2033490A1 (en) 1991-07-05
EP0440514A3 (en) 1992-03-04
KR910015122A (ko) 1991-08-31
TW197533B (cg-RX-API-DMAC7.html) 1993-01-01
EP0440514A2 (en) 1991-08-07
US5023480A (en) 1991-06-11
AU6860191A (en) 1991-07-11

Similar Documents

Publication Publication Date Title
JPH0697812A (ja) プッシュプルカスコード論理
TW423218B (en) Charge-redistribution low-swing differential logic circuit
US6014041A (en) Differential current switch logic gate
JP5430507B2 (ja) 電圧レベルシフタ
JP2000207887A (ja) ラッチ型センス増幅器
JP2021052393A (ja) 高コモンモード過渡耐性高電圧レベルシフタ
US8324932B2 (en) High-speed static XOR circuit
US20030210078A1 (en) Current source evaluation sense-amplifier
US7429880B2 (en) Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI)
US20050162193A1 (en) High performance sense amplifiers
CN110119640B (zh) 双轨预充电逻辑单元及其预充电方法
US6252426B1 (en) High speed logic family
JP2861910B2 (ja) 出力回路
US20070008014A1 (en) Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices
CN110855287B (zh) 基于延迟门控正反馈的高速动态多米诺全加器
US6326814B1 (en) Method and apparatus for enhancing noise tolerance in dynamic silicon-on-insulator logic gates
KR100837022B1 (ko) 감지증폭회로
JPH10327066A (ja) トランジスタ論理回路におけるnMOSゲート入力型センスアンプ
CN214069906U (zh) 复合逻辑门电路和矿机设备
CN114793114B (zh) 复合逻辑门电路和计算设备
JP2551586B2 (ja) インタフエ−ス回路
Singh et al. Analysis and design guidelines for customized logic families in CMOS
US7023255B1 (en) Latch with data jitter free clock load
JPS61198817A (ja) 半導体集積回路装置
Zhao et al. A low power domino with differential-controlled-keeper

Legal Events

Date Code Title Description
A977 Report on retrieval

Effective date: 20040705

Free format text: JAPANESE INTERMEDIATE CODE: A971007

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040722

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040810

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070820

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080820

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 5

Free format text: PAYMENT UNTIL: 20090820

LAPS Cancellation because of no payment of annual fees
S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350