JPH0656461B2 - Matrix array - Google Patents

Description

The present invention relates to a matrix array using a MOS field effect transistor, and more particularly to a method for constructing a matrix array to facilitate the repair of defects.

Development of a large-area display device using a matrix array has been actively progressed recently, and it is expected to have a wide range of applications such as small information devices and handy-type televisions. As a flat-panel large-capacity display device, a device in which switching elements are arranged in a matrix array is most promising.

FIG. 1 is a layout diagram showing an example of the configuration of an active matrix array substrate in which nonlinear switching elements are arranged in a matrix array. A region surrounded by 1 in the drawing is a display region, and the non-linear elements 2 are arranged in a matrix therein. Reference numeral 3 is a data signal line (source line) to the non-linear element 2, and 4 is a timing signal line (gate line) to the non-linear element 2. As shown in FIG. 1, when the matrix array substrate is configured, defects easily occur in addition to pattern defects that occur when patterning each line and non-linear element, as well as insulation defects and non-linear defects at intersections of source lines and gate lines. Insulation failure of the element 2 may be mentioned. For pattern defects, the number of defects can be reduced to a considerably low level by improving the process, removing dust, etc., whereas for insulation defects, improving the quality of the insulating layer and increasing the thickness. Although it is possible to reduce the number of defects in the initial stage due to factors such as the above, static electricity often causes insulation defect defects between lines after the matrix array is completed. As can be seen from FIG. 1, this static electricity defect causes static electricity on the source line or the gate line outside the display area of the panel, resulting in insulation failure at the intersection of the line and the line orthogonal to that line. The data signal leaks to the gate line, the timing signal leaks to the source line, and the display of all the pixels on the line including the defective insulation portion becomes defective, resulting in a so-called line defect, which significantly impairs the display characteristics. The correction method when such an insulation failure occurs is not only by cutting the source line or the gate line before and after the insulation failure point, and the source line or the gate line is broken by such a correction method. All the pixels connected to this broken line are non-lighting defects, and the remaining line defects cannot be removed. When the matrix array is constructed on a single crystal silicon substrate, it is possible to protect the matrix array from static electricity by forming a diode and a resistor for static electricity protection in the silicon substrate, but the matrix array on the glass plate When the array is configured, it is difficult to provide a static electricity protection circuit, and thus the above-described insulation failure is likely to occur in a large amount, and mass production of the matrix array is difficult.

FIG. 2 shows an example of a matrix array using a MOS field effect transistor as a non-linear element, and shows an equivalent circuit of one pixel of a matrix array liquid crystal display device. Reference numeral 5 is a MOS field effect transistor for switching data signals. Reference numeral 6 is a capacitor, which is used for holding a data signal. Reference numeral 7 is a liquid crystal panel, 7-1 is a liquid crystal drive electrode formed corresponding to the liquid crystal drive element, and 7-2 is an upper glass panel. Specific examples of the matrix array in the example of FIG. 2 are (a) and (b) of FIG.
(a) is a plan view and (b) is a cross-sectional view taken along the dashed-dotted line Elo in (a). This is an example in which a matrix array is formed by forming thin film transistors on the glass substrate 15. The surface of the polycrystalline silicon 8 is thermally oxidized to form the gate insulating film 13, and then the second-layer polycrystalline film is formed. By forming and patterning silicon, the gate line 9 and the gate electrode 9 of the transistor and one electrode 12 of the charge storage capacitor are simultaneously formed. further,
Impurities are diffused into the second-layer polycrystalline silicon 9 and 12, and at the same time, the gate electrode 9 of the first-layer polycrystalline silicon 8 is formed.
Impurities are also diffused into the region not covered with the silicon to form the source / drain of the transistor. Next, after forming the interlayer insulating film 14 on the entire surface, contact holes are formed in the source / drain regions of the transistor. Finally, the source line 10 and the pixel drive electrode 11 are formed to complete the matrix array. In this case, the interlayer insulating film 14 not only insulates the gate line 9 from the source line 10,
Since the insulating film of the charge storage capacitor composed of the electrodes 11 and 12 also serves as the charge storage capacitor, the capacitance of this capacitor cannot take a sufficient value unless it is made as thin as possible. For example, when the size of one pixel is 1 mm square, the size of the capacitor is from the brightness of the screen to about 200 μm 2, and the insulating film is made of silicon oxide and has a thickness of 5 mm.
In case of 000 angstrom, the condenser capacity is about 2.
You only get 5 picofarads. On the other hand, the capacity of the pixel liquid crystal is about 9 picofarads when the thickness of the liquid crystal is 10 microns. The capacity of the condenser is of no existence value unless it has at least the capacity of the liquid crystal, and ideally 2 to
It is necessary to triple. Therefore, for this purpose, the film thickness of the interlayer insulating film is reduced to about 1/5 to 1/10, or the area is set to 5
You have to multiply by 10 times. As described above, the area cannot be larger than the above size due to the brightness of the panel, and the only method is to thin the interlayer insulating film. In this case, the silicon oxide film must have a film thickness of 1000 angstroms or less. Even if a silicon nitride film having a large relative dielectric constant is used, the dielectric constant is at most twice that of the silicon oxide film, so the film thickness must be thinned to about 1000 to 2000 angstroms. Considering the gate insulating film 13 of the transistor, on the other hand, this thickness is usually 1000 to 2000 angstroms even if it is thin, and in some cases 5000 angstroms or more is required due to the breakdown voltage of the transistor. Comparing the breakdown voltage between the interlayer insulating film and the gate insulating film of the transistor, since the gate insulating film is a thermal oxide film of silicon, the breakdown voltage is higher than that of a silicon oxide film such as an interlayer insulating film formed by vapor phase epitaxy. Is about twice as large as that of the same thickness, and when the thickness of the interlayer insulating film and the gate insulating film is set to 1000 to 2000 angstroms as described above, the withstand voltage of the interlayer insulating film is always lower. If the source line and the gate line cross each other when the source line is charged with static electricity, the capacity of the capacitor will decrease and the effect of inserting the capacitor will disappear, as can be seen from FIG.

The present invention has been made in view of the above points, increasing the breakdown voltage at the intersection of the gate line and the source line, does not become a linear defect even if the defect caused by electrostatic breakdown is corrected, Also, the capacity of the condenser can be set to a sufficient value.

The present invention will be described in detail below with reference to the drawings.

FIG. 4 shows an example of carrying out the present invention.
(a) is a cross-sectional view at the same position as the cross-sectional view of FIG. 3 (b),
(b) is a plan view showing only the vicinity of the intersection of the source line 10 and the gate line 9. Each member number in FIG. 4 is the third
Similar to the figure, the manufacturing method is the same as the example of FIG. 3 up to formation of the gate line 9 and the capacitor electrode 12 and diffusion of impurities. As the interlayer insulating film, first, the first-layer silicon oxide film 14-1 is formed on the entire surface of the substrate, and then the second-layer silicon oxide film is formed on the entire surface of the substrate. As described above, the second-layer silicon oxide film other than the intersecting region between the gate line 9 and the source line 10 is removed by etching. Next, similarly to the example of FIG. 3, a contact hole is opened in the first layer silicon oxide film of the source / drain region of the transistor, and the source line 10 is formed to complete the process. First layer silicon oxide film 14-1
Is 1000 angstroms or less to secure the capacitance of the capacitor, and the thickness of the second layer silicon oxide film is preferably 5000 angstroms or more in consideration of the breakdown voltage between the gate line and the source line. As a result, the capacitance of the capacitor can be sufficiently secured, and the breakdown voltage at the intersection of the gate line and the source line can be made higher than the gate breakdown voltage of the transistor.

In the example of FIG. 4, the interlayer insulating film 14- formed on the entire surface of the substrate
1 was first formed, and then the interlayer insulating film 14-2 provided only in the intersection region of the source line and the gate line was formed. However, the order may be reversed, and both insulating films may be formed like silicon oxide films. In the case of forming the same material, since 14-2 is thicker, etching is easier. Further, when the insulating film 14-1 is first formed as shown in FIG. 4, if it is formed of a silicon nitride film and the insulating film 14-2 is formed of a silicon oxide film, etching during patterning as shown in FIG. It has selectivity and is better.

FIG. 5 shows another embodiment of the present invention (a)
Is a plan view, and (b) is a cross-sectional view taken along the dashed-dotted line Hanni in (a). The manufacturing process is the same as in the example of FIG.
A thermal oxide film 13 is grown on the surface of the silicon thin film 8, and second silicon thin films 9 and 12 are formed and patterned thereon. Further, the second silicon thin films 9 and 12
Then, the impurities are diffused into a region of the silicon thin film 8 which is not covered with the silicon thin film 9. After this, first, the developed insulating film 14-2 of the first layer is removed by etching, and the interlayer insulating film on the surface of the silicon thin film 12 used as one electrode of the capacitor is the first layer 14-1 only. Next, contact holes are opened in the interlayer insulating film on the source / drain regions of the transistors, the source lines 10 and the pixel drive electrodes 11 are formed, and the array is completed. As in the case of the example of FIG. 4, the film thickness of the interlayer insulating film 14-1 is about 1000 angstroms, and the film thickness of the interlayer insulating film 14-2 is 5000.
If it is more than Angstrom, the withstand voltage between both lines at the intersection of the source line and the gate line can be higher than the gate withstand voltage of the transistor.
It is possible to set the capacity of the pixel capacitor to a sufficient value. In the case of FIG. 5, since the thick interlayer insulating film also covers the transistor, it is useful for the protection of the device and the reliability is improved. Further, the thick interlayer insulating film 14-2 is as shown by the broken line 16 in FIG. , It is not necessary to remove it from the condenser electrode,
Although the periphery of the capacitor electrode may be covered, the larger the area where the interlayer film 14-2 is removed by etching, the larger the capacity of the capacitor can be. The material of the two interlayer insulating films 14-1 and 14-2 is generally a silicon oxide film, but a silicon nitride film, alumina, etc. may be used.
It goes without saying that the layers may be formed first as in the example of FIG. Further, in the embodiment shown in FIG. 5, the dead space of the pixel drive electrode is reduced and the contrast is improved. In this way, the gate line 9 covers the transistor 8 with the pixel drive electrode 11 so that the insulating film is 1
It is possible to use only 1 of 4 but thicker insulating film 1
The presence of 4-2 is effective in reducing defects such as shorts.

As described above, the matrix array of the present invention includes a plurality of gate lines, a plurality of source lines orthogonal to the plurality of gate lines with an insulating film interposed therebetween, a plurality of gate lines and the plurality of source lines. In a matrix array including thin film transistors provided at intersections and charge holding capacitors connected to the thin film transistors, the charge holding capacitor has a first insulating layer sandwiched between two electrodes, The insulating film in the intersection region of the gate line and the source line is composed of the first insulating layer and the second insulating layer, and the insulating film is at least the first insulating layer of the charge holding capacitor. It is characterized by being thick,
It has the following effects.

A) When static electricity enters the matrix array, the insulation layer of the charge holding capacitor or the insulation layer on the thin film transistor, which is thinner than the insulation layer at the intersection of the gate line and the source line, is destroyed first, so the gate line Do not short-circuit at the intersection of the and source lines. Therefore, the influence of static electricity is sufficient for a point defect of one pixel, and a line defect is not caused.

B) Furthermore, since the insulating film in the intersection region of the gate line and the source line is formed by stacking two insulating layers, even if there is a pinhole in one insulating layer, the same position in the other insulating layer. It is extremely unlikely that pinholes will form in the. Therefore,
Short-circuit defects between lines can be almost completely prevented.

C) Since there is a charge holding capacitor, the data signal holding characteristics of the matrix array are improved.

The application of the present invention is not limited to the matrix array in which the capacitor electrodes are independently provided as shown in the above embodiment, but can be applied to the matrix array of the type in which the gate line of the adjacent pixel is shared with the capacitor electrode of the pixel. Is.

[Brief description of drawings]

FIG. 1 is a layout diagram showing a configuration example of a matrix array,
FIG. 2 is a wiring diagram showing an equivalent circuit of an example of a matrix array display device using a liquid crystal as a display body.
(a), (b) is the top view and sectional drawing which show the specific example of the example of FIG. 4 (a) and 4 (b) are a plan view and a sectional view showing an example in which the present invention is carried out, and FIGS. 5 (a) and 5 (b) show another embodiment of the present invention. It is a top view and a sectional view.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshihiko Mano 3-3-5 Yamato, Suwa City, Nagano Stock Company Suwa Seikosha Co., Ltd. (56) Reference JP-A-58-125087 (JP, A) 54-152894 (JP, A) JP-A-58-190042 (JP, A)

Claims (1)

[Claims] 1. A thin film provided at a plurality of gate lines, a plurality of source lines orthogonal to the plurality of gate lines via an insulating film, and a thin film provided at an intersection of the plurality of gate lines and the plurality of source lines. A matrix array including a transistor and a charge holding capacitor connected to the thin film transistor, wherein the charge holding capacitor sandwiches a first insulating layer between two electrodes, and the gate line and the source line. Is characterized in that the insulating film in the intersection region of is composed of the first insulating layer and the second insulating layer, and the insulating film is at least thicker than the first insulating layer of the charge holding capacitor. Matrix array.