WO2010131393A1 - Wiring structure, wiring substrate, liquid crystal display panel, and method for manufacturing wiring structure - Google Patents

Wiring structure, wiring substrate, liquid crystal display panel, and method for manufacturing wiring structure Download PDF

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Publication number
WO2010131393A1
WO2010131393A1 PCT/JP2010/000959 JP2010000959W WO2010131393A1 WO 2010131393 A1 WO2010131393 A1 WO 2010131393A1 JP 2010000959 W JP2010000959 W JP 2010000959W WO 2010131393 A1 WO2010131393 A1 WO 2010131393A1
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WO
WIPO (PCT)
Prior art keywords
wiring
insulating film
wirings
substrate
intersect
Prior art date
Application number
PCT/JP2010/000959
Other languages
French (fr)
Japanese (ja)
Inventor
田中信也
菊池哲郎
山崎周郎
嶋田純也
Original Assignee
シャープ株式会社
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Publication of WO2010131393A1 publication Critical patent/WO2010131393A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5221—Crossover interconnections
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a wiring structure and the like arranged so as to cross each other through an insulating film.
  • Patent Document 1 discloses an example in which a shift register is configured by gate monolithic. The configuration of Patent Document 1 will be described with reference to FIG.
  • FIG. 9 shows a configuration of a liquid crystal display device having a conventional wiring structure.
  • the conventional wiring structure is connected to each of the plurality of main wirings 550 arranged in the gate driving circuit region and each of the main wirings 550 through the contact hole 570, and crosses the main wiring 550.
  • a branch wiring 560 is formed.
  • the branch wiring 560 branched from the main wiring 550 is arranged to intersect with the plurality of main wirings 550.
  • a capacitance is formed in a region where the main wiring 550 and the branch wiring 560 intersect (hereinafter referred to as a cross capacitance).
  • the cross capacitance is formed, the waveform shape of a signal output from the main wiring 550 or the branch wiring 560 becomes dull.
  • Patent Documents 2 and 3 do not take into account the cross capacitance due to the wiring crossing, and there arises a problem that the reliability of the output signals from the wirings crossing each other is lowered.
  • the present invention has been made in view of the above-described problems, and an object thereof is to realize a wiring structure with high output signal reliability.
  • a wiring structure of the present invention is formed by covering a plurality of first wirings disposed on a substrate and an upper layer of the substrate, covering the plurality of first wirings.
  • An insulating film, and a second wiring which is an upper layer of the insulating film and is arranged so as to intersect at least one of the plurality of first wirings with the insulating film interposed therebetween,
  • a laminated portion made of an insulating material is formed at least in a region where the first wiring and the second wiring intersect, and the second wiring includes the insulating film and the laminated portion. This is characterized in that it intersects with the first wiring.
  • a method for manufacturing a wiring structure includes a first wiring forming step of patterning a plurality of first wirings on a substrate, and the first wiring formed in the first wiring forming step.
  • a second wiring forming step of patterning the second wiring so as to intersect the first wiring is
  • a laminated portion made of the insulating film material is provided in addition to the insulating film. Yes.
  • the second wiring crosses the first wiring through the insulating film and the stacked portion. That is, the thickness of the insulating material in the region where the first wiring and the second wiring intersect is formed thicker than the thickness of the other regions.
  • a wiring structure includes a display driving circuit monolithically formed on a substrate, and a plurality of second driving circuits disposed on the substrate and supplying driving signals to the driving circuit.
  • One wiring, an upper layer of the substrate and covering the plurality of first wirings, and an upper layer of the insulating film, the plurality of first It is connected to at least one of the wirings through a contact hole formed in the insulating film, and serves as an input wiring for a predetermined driving signal to the driving circuit, and the plurality of first wirings
  • a stack of materials is formed Cage, the second wiring through the insulating film and the laminated portion, is characterized in that intersects with the first wiring.
  • the wiring structure of the present invention includes a plurality of first wirings disposed on a substrate, an insulating film formed on the substrate and covering the plurality of first wirings, and the insulating film.
  • a laminated portion made of an insulating material is formed in a region where one wiring and the second wiring intersect, and the second wiring is connected to the first wiring via the insulating film and the laminated portion. It is a configuration that intersects.
  • the wiring structure of the present invention includes a display driving circuit monolithically formed on a substrate, a plurality of first wirings arranged on the substrate and supplying a driving signal to the driving circuit, and an upper layer of the substrate An insulating film formed so as to cover the plurality of first wirings, and an upper layer of the insulating film, wherein at least one of the plurality of first wirings is interposed through the insulating film, and It is connected via a contact hole formed in the insulating film and serves as an input wiring for a predetermined driving signal to the driving circuit, and intersects with at least one of the other first wirings.
  • a laminated portion made of an insulating material is formed in an upper layer of the insulating film and at least in a region where the first wiring and the second wiring intersect with each other.
  • the second wiring is Insulating film and through the laminated portion, it is configured to intersect with the first wiring.
  • a first wiring forming step of patterning a plurality of first wirings on a substrate, and an insulating film is formed to cover the first wiring formed in the first wiring forming step.
  • An insulating film forming step and an upper layer of the insulating film formed in the insulating film forming step, wherein the first wiring and a second wiring different from the first wiring are crossed through the insulating film.
  • the first wiring is formed through a stacked portion forming step of forming a stacked portion made of an insulating material in the region, the stacked portion formed in the stacked portion forming step, and the insulating film formed in the insulating film forming step.
  • FIG. 3 is a cross-sectional view taken along line A-A ′ in FIG. 2. It is a top view showing the structure of the wiring structure of the display panel of this invention. It is the schematic showing the structure of the liquid crystal display device to which the wiring structure of the display panel of this invention is applied. It is an equivalent circuit diagram of the drive circuit connected with the wiring of the wiring structure of the display panel of this invention. It is sectional drawing showing the structure of a general wiring structure. It is a figure showing the clock waveform output from the drive circuit connected with the wiring structure of the display panel of this invention, and the wiring of a general wiring structure. It is a top view showing the 1st modification of the structure of the wiring which applies the wiring structure of the display panel of this invention. It is a top view showing the 2nd modification of the structure of the wiring which applies the wiring structure of the display panel of this invention. It is a top view showing a prior art.
  • FIG. 3 shows a configuration of a liquid crystal display device 1 that is a display device according to the present embodiment.
  • the liquid crystal display device 1 includes a display panel (liquid crystal display panel) 2, a flexible printed circuit board 3, and a control board 4.
  • the display panel 2 includes a display region 2a, a plurality of gate bus lines GL, a plurality of source bus lines SL,... Using amorphous silicon, polycrystalline silicon, CG silicon, microcrystalline silicon, or the like on a glass substrate (substrate) 58.
  • the display panel includes an active matrix wiring substrate in which the gate drivers 5a and 5b are formed, and a counter substrate disposed to face the wiring substrate through a liquid crystal layer.
  • the display area 2a is an area in which a plurality of picture elements PIX ... are arranged in a matrix.
  • the picture element PIX includes a TFT (TFT element) 21 which is a selection element of the picture element PIX, a liquid crystal capacitor CL, and an auxiliary capacitor Cs.
  • the gate of the TFT 21 is connected to the gate bus line GL, and the source of the TFT 21 is connected to the source bus line SL.
  • the liquid crystal capacitor CL and the auxiliary capacitor Cs are connected to the drain of the TFT 21.
  • a counter electrode is disposed on the counter substrate in a region facing the TFT 21 via the liquid crystal layer.
  • the plurality of gate bus lines GL are composed of gate bus lines GL1, GL2, GL3,.
  • the first group of gate bus lines GL consisting of every other gate bus line GL1, GL3, GL5,... Is connected to the output of the gate driver 5a, and every other one is arranged.
  • the second group of gate bus lines GL ... Composed of the gate bus lines GL 2, GL 4, GL 6, etc. connected to the output of the gate driver 5 b.
  • the plurality of source bus lines SL are composed of source bus lines SL1, SL2, SL3,..., SLm, and are connected to the output of the source driver 6 described later. Further, although not shown, auxiliary capacitance lines for applying an auxiliary capacitance voltage to the auxiliary capacitances Cs of the picture elements PIX... Are formed.
  • the gate driver 5a is provided on the display panel 2 in a region adjacent to the display region 2a on one side in the direction in which the gate bus lines GL... Extend, and the first group of gate bus lines GL1 and GL3. ⁇ Supply gate pulses to each of GL5.
  • the gate driver 5b is provided in a region adjacent to the display region 2a on the other side of the display region 2a in the extending direction of the gate bus lines GL, and the second group of gate bus lines GL2 and GL4. -Gate pulses are sequentially supplied to each of GL6.
  • These gate drivers 5a and 5b are built monolithically with the display area 2a in the display panel 2, and all gate drivers called gate monolithic, gate driverless, panel built-in gate drivers, gate-in panels, etc. are gate drivers. 5a and 5b.
  • each of the plurality of gate bus lines GL and each of the plurality of source bus lines SL intersect each other in the display region 2a via an insulating film (not shown).
  • the vertical relationship of wiring between the plurality of gate bus lines GL and the plurality of source bus lines SL is not particularly limited, and can be appropriately selected depending on the configuration of the picture elements PIX, the TFTs 21 and the like.
  • the flexible printed circuit board 3 includes a source driver 6.
  • the source driver 6 supplies a data signal to each of the source bus lines SL.
  • the control board 4 is connected to the flexible printed circuit board 3 and supplies necessary signals and power to the gate drivers 5a and 5b and the source driver 6. Signals and power supplied from the control board 4 to the gate drivers 5a and 5b are supplied from the display panel 2 to the gate drivers 5a and 5b via the flexible printed board 3.
  • FIG. 2 is a plan view showing the main part of the gate driver 5a.
  • FIG. 1 is a cross-sectional view taken along line A-A ′ of FIG.
  • the gate driver 5a is branched from a plurality of trunk wirings (first wirings) 51a, 51b, 51c, 51d and the trunk wirings 51a, 51b, 51c arranged on the glass substrate 58, and one end portion of each of the gate wirings 5a, 51b, 51c.
  • Branch wirings (second wirings) 52a, 52b, 52c, and 52d that are connected to at least one of 51b and 51c and the other terminal is connected to the input side terminal of the drive circuit 55, and branch wirings 52a, 52b, and 52c 52c and 52d, and a drive circuit 55 for outputting signals and power output from the branch lines 52a, 52b, and 52c to the display area 2a.
  • the wiring structure 50 according to the present embodiment can be applied to the wiring structure of the gate driver 5a, for example.
  • the wiring structure 50 includes a plurality of trunk wires 51b, 51c, and 51d disposed on the glass substrate 58, and an insulating film 54 that is an upper layer of the glass substrate and covers the trunk wires 51b, 51c, and 51d. And branch wirings 52 a, 52 b, and 52 c that are arranged on the insulating film 54 so as to intersect any of the trunk wirings 51 b, 51 c, and 51 d via the insulating film 54. .
  • the wiring structure 50 is an upper layer of the insulating film 54, and a laminated portion 56 made of an insulating material is formed at least in a region where the trunk wirings 51b, 51c, 51d and the branch wirings 52a, 52b, 52c intersect. Has been. Further, the branch wirings 52 a, 52 b, and 52 c of the wiring structure 50 are configured to intersect with the trunk wirings 51 b, 51 c, and 51 d through the insulating film 54 and the laminated portion 56.
  • An interlayer insulating film 57 is formed on the insulating film 54, the laminated portion 56 that is a laminated portion of the insulating material with respect to the insulating film 54, and the upper layers of the branch wirings (branch wirings 52 a, 52 b, 52 c, 52 d). .
  • the trunk wirings 51 a, 51 b, 51 c, 51 d are arranged on the glass substrate 58 and supply driving signals to the driving circuit 55.
  • the driving signals supplied by the trunk lines 51a, 51b, 51c, and 51d are input from the control board 4 and include the power supply voltage VSS.
  • the trunk wirings 51a, 51b, 51c, and 51d are formed of gate bus line metal or source bus line metal.
  • a wiring material for forming the trunk wires 51a, 51b, 51c and 51d is formed on a glass substrate by a sputtering method, and the formed wiring material is used as a photo It forms on a glass substrate by patterning by the lithography method (1st wiring formation process).
  • the metal for the gate bus line is, for example, Ta (or TaN), Ti (or TiN), Al (or an alloy containing Al as a main component), Mo (or MoN), and Cr, each in a single layer, or those It can comprise with the laminated structure by some combination of these.
  • the source bus line metal can be made of the same material as that of the gate metal GM, for example, Ta (or TaN), Ti (or TiN), Al (or an alloy containing Al as a main component), Mo ( Or MoN) and Cr can each be formed of a single layer or a laminated structure of some combination thereof.
  • the branch wirings 52 a, 52 b, 52 c, and 52 d are connected to the trunk wirings 51 a, 51 b, 51 c, and 51 d to output signals transmitted to the trunk wirings 51 a, 51 b, 51 c, and 51 d, power supplies, and the like to the drive circuit 55. Wiring branched from each.
  • Each of the branch wirings 52a, 52b, and 52c is connected to at least one trunk wiring (the trunk wiring 51d in the present embodiment) via the insulating film 54 and the stacked portion 56 stacked on the insulating film 54. Crossed.
  • the branch wirings 52a, 52b, 52c, and 52d are formed on the insulating film 54 and the stacked portion 56 after the insulating film 54 and the stacked portion 56 are formed.
  • a wiring material for forming each of the branch wirings 52a, 52b, 52c, and 52d is formed on the insulating film 54 and the laminated portion 56 by sputtering, and the formed wiring material is patterned by photolithography. As a result, the branch wirings 52a, 52b, 52c, and 52d are formed on the insulating film 54 and the stacked portion 56 (second wiring forming step).
  • branch wiring 52 a One end of the branch wiring 52 a is connected to the trunk wiring 51 a through a contact hole 53 a formed in the insulating film 54, and the other end of the branch wiring 52 a is connected to the input terminal VSS of the drive circuit 55.
  • the branch wiring 52 a is arranged so as to intersect with the trunk wirings 51 b, 51 c, 51 d via the insulating film 54 and the stacked portion 56.
  • branch wiring 52 b is connected to the trunk wiring 51 b through a contact hole 53 b formed in the insulating film 54, and the other end of the branch wiring 52 b is connected to the input terminal CKA of the drive circuit 55.
  • the branch wiring 52 b is arranged so as to intersect with the trunk wirings 51 c and 51 d via the insulating film 54 and the stacked portion 56.
  • branch wiring 52 c is connected to the trunk wiring 51 c through a contact hole 53 c formed in the insulating film 54, and the other end of the branch wiring 52 b is connected to the input terminal CKB of the drive circuit 55.
  • the branch wiring 52 c is arranged so as to intersect with the trunk wiring 51 d via the insulating film 54 and the stacked portion 56.
  • branch wiring 52d One end of the branch wiring 52d is connected to the trunk wiring 51d through a contact hole 53d formed in the insulating film 54, and the other end of the branch wiring 52b is connected to the input terminal CKC of the drive circuit 55. Has been.
  • the branch wiring 52d does not intersect any of the trunk wirings 51a, 51b, 51c, and 51d.
  • each of the branch wirings 52a, 52b, and 52c is connected to at least one of the trunk wirings 51a, 51b, and 51c and any one of the contact holes 53a, 53b, and 53c formed in the insulating film 54.
  • the other end is connected to one of the input terminals VSS, CKA, and VKB of the drive circuit 55.
  • the branch wirings 52a, 52b, and 52c serve as input wirings for a predetermined driving signal to the driving circuit 55, and at least one of the trunk wirings 51b, 51c, and 51d, the insulating film 54, and the like. They are arranged so as to intersect with each other through the stacked portion 56.
  • the branch wirings 52a, 52b, and 52c connect any of the trunk wirings 51a, 51b, and 51c to the drive circuit 55, so that the branch wirings 52a, 52b, and 52c, A region intersecting with 51c and 51d is formed.
  • a cross capacitance that causes the waveform of the driving signal supplied to the driving circuit 55 to become dull is generated.
  • the wiring structure 50 is an upper layer of the insulating film 54 and is in a region where at least one of the trunk wirings 51b, 51c, 51d and the branch wirings 52a, 52b, 52c intersect.
  • the laminated portion 56 made of an insulating material is formed, and the branch wirings 52 a, 52 b, and 52 c intersect the trunk wirings 51 b, 51 c, and 51 d through the insulating film 54 and the laminated portion 56.
  • the cross capacitance generated in the region where the trunk wirings 51b, 51c, 51d and the branch wirings 52a, 52b, 52c intersect can be reduced. For this reason, it is possible to suppress the occurrence of cross capacitance and the dullness of the waveform of the driving signal output from the branch wirings 52a, 52b, and 52c, so that the supply is supplied from the branch wirings 52a, 52b, and 52c to the drive circuit 55. The reliability of the driving signal to be performed can be improved.
  • the branch wirings 52a, 52b, 52c, and 52d are made of metal of a material different from that of the trunk wirings 51a, 51b, 51c, and 51d, and the trunk wirings 51a, 51b, 51c, and 51d are made of metal for the source bus line.
  • the branch wirings 52a, 52b, 52c, and 52d are formed of metal for gate bus lines.
  • trunk lines 51a, 51b, 51c, and 51d are made of gate bus line metal
  • branch lines 52a, 52b, 52c, and 52d are made of source bus line metal
  • trunk wires 51a, 51b, 51c, and 51d and the branch wires 52a, 52b, 52c, and 52d can be configured for a material generally used for the TFT 21, for example.
  • the drive circuit 55 has one terminal connected to the branch wirings 52a, 52b, and 52c, and the other terminal connected to the gate bus line GL.
  • the drive circuit 55 is a display drive circuit built monolithically on a substrate.
  • the drive circuit 55 is, for example, a shift register, a power supply circuit for supplying power to the picture element PIX, or a drive circuit for controlling the driving of the TFT 21.
  • the input-side terminal VSS is connected to the branch wiring 52a
  • the input-side terminal CKA is connected to the branch wiring 52b
  • the input-side terminal CKB is connected to the branch wiring 52c.
  • the terminal CKC on the input side is connected to the branch wiring 52d.
  • the terminal GOUT on the output side of the drive circuit 55 is connected to the gate bus line GL1. That is, each of the branch lines 52a, 52b, 52c, and 52d is connected to the gate bus line GL1 and the picture element PIX in the display area 2a via the drive circuit 55.
  • the signal input to the drive circuit 55 from the input terminal VSS may be a power supply voltage or a drive signal.
  • a general configuration can be applied to the internal configuration of the drive circuit 55, and a description thereof will be omitted.
  • the insulating film 54 is formed after the trunk wirings 51a, 51b, 51c and 51d are patterned.
  • the insulating film 54 can be formed by, for example, a CVD method (insulating film forming step).
  • the insulating film 54 is formed on the glass substrate 58 so as to cover the trunk wires 51a, 51b, 51c, and 51d.
  • the insulating film including the insulating film 54 has a thickness in a region where each of the trunk lines 51b, 51c, and 51d intersects each of the branch lines 52a, 52b, and 52c, respectively. Compared with the film thickness of the region where each of the branch wirings 52a, 52b, and 52c does not intersect, it is formed thicker because the stacked portion 56 is formed.
  • the stacked portion 56 only needs to be provided in a region where at least each of the trunk wires 51b, 51c, and 51d and each of the branch wires 52a, 52b, and 52c intersect, and the extending direction of the trunk wires 51b, 51c, and 51d And may be provided on the main wirings 51b, 51c, 51d.
  • the lower limit value of the film thickness of the laminated portion 56 is preferably about 10% of the film thickness of the insulating film 54.
  • the lower limit of the film thickness of the laminated portion 56 is preferably about 300 mm.
  • the upper limit value of the film thickness of the laminated part 56 is preferably about 1 ⁇ m from the coating film thickness when the laminated part 56 is formed as an SOG (spin-on-glass) film, for example.
  • the laminated portion 56 is formed with a thickness of 300 to 1 ⁇ m. That is, the difference in film thickness between the insulating film in the region where the stacked portion 56 is formed and the insulating film in the region where the stacked portion 56 is not formed (the thickness of the stacked portion 56) is preferably about 300 to 1 ⁇ m. . As a result, it is possible to more effectively reduce the cross capacitance generated by the intersection between the main wiring and the branch wiring.
  • the insulating film 54 may be made of an insulating film such as SiNx (silicon nitride film), SiO 2 (silicon dioxide), or SOG film.
  • the stacked portion 56 formed in the upper layer of the insulating film 54 may be formed of the same insulating film material as the insulating film 54.
  • the insulating film 54 is formed to be thick as a whole, including the thickness at which the stacked portion 56 is to be formed. Then, the insulating material that becomes the insulating film 54 of an unnecessary film thickness is removed from the insulating material that becomes the insulating film 54 other than the formation region of the stacked portion 56 by etching (stacked portion forming step). As described above, the stacked portion 56 can be formed on the insulating film 54.
  • an etching mask is increased as compared with the case where the stacked portion 56 is not formed in the insulating film 54.
  • the insulating film in the region where each of the main wirings 51b, 51c, 51d, which is the formation region of the stacked portion 56, and each of the branch wirings 52a, 52b, 52c intersect can be formed in a single layer structure.
  • the insulating film 54 and the laminated portion 56 from the same insulating material, it is not necessary to prepare an insulating material different from the insulating film 54 in order to constitute the laminated portion 56, and the material cost is reduced. Improvement can be suppressed.
  • the stacked portion 56 formed on the upper layer of the insulating film 54 may be formed of an insulating material different from that of the insulating film 54.
  • the stacked portion 56 is formed by patterning a SiO 2 (silicon dioxide) or SOG film in a region where the stacked portion 56 is formed (stacked portion forming step).
  • the insulating film in the region where each of the trunk wirings 51b, 51c, 51d, which is the formation region of the stacked portion 56, and each of the branch wirings 52a, 52b, 52c may have a two-layer structure.
  • the degree of freedom in selecting the insulating material to be selected for reducing the cross capacitance can be improved. it can.
  • the insulating film 54 and the stacked portion 56 may be formed of the same material by patterning an insulating material of the same material as the insulating film 54 to form the stacked portion 56.
  • the cross capacitance generated in the region where the main wirings 51b, 51c, 51d and the branch wirings 52a, 52b, 52c intersect can be reduced. it can.
  • cross capacitance is generated, and it is possible to suppress the dullness of the waveforms of the signals output from the trunk lines 51b, 51c, and 51d and the branch lines 52a, 52b, and 52c, so that the trunk lines 51b, 51c, and 51d , And the reliability of signals output from the branch wirings 52a, 52b, and 52c.
  • a signal with less waveform dullness and a power source are input to the drive circuit 55 from the branch wirings 52a, 52b, and 52c. Since the drive circuit 55 is supplied with a signal with less waveform dullness and a power source, the drive circuit 55 displays a gate output with less dullness through the internal transistor from the gate bus line GL1. The data can be output to the area 2a.
  • FIG. 4 is an equivalent circuit of the drive circuit 55. As shown in FIG. 4, a signal such as a clock signal is input at the timing when the transistor in the drive circuit 55 is ON. If the input signal is dull, the waveform shape of the gate output output from the drive circuit 55 will be dull.
  • FIG. 5 shows a configuration of the wiring structure 100 in which the laminated portion 56 is not provided on the insulating film 54 in a region where the trunk wirings 51b, 51c, and 51d intersect with the branch wirings 52a, 52b, and 52c, respectively. It is sectional drawing.
  • the difference between the wiring structure 100 and the wiring structure 50 is that the laminated portion 56 is not provided on the insulating film 54 of the wiring structure 100, and the insulating film is configured only from the insulating film 54 having a uniform thickness. It is. Since others are the same, the same member number is attached
  • FIG. 6 shows a clock waveform output from the drive circuit 55 as a gate output.
  • the clock waveform a in FIG. 6 is a clock waveform output from the drive circuit 55 when the wiring structure 50 is used for the wiring of the gate driver 5a as described above. 6 is a clock waveform output from the drive circuit 55 when the wiring structure 100 is used instead of the wiring structure 50 for the wiring of the gate driver 5a.
  • the waveform dullness of the clock waveform a is reduced.
  • the wiring structure, the number of drive circuits, the number of trunk wirings and branch wirings can be variously configured in addition to the above description.
  • FIG. 7 and 8 are modifications of the configuration to which the wiring structure 50 is applied.
  • FIG. 7 is a plan view showing a first modification of the wiring configuration to which the wiring structure 50 of the present embodiment is applied.
  • FIG. 8 is a plan view illustrating a second modification of the wiring configuration to which the wiring structure 50 of the present embodiment is applied.
  • the trunk wirings 51-1a, 51-2a, and 51-3a are juxtaposed in parallel with each other.
  • One end of the branch wiring 52a is connected to the trunk wiring 51-1a via the contact hole 53a, and the other end is connected to the input terminal VSS of the drive circuit 55.
  • FIG. 8 shows a configuration in which a plurality of drive circuits are connected in series.
  • a drive circuit 55a is arranged between the trunk wirings 51-1a, 51-2a, and 51-3a and the trunk wirings 51b, 51c, and 51d.
  • the trunk lines 51-1a, 51-2a, and 51-3a that are electrically connected to each other are connected to the input terminal VSS1 of the drive circuit 55a via the 51-3a.
  • One terminal of the branch wiring 52a is connected to the output terminal VSS2 of the drive circuit 55a, and the other terminal is connected to the input terminal VSS3 of the drive circuit 55b.
  • One terminal of the branch wiring 52b is connected to the output terminal CKA1 of the drive circuit 55a, and is connected to the intersecting trunk wiring 51b via the contact hole 53b, and the other terminal is the input terminal CKA2 of the drive circuit 55b.
  • One terminal of the branch wiring 52c is connected to the output terminal CKB1 of the driving circuit 55a, and is connected to the intersecting trunk wiring 51c via the contact hole 53c, and the other terminal is the input terminal CKB2 of the driving circuit 55b.
  • One terminal of the branch wiring 52d is connected via the contact hole 53d, and the other terminal is connected to the input terminal CKC of the drive circuit 55.
  • the output terminal GOUT of the drive circuit 55b is connected to the gate bus line GL1.
  • the wiring structure 50 can be applied to various monolithic circuits formed in the gate driver 5a, the gate driver 5b, the source driver 6 and the like. According to such a wiring structure 50, the dullness of the waveform of the drive signal supplied to the drive circuit 55 and the drive circuit 55b can be reduced, so that a plurality of drive circuits are provided around the display area 2a. The drive circuit can be densified.
  • the wiring structure 50 can be applied to the intersection of the source bus line SL and the gate bus line GL in the display area 2a shown in FIG.
  • the source bus line SL and the gate bus line GL formed via an insulating film may be either an upper layer or a lower layer.
  • the wiring structure 50 has the following structure. Can be expressed as follows.
  • the wiring structure 50 includes a plurality of gate bus lines GL disposed on the glass substrate 58 and an insulating film (not shown) that is an upper layer of the glass substrate 58 and covers the plurality of gate bus lines GL. And a plurality of source bus lines SL arranged above the insulating film and intersecting at least one of the plurality of gate bus lines GL via the insulating film.
  • the wiring structure 50 is an upper layer of the insulating film, and in the region where at least the plurality of gate bus lines GL and the plurality of source bus lines SL intersect each other, a stacked portion 56 made of an insulating material is formed.
  • each of the plurality of source bus lines SL of the wiring structure 50 is configured to intersect with each of the plurality of gate bus lines GL via the insulating film and the stacked portion 56.
  • the cross capacitance generated in the region where the source bus line SL and the gate bus line GL intersect can be suppressed.
  • the capacity can be reduced.
  • the drive circuit 55 can be reduced in size, and the panel frame area (gate drivers 5a and 5b, source driver 6 which is the peripheral part of the display area 2a is arranged. Area) can be reduced.
  • the wiring structure 50 is It can be expressed as follows.
  • the wiring structure 50 includes a plurality of source bus lines SL disposed on the glass substrate 58 and an insulating film (not shown) that is an upper layer of the glass substrate 58 and covers the plurality of source bus lines SL. And a plurality of gate bus lines GL arranged on the insulating film and intersecting at least one of the plurality of source bus lines SL via the insulating film.
  • a laminated portion 56 made of an insulating material is provided in a region above the insulating film and intersecting at least the plurality of source bus lines SL and the plurality of gate bus lines GL. Is formed.
  • Each of the plurality of gate bus lines GL of the wiring structure 50 is configured to intersect with each of the plurality of source bus lines SL via the insulating film and the stacked portion 56.
  • the wiring structure of the present invention includes a plurality of first wirings arranged on a substrate and an upper layer of the substrate, wherein the plurality of first wirings are arranged.
  • An insulating film formed so as to cover, and a second wiring that is an upper layer of the insulating film and is arranged to intersect with at least one of the plurality of first wirings via the insulating film.
  • a stacked portion made of an insulating material is formed at least in a region above the insulating film, where at least the first wiring and the second wiring intersect with each other. It is characterized in that it intersects with the first wiring via the film and the laminated portion.
  • a method for manufacturing a wiring structure includes a first wiring forming step of patterning a plurality of first wirings on a substrate, and the first wiring formed in the first wiring forming step.
  • a second wiring forming step of patterning the second wiring so as to intersect the first wiring is
  • a laminated portion made of the insulating film material is provided in addition to the insulating film. Yes.
  • the second wiring crosses the first wiring through the insulating film and the stacked portion. That is, the thickness of the insulating material in the region where the first wiring and the second wiring intersect is formed thicker than the thickness of the other regions.
  • a wiring structure includes a display driving circuit monolithically formed on a substrate, and a plurality of second driving circuits disposed on the substrate and supplying driving signals to the driving circuit.
  • One wiring, an upper layer of the substrate and covering the plurality of first wirings, and an upper layer of the insulating film, the plurality of first It is connected to at least one of the wirings through a contact hole formed in the insulating film, and serves as an input wiring for a predetermined driving signal to the driving circuit, and the plurality of first wirings
  • a stack of materials is formed Cage, the second wiring through the insulating film and the laminated portion, is characterized in that intersects with the first wiring.
  • the laminated portion made of the insulating material is formed in the region where the first wiring and the second wiring intersect, the region where the first wiring and the second wiring intersect.
  • the generated cross capacitance can be reduced.
  • the insulating film and the stacked portion are preferably made of different insulating materials.
  • an insulating material different from that of the insulating film can be configured as a laminated portion in order to reduce cross capacitance generated when the first wiring and the second wiring intersect. For this reason, the freedom degree of selection of the insulating material selected in order to reduce the said cross capacity can be improved.
  • the insulating film and the stacked portion are preferably made of the same insulating material.
  • the stacked portion can be formed of the same insulating material as the insulating film, it is not necessary to prepare an insulating material for forming the stacked portion, and the increase in material cost is suppressed. be able to.
  • the first wiring of the wiring structure is formed of a gate bus line metal
  • the second wiring is formed of a source bus line metal, or the first wiring is a source bus line metal.
  • the second wiring is formed of a gate bus line metal.
  • the first wiring and the second wiring can be configured for a material generally used for TFT elements, for example.
  • a wiring board of the present invention includes the above wiring structure, and a display region in which TFT elements are formed in a matrix is arranged.
  • the one end of the second wiring is connected to the first wiring, and the other end of the second wiring is connected to a gate bus line connected to the TFT element. It is preferable that
  • the wiring structure can be provided in a region adjacent to the display region, which is a wiring substrate on which a display region in which TFT elements are formed in a matrix is arranged.
  • a wiring board with a small cross capacitance can be configured by providing a plurality of wirings and various branch wirings branched from the wirings in a region adjacent to the display region. Therefore, a circuit for driving the TFT element can be arranged in a region adjacent to the display region while suppressing the generation of cross capacitance.
  • the liquid crystal display panel of the present invention has a counter electrode disposed in a region facing the TFT element of the wiring substrate and the wiring substrate, and is disposed to face the wiring substrate through a liquid crystal layer.
  • the counter substrate is preferably provided.
  • the present invention increases the film thickness of the insulating film formed between the wirings crossing each other, so that the present invention can be applied to a display panel having a wiring structure arranged so as to cross through the insulating film.

Abstract

A wiring structure (50) comprises a plurality of main wires (51b, 51c, 51d) arranged on a glass substrate (58), an insulation layer (54) provided on the glass substrate (58) to cover the main wires (51b, 51c, 51d), and branch wires (52a, 52b, 52c) provided on the insulation layer (54) to intersect any of the main wires (51b, 51c, 51d) through the insulation layer (54). A laminate portion (56) made of an insulation material is formed on the insulation layer (54) at least in an area in which the branch wires (52a, 52b, 52c) intersect the main wires (51b, 51c, 51d), and the branch wires (52a, 52b, 52c) intersect the main wires (51b, 51c, 51d) through the insulation film (54) and the laminate portion (56). Consequently, the reliability of an output signal can be enhanced.

Description

配線構造、配線基板、液晶表示パネル、及び配線構造の製造方法Wiring structure, wiring board, liquid crystal display panel, and manufacturing method of wiring structure
　本発明は、絶縁膜を介して互いに交差して配される配線構造等に関する。 The present invention relates to a wiring structure and the like arranged so as to cross each other through an insulating film.
　近年、液晶パネル上に、アモルファスシリコン等の非晶質シリコンでゲートドライバを形成し、コスト削減を図るゲートモノリシック化が進められている。ゲートモノリシックは、ゲートドライバレス、パネル内蔵ゲートドライバ、ゲートインパネルなどとも称される。例えば、特許文献１には、ゲートモノリシックにより、シフトレジスタを構成した例が開示されている。特許文献１の構成について、図９を用いて説明する。 In recent years, gate monolithics have been promoted to reduce costs by forming a gate driver with amorphous silicon such as amorphous silicon on a liquid crystal panel. Gate monolithic is also referred to as a gate driverless, panel built-in gate driver, gate-in panel, or the like. For example, Patent Document 1 discloses an example in which a shift register is configured by gate monolithic. The configuration of Patent Document 1 will be described with reference to FIG.
　図９は、従来の配線構造を備える液晶表示装置の構成を表す。 FIG. 9 shows a configuration of a liquid crystal display device having a conventional wiring structure.
　図９に示すように、従来の配線構造は、ゲート駆動回路領域に配置された複数の主配線５５０のそれぞれと、コンタクトホール５７０で主配線５５０のそれぞれと接続され、主配線５５０と交差して分岐配線５６０が形成されている。 As shown in FIG. 9, the conventional wiring structure is connected to each of the plurality of main wirings 550 arranged in the gate driving circuit region and each of the main wirings 550 through the contact hole 570, and crosses the main wiring 550. A branch wiring 560 is formed.
日本国公表特許公報「特表２００５－５２７８５６号公報（２００５年９月１５日公表）」Japanese Patent Gazette “Special Table 2005-527856 (published on September 15, 2005)” 日本国公開特許公報「特開２００６－２５９６９１号公報（２００６年９月２８日公開）」Japanese Patent Publication “Japanese Patent Laid-Open No. 2006-259691 (published on September 28, 2006)” 日本国公開特許公報「特開平９－１７９１３０号公報（１９９７年７月１１日公開）」Japanese Patent Publication “JP 9-179130 A (published July 11, 1997)”
　しかしながら、図９の構成では、主配線５５０から分岐する分岐配線５６０は、複数配されている主配線５５０と交差して配されることになる。このように、主配線５５０と、分岐配線５６０とが交差する領域では容量が形成される（以下、クロス容量と称する）。そして、クロス容量が形成されると、主配線５５０や、分岐配線５６０から出力される信号の波形形状に鈍りが生じることになる。 However, in the configuration of FIG. 9, the branch wiring 560 branched from the main wiring 550 is arranged to intersect with the plurality of main wirings 550. Thus, a capacitance is formed in a region where the main wiring 550 and the branch wiring 560 intersect (hereinafter referred to as a cross capacitance). When the cross capacitance is formed, the waveform shape of a signal output from the main wiring 550 or the branch wiring 560 becomes dull.
　特許文献１の技術では、この出力信号の波形の鈍りについて何ら考慮されていない。このため分岐配線５６０から出力される信号の波形形状に鈍りが生じ、分岐配線５６０の信号の出力先の駆動回路の動作マージンを低下させるなどにより、画像の表示品質を低下させる原因となる。 In the technique of Patent Document 1, no consideration is given to the dullness of the waveform of the output signal. For this reason, the waveform shape of the signal output from the branch wiring 560 becomes dull, which causes a reduction in the display quality of the image, for example, by reducing the operation margin of the drive circuit to which the signal of the branch wiring 560 is output.
　また、特許文献２、３に開示された技術も配線交差によるクロス容量について考慮されておらず、互いに交差する配線からの出力信号の信頼性が低下するという課題が生じる。 Also, the techniques disclosed in Patent Documents 2 and 3 do not take into account the cross capacitance due to the wiring crossing, and there arises a problem that the reliability of the output signals from the wirings crossing each other is lowered.
　本発明は、上記の問題点に鑑みてなされたものであり、その目的は、出力信号の信頼性が高い配線構造を実現することにある。 The present invention has been made in view of the above-described problems, and an object thereof is to realize a wiring structure with high output signal reliability.
　上記の課題を解決するために、本発明の配線構造は、基板上に配されている複数の第１配線と、上記基板の上層であって、上記複数の第１配線を覆って形成されている絶縁膜と、上記絶縁膜の上層であって、上記絶縁膜を介して、上記複数の第１配線の少なくとも何れか１つと交差して配されている第２配線とを備え、上記絶縁膜の上層であって、少なくとも上記第１配線と、上記第２配線とが交差する領域には、絶縁材料からなる積層部が形成されており、上記第２配線は、上記絶縁膜及び上記積層部を介して、上記第１配線と交差していることを特徴としている。 In order to solve the above problems, a wiring structure of the present invention is formed by covering a plurality of first wirings disposed on a substrate and an upper layer of the substrate, covering the plurality of first wirings. An insulating film, and a second wiring which is an upper layer of the insulating film and is arranged so as to intersect at least one of the plurality of first wirings with the insulating film interposed therebetween, A laminated portion made of an insulating material is formed at least in a region where the first wiring and the second wiring intersect, and the second wiring includes the insulating film and the laminated portion. This is characterized in that it intersects with the first wiring.
　上記課題を解決するために、本発明の配線構造の製造方法は、基板上に複数の第１配線をパターニングする第１配線形成工程と、上記第１配線形成工程で形成された上記第１配線を覆って絶縁膜を形成する絶縁膜形成工程と、上記絶縁膜形成工程で形成された上記絶縁膜の上層であって、上記絶縁膜を介して上記第１配線と、当該第１配線とは異なる第２配線とを交差させる領域に、絶縁材料からなる積層部を形成する積層部形成工程と、上記積層部形成工程で形成した積層部と、上記絶縁膜形成工程で形成した絶縁膜とを介して、上記第１配線と交差するように上記第２配線をパターニングする第２配線形成工程とを含むことを特徴としている。 In order to solve the above problems, a method for manufacturing a wiring structure according to the present invention includes a first wiring forming step of patterning a plurality of first wirings on a substrate, and the first wiring formed in the first wiring forming step. An insulating film forming step of forming an insulating film so as to cover the upper surface of the insulating film, and an upper layer of the insulating film formed in the insulating film forming step, wherein the first wiring and the first wiring are interposed through the insulating film, A laminated portion forming step of forming a laminated portion made of an insulating material in a region where different second wirings intersect, a laminated portion formed in the laminated portion forming step, and an insulating film formed in the insulating film forming step And a second wiring forming step of patterning the second wiring so as to intersect the first wiring.
　上記構成によると、上記絶縁膜を介して、互いに交差する第１配線と、第２配線とが交差する領域には、上記絶縁膜に加えて、上記絶縁膜材料からなる積層部が設けられている。そして、上記第２配線は、上記絶縁膜及び上記積層部を介して、上記第１配線と交差している。つまり、上記第１配線と、上記第２配線とが交差する領域の絶縁材料の膜厚は、それ以外の領域の膜厚と比較して、厚く形成されている。 According to the above configuration, in the region where the first wiring and the second wiring intersect with each other via the insulating film, a laminated portion made of the insulating film material is provided in addition to the insulating film. Yes. The second wiring crosses the first wiring through the insulating film and the stacked portion. That is, the thickness of the insulating material in the region where the first wiring and the second wiring intersect is formed thicker than the thickness of the other regions.
　このため、上記第１配線と、第２配線とが交差する領域に発生する容量（クロス容量）を低減することができる。これにより、クロス容量が発生し、上記第１配線、及び上記第２配線から出力される信号の波形が鈍ることを抑制することができるので、第１配線、及び第２配線から出力される信号の信頼性を向上させることができる。 For this reason, it is possible to reduce the capacitance (cross capacitance) generated in the region where the first wiring and the second wiring intersect. As a result, cross capacitance is generated, and it is possible to suppress a dull waveform of signals output from the first wiring and the second wiring. Therefore, signals output from the first wiring and the second wiring. Reliability can be improved.
　上記課題を解決するために、本発明の配線構造は、基板にモノリシックに作り込まれた表示の駆動回路と、基板上に配されるとともに上記駆動回路に駆動用の信号を供給する複数の第１配線と、上記基板の上層であって、上記複数の第１配線を覆って形成されている絶縁膜と、上記絶縁膜の上層であって、上記絶縁膜を介して、上記複数の第１配線の少なくとも何れか１つと上記絶縁膜に形成されたコンタクトホールを介して接続されて上記駆動回路への所定の上記駆動用の信号の入力配線となっているとともに、上記複数の第１配線の他の少なくとも何れか１つと交差して配されている第２配線とを備え、上記絶縁膜の上層であって、少なくとも上記第１配線と、上記第２配線とが交差する領域には、絶縁材料からなる積層部が形成されており、上記第２配線は、上記絶縁膜及び上記積層部を介して、上記第１配線と交差していることを特徴としている。 In order to solve the above-described problems, a wiring structure according to the present invention includes a display driving circuit monolithically formed on a substrate, and a plurality of second driving circuits disposed on the substrate and supplying driving signals to the driving circuit. One wiring, an upper layer of the substrate and covering the plurality of first wirings, and an upper layer of the insulating film, the plurality of first It is connected to at least one of the wirings through a contact hole formed in the insulating film, and serves as an input wiring for a predetermined driving signal to the driving circuit, and the plurality of first wirings A second wiring arranged to intersect with at least one of the other, and is an upper layer of the insulating film, wherein at least an area where the first wiring and the second wiring intersect is insulated A stack of materials is formed Cage, the second wiring through the insulating film and the laminated portion, is characterized in that intersects with the first wiring.
　上記構成によると、上記第１配線と、第２配線とが交差する領域に発生するクロス容量を低減することができる。これにより、クロス容量の発生によって上記第２配線から上記駆動回路に供給される駆動用の信号の波形の形状が鈍ることを防止できるので、信頼性が高い駆動用の信号を駆動回路に供給することができる。 According to the above configuration, it is possible to reduce the cross capacitance generated in the region where the first wiring and the second wiring intersect. As a result, it is possible to prevent the waveform of the driving signal supplied from the second wiring to the driving circuit from being dull due to the generation of the cross capacitance, so that a highly reliable driving signal is supplied to the driving circuit. be able to.
　本発明の配線構造は、基板上に配されている複数の第１配線と、上記基板の上層であって、上記複数の第１配線を覆って形成されている絶縁膜と、上記絶縁膜の上層であって、上記絶縁膜を介して、上記複数の第１配線の少なくとも何れか１つと交差して配されている第２配線とを備え、上記絶縁膜の上層であって、少なくとも上記第１配線と、上記第２配線とが交差する領域には、絶縁材料からなる積層部が形成されており、上記第２配線は、上記絶縁膜及び上記積層部を介して、上記第１配線と交差している構成である。 The wiring structure of the present invention includes a plurality of first wirings disposed on a substrate, an insulating film formed on the substrate and covering the plurality of first wirings, and the insulating film. An upper layer, and a second wiring that intersects with at least one of the plurality of first wirings via the insulating film, and is an upper layer of the insulating film and includes at least the first wiring A laminated portion made of an insulating material is formed in a region where one wiring and the second wiring intersect, and the second wiring is connected to the first wiring via the insulating film and the laminated portion. It is a configuration that intersects.
　本発明の配線構造は、基板にモノリシックに作り込まれた表示の駆動回路と、基板上に配されるとともに上記駆動回路に駆動用の信号を供給する複数の第１配線と、上記基板の上層であって、上記複数の第１配線を覆って形成されている絶縁膜と、上記絶縁膜の上層であって、上記絶縁膜を介して、上記複数の第１配線の少なくとも何れか１つと上記絶縁膜に形成されたコンタクトホールを介して接続されて上記駆動回路への所定の上記駆動用の信号の入力配線となっているとともに、上記複数の第１配線の他の少なくとも何れか１つと交差して配されている第２配線とを備え、上記絶縁膜の上層であって、少なくとも上記第１配線と、上記第２配線とが交差する領域には、絶縁材料からなる積層部が形成されており、上記第２配線は、上記絶縁膜及び上記積層部を介して、上記第１配線と交差している構成である。 The wiring structure of the present invention includes a display driving circuit monolithically formed on a substrate, a plurality of first wirings arranged on the substrate and supplying a driving signal to the driving circuit, and an upper layer of the substrate An insulating film formed so as to cover the plurality of first wirings, and an upper layer of the insulating film, wherein at least one of the plurality of first wirings is interposed through the insulating film, and It is connected via a contact hole formed in the insulating film and serves as an input wiring for a predetermined driving signal to the driving circuit, and intersects with at least one of the other first wirings. A laminated portion made of an insulating material is formed in an upper layer of the insulating film and at least in a region where the first wiring and the second wiring intersect with each other. The second wiring is Insulating film and through the laminated portion, it is configured to intersect with the first wiring.
　本発明の配線構造の製造方法は、基板上に複数の第１配線をパターニングする第１配線形成工程と、上記第１配線形成工程で形成された上記第１配線を覆って絶縁膜を形成する絶縁膜形成工程と、上記絶縁膜形成工程で形成された上記絶縁膜の上層であって、上記絶縁膜を介して上記第１配線と、当該第１配線とは異なる第２配線とを交差させる領域に、絶縁材料からなる積層部を形成する積層部形成工程と、上記積層部形成工程で形成した積層部と、上記絶縁膜形成工程で形成した絶縁膜とを介して、上記第１配線と交差するように上記第２配線をパターニングする第２配線形成工程とを含む。 In the method for manufacturing a wiring structure according to the present invention, a first wiring forming step of patterning a plurality of first wirings on a substrate, and an insulating film is formed to cover the first wiring formed in the first wiring forming step. An insulating film forming step and an upper layer of the insulating film formed in the insulating film forming step, wherein the first wiring and a second wiring different from the first wiring are crossed through the insulating film. The first wiring is formed through a stacked portion forming step of forming a stacked portion made of an insulating material in the region, the stacked portion formed in the stacked portion forming step, and the insulating film formed in the insulating film forming step. A second wiring forming step of patterning the second wiring so as to intersect.
　これにより、第１配線、及び第２配線から出力される信号の信頼性を向上させる効果を奏する。 This produces an effect of improving the reliability of signals output from the first wiring and the second wiring.
図２のＡ－Ａ’線矢視断面図である。FIG. 3 is a cross-sectional view taken along line A-A ′ in FIG. 2. 本発明の表示パネルの配線構造の構成を表す平面図である。It is a top view showing the structure of the wiring structure of the display panel of this invention. 本発明の表示パネルの配線構造を適用する液晶表示装置の構成を表す概略図である。It is the schematic showing the structure of the liquid crystal display device to which the wiring structure of the display panel of this invention is applied. 本発明の表示パネルの配線構造の配線と接続される駆動回路の等価回路図である。It is an equivalent circuit diagram of the drive circuit connected with the wiring of the wiring structure of the display panel of this invention. 一般的な配線構造の構成を表す断面図である。It is sectional drawing showing the structure of a general wiring structure. 本発明の表示パネルの配線構造、及び一般的な配線構造の配線と接続される駆動回路から出力されるクロック波形を表す図である。It is a figure showing the clock waveform output from the drive circuit connected with the wiring structure of the display panel of this invention, and the wiring of a general wiring structure. 本発明の表示パネルの配線構造を適用する配線の構造の第１の変形例を表す平面図である。It is a top view showing the 1st modification of the structure of the wiring which applies the wiring structure of the display panel of this invention. 本発明の表示パネルの配線構造を適用する配線の構造の第２の変形例を表す平面図である。It is a top view showing the 2nd modification of the structure of the wiring which applies the wiring structure of the display panel of this invention. 従来技術を表す平面図である。It is a top view showing a prior art.
　〔実施の形態１〕
　以下、本発明の実施の形態について、詳細に説明する。 [Embodiment 1]
Hereinafter, embodiments of the present invention will be described in detail.
　（全体構成）
　図３に、本実施形態に係る表示装置である液晶表示装置１の構成を示す。 (overall structure)
FIG. 3 shows a configuration of a liquid crystal display device 1 that is a display device according to the present embodiment.
　液晶表示装置１は、表示パネル（液晶表示パネル）２、フレキシブルプリント基板３、および、コントロール基板４を備えている。 The liquid crystal display device 1 includes a display panel (liquid crystal display panel) 2, a flexible printed circuit board 3, and a control board 4.
　表示パネル２は、ガラス基板（基板）５８上にアモルファスシリコンや多結晶シリコン、ＣＧシリコン、微結晶シリコンなどを用いて表示領域２ａ、複数のゲートバスラインＧＬ…、複数のソースバスラインＳＬ…、および、ゲートドライバ５ａ・５ｂが作り込まれたアクティブマトリクス型の配線基板と、液晶層を介して、配線基板と対向配置される対向基板とを備える表示パネルである。表示領域２ａは、複数の絵素ＰＩＸ…がマトリクス状に配置された領域である。絵素ＰＩＸは、絵素ＰＩＸの選択素子であるＴＦＴ（ＴＦＴ素子）２１、液晶容量ＣＬ、および、補助容量Ｃｓを備えている。ＴＦＴ２１のゲートはゲートバスラインＧＬに接続されており、ＴＦＴ２１のソースはソースバスラインＳＬに接続されている。液晶容量ＣＬおよび補助容量ＣｓはＴＦＴ２１のドレインに接続されている。また、対向基板上であって、液晶層を介してＴＦＴ２１と対向する領域には対向電極が配置されている。 The display panel 2 includes a display region 2a, a plurality of gate bus lines GL, a plurality of source bus lines SL,... Using amorphous silicon, polycrystalline silicon, CG silicon, microcrystalline silicon, or the like on a glass substrate (substrate) 58. In addition, the display panel includes an active matrix wiring substrate in which the gate drivers 5a and 5b are formed, and a counter substrate disposed to face the wiring substrate through a liquid crystal layer. The display area 2a is an area in which a plurality of picture elements PIX ... are arranged in a matrix. The picture element PIX includes a TFT (TFT element) 21 which is a selection element of the picture element PIX, a liquid crystal capacitor CL, and an auxiliary capacitor Cs. The gate of the TFT 21 is connected to the gate bus line GL, and the source of the TFT 21 is connected to the source bus line SL. The liquid crystal capacitor CL and the auxiliary capacitor Cs are connected to the drain of the TFT 21. A counter electrode is disposed on the counter substrate in a region facing the TFT 21 via the liquid crystal layer.
　複数のゲートバスラインＧＬ…は、ゲートバスラインＧＬ１・ＧＬ２・ＧＬ３・…・ＧＬｎからなる。そして、そのうち１つおきに配置されたゲートバスラインＧＬ１・ＧＬ３・ＧＬ５…からなる第１のグループのゲートバスラインＧＬ…はゲートドライバ５ａの出力に接続されており、残りの１つおきに配置されたゲートバスラインＧＬ２・ＧＬ４・ＧＬ６…からなる第２のグループのゲートバスラインＧＬ…はゲートドライバ５ｂの出力に接続されている。 The plurality of gate bus lines GL are composed of gate bus lines GL1, GL2, GL3,. The first group of gate bus lines GL consisting of every other gate bus line GL1, GL3, GL5,... Is connected to the output of the gate driver 5a, and every other one is arranged. The second group of gate bus lines GL... Composed of the gate bus lines GL 2, GL 4, GL 6, etc. connected to the output of the gate driver 5 b.
　複数のソースバスラインＳＬ…は、ソースバスラインＳＬ１・ＳＬ２・ＳＬ３・…・ＳＬｍからなり、それぞれ後述するソースドライバ６の出力に接続されている。また、図示しないが、絵素ＰＩＸ…の各補助容量Ｃｓに補助容量電圧を与える補助容量配線が形成されている。 The plurality of source bus lines SL are composed of source bus lines SL1, SL2, SL3,..., SLm, and are connected to the output of the source driver 6 described later. Further, although not shown, auxiliary capacitance lines for applying an auxiliary capacitance voltage to the auxiliary capacitances Cs of the picture elements PIX... Are formed.
　ゲ－トドライバ５ａは、表示パネル２上で表示領域２ａに対してゲートバスラインＧＬ…の延びる方向の一方側に隣接する領域に設けられており、第１のグループのゲートバスラインＧＬ１・ＧＬ３・ＧＬ５…のそれぞれに順次ゲートパルスを供給する。ゲ－トドライバ５ｂは、表示パネル２上で表示領域２ａに対してゲートバスラインＧＬ…の延びる方向の他方側に隣接する領域に設けられており、第２のグループのゲートバスラインＧＬ２・ＧＬ４・ＧＬ６…のそれぞれに順次ゲートパルスを供給する。これらのゲートドライバ５ａ・５ｂは表示パネル２に表示領域２ａとモノリシックに作り込まれており、ゲートモノリシック、ゲートドライバレス、パネル内蔵ゲートドライバ、ゲートインパネルなどと称されるゲートドライバは全てゲートドライバ５ａ・５ｂに含まれ得る。 The gate driver 5a is provided on the display panel 2 in a region adjacent to the display region 2a on one side in the direction in which the gate bus lines GL... Extend, and the first group of gate bus lines GL1 and GL3.・ Supply gate pulses to each of GL5. The gate driver 5b is provided in a region adjacent to the display region 2a on the other side of the display region 2a in the extending direction of the gate bus lines GL, and the second group of gate bus lines GL2 and GL4. -Gate pulses are sequentially supplied to each of GL6. These gate drivers 5a and 5b are built monolithically with the display area 2a in the display panel 2, and all gate drivers called gate monolithic, gate driverless, panel built-in gate drivers, gate-in panels, etc. are gate drivers. 5a and 5b.
　ここで、複数のゲートバスラインＧＬのそれぞれと、複数のソースバスラインＳＬのそれぞれとは、絶縁膜（不図示）を介して、表示領域２ａ内で交差している。なお、複数のゲートバスラインＧＬと、複数のソースバスラインＳＬとの配線の上下関係は特に限定されるものではなく、絵素ＰＩＸや、ＴＦＴ２１等の構成によって適宜、選択が可能である。 Here, each of the plurality of gate bus lines GL and each of the plurality of source bus lines SL intersect each other in the display region 2a via an insulating film (not shown). Note that the vertical relationship of wiring between the plurality of gate bus lines GL and the plurality of source bus lines SL is not particularly limited, and can be appropriately selected depending on the configuration of the picture elements PIX, the TFTs 21 and the like.
　フレキシブルプリント基板３は、ソースドライバ６を備えている。ソースドライバ６はソースバスラインＳＬ…のそれぞれにデータ信号を供給する。コントロール基板４はフレキシブルプリント基板３に接続されており、ゲートドライバ５ａ・５ｂおよびソースドライバ６に必要な信号や電源を供給する。コントロール基板４から出力されたゲートドライバ５ａ・５ｂへ供給する信号および電源は、フレキシブルプリント基板３を介して表示パネル２上からゲートドライバ５ａ・５ｂへ供給される。 The flexible printed circuit board 3 includes a source driver 6. The source driver 6 supplies a data signal to each of the source bus lines SL. The control board 4 is connected to the flexible printed circuit board 3 and supplies necessary signals and power to the gate drivers 5a and 5b and the source driver 6. Signals and power supplied from the control board 4 to the gate drivers 5a and 5b are supplied from the display panel 2 to the gate drivers 5a and 5b via the flexible printed board 3.
　（ゲートドライバ５ａ）
　次に、図１、図２を用い、本実施の形態の配線構造５０を適用するゲートドライバ５ａの構成について説明する。 (Gate driver 5a)
Next, the configuration of the gate driver 5a to which the wiring structure 50 of the present embodiment is applied will be described with reference to FIGS.
　図２は、ゲートドライバ５ａの要部を表す平面図である。図１は、図２のＡ－Ａ’線矢視断面図である。 FIG. 2 is a plan view showing the main part of the gate driver 5a. FIG. 1 is a cross-sectional view taken along line A-A ′ of FIG.
　ゲートドライバ５ａは、ガラス基板５８上に複数配された幹配線（第１配線）５１ａ・５１ｂ・５１ｃ・５１ｄと、幹配線５１ａ・５１ｂ・５１ｃから分岐され、一方の端部が幹配線５１ａ・５１ｂ・５１ｃの少なくとも何れか１つと接続され、他方の端子が駆動回路５５の入力側の端子と接続された分岐配線（第２配線）５２ａ・５２ｂ・５２ｃ・５２ｄと、分岐配線５２ａ・５２ｂ・５２ｃ・５２ｄと接続され、分岐配線５２ａ・５２ｂ・５２ｃのそれぞれから出力される信号や電源を、表示領域２ａに出力するための駆動回路５５とを備えている。 The gate driver 5a is branched from a plurality of trunk wirings (first wirings) 51a, 51b, 51c, 51d and the trunk wirings 51a, 51b, 51c arranged on the glass substrate 58, and one end portion of each of the gate wirings 5a, 51b, 51c. Branch wirings (second wirings) 52a, 52b, 52c, and 52d that are connected to at least one of 51b and 51c and the other terminal is connected to the input side terminal of the drive circuit 55, and branch wirings 52a, 52b, and 52c 52c and 52d, and a drive circuit 55 for outputting signals and power output from the branch lines 52a, 52b, and 52c to the display area 2a.
　そして、本実施の形態に係る配線構造５０は、例えば、ゲートドライバ５ａの配線の構造に適用することができる。 The wiring structure 50 according to the present embodiment can be applied to the wiring structure of the gate driver 5a, for example.
　配線構造５０は、ガラス基板５８上に配される複数の幹配線５１ｂ・５１ｃ・５１ｄと、上記ガラス基板の上層であって、幹配線５１ｂ・５１ｃ・５１ｄを覆って形成されている絶縁膜５４と、絶縁膜５４の上層であって、絶縁膜５４を介して、幹配線５１ｂ・５１ｃ・５１ｄの何れかと交差して配されている分岐配線５２ａ・５２ｂ・５２ｃとを含んで構成されている。 The wiring structure 50 includes a plurality of trunk wires 51b, 51c, and 51d disposed on the glass substrate 58, and an insulating film 54 that is an upper layer of the glass substrate and covers the trunk wires 51b, 51c, and 51d. And branch wirings 52 a, 52 b, and 52 c that are arranged on the insulating film 54 so as to intersect any of the trunk wirings 51 b, 51 c, and 51 d via the insulating film 54. .
　そして、配線構造５０は、絶縁膜５４の上層であって、少なくとも幹配線５１ｂ・５１ｃ・５１ｄと、分岐配線５２ａ・５２ｂ・５２ｃとが交差する領域には、絶縁材料からなる積層部５６が形成されている。また、配線構造５０の分岐配線５２ａ・５２ｂ・５２ｃは、絶縁膜５４及び積層部５６を介して、幹配線５１ｂ・５１ｃ・５１ｄと交差している構成である。 The wiring structure 50 is an upper layer of the insulating film 54, and a laminated portion 56 made of an insulating material is formed at least in a region where the trunk wirings 51b, 51c, 51d and the branch wirings 52a, 52b, 52c intersect. Has been. Further, the branch wirings 52 a, 52 b, and 52 c of the wiring structure 50 are configured to intersect with the trunk wirings 51 b, 51 c, and 51 d through the insulating film 54 and the laminated portion 56.
　そして、絶縁膜５４や、絶縁膜５４に対する絶縁材料の積層部分である積層部５６、及び各分岐配線（分岐配線５２ａ・５２ｂ・５２ｃ・５２ｄ）の上層には層間絶縁膜５７が形成されている。 An interlayer insulating film 57 is formed on the insulating film 54, the laminated portion 56 that is a laminated portion of the insulating material with respect to the insulating film 54, and the upper layers of the branch wirings (branch wirings 52 a, 52 b, 52 c, 52 d). .
　幹配線５１ａ・５１ｂ・５１ｃ・５１ｄは、ガラス基板５８上に配されているとともに、駆動回路５５に駆動用の信号を供給するものである。幹配線５１ａ・５１ｂ・５１ｃ・５１ｄが供給する駆動用の信号は、コントロール基板４から入力されてくるものであり、電源電圧ＶＳＳも含むものとする。 The trunk wirings 51 a, 51 b, 51 c, 51 d are arranged on the glass substrate 58 and supply driving signals to the driving circuit 55. The driving signals supplied by the trunk lines 51a, 51b, 51c, and 51d are input from the control board 4 and include the power supply voltage VSS.
　幹配線５１ａ・５１ｂ・５１ｃ・５１ｄは、ゲートバスライン用メタル、またはソースバスライン用メタルで形成されている。幹配線５１ａ・５１ｂ・５１ｃ・５１ｄは、例えば、幹配線５１ａ・５１ｂ・５１ｃ・５１ｄのそれぞれとするための配線材料をスパッタリング法によってガラス基板上に成膜し、この成膜した配線材料をフォトリソグラフィー法によってパターニングすることによりガラス基板上に形成される（第１配線形成工程）。 The trunk wirings 51a, 51b, 51c, and 51d are formed of gate bus line metal or source bus line metal. For the trunk wires 51a, 51b, 51c and 51d, for example, a wiring material for forming the trunk wires 51a, 51b, 51c and 51d is formed on a glass substrate by a sputtering method, and the formed wiring material is used as a photo It forms on a glass substrate by patterning by the lithography method (1st wiring formation process).
　ゲートバスライン用メタルは、例えば、Ｔａ（またはＴａＮ）、Ｔｉ（またはＴｉＮ）、Ａｌ（またはＡｌを主成分とする合金）、Ｍｏ（またはＭｏＮ）、Ｃｒを、それぞれ単層で、もしくは、それらのうちのいくつかの組み合わせによる積層構造で構成することができる。また、ソースバスライン用メタルは、例えば、ゲートメタルＧＭと同様の材料を用いることができ、Ｔａ（またはＴａＮ）、Ｔｉ（またはＴｉＮ）、Ａｌ（またはＡｌを主成分とする合金）、Ｍｏ（またはＭｏＮ）、Ｃｒを、それぞれ単層で、もしくは、それらのうちのいくつかの組み合わせによる積層構造で構成することができる。 The metal for the gate bus line is, for example, Ta (or TaN), Ti (or TiN), Al (or an alloy containing Al as a main component), Mo (or MoN), and Cr, each in a single layer, or those It can comprise with the laminated structure by some combination of these. The source bus line metal can be made of the same material as that of the gate metal GM, for example, Ta (or TaN), Ti (or TiN), Al (or an alloy containing Al as a main component), Mo ( Or MoN) and Cr can each be formed of a single layer or a laminated structure of some combination thereof.
　分岐配線５２ａ・５２ｂ・５２ｃ・５２ｄは、幹配線５１ａ・５１ｂ・５１ｃ・５１ｄに伝送されている信号や、電源などを駆動回路５５へ出力するために、幹配線５１ａ・５１ｂ・５１ｃ・５１ｄのそれぞれから分岐された配線である。 The branch wirings 52 a, 52 b, 52 c, and 52 d are connected to the trunk wirings 51 a, 51 b, 51 c, and 51 d to output signals transmitted to the trunk wirings 51 a, 51 b, 51 c, and 51 d, power supplies, and the like to the drive circuit 55. Wiring branched from each.
　分岐配線５２ａ・５２ｂ・５２ｃのそれぞれは、絶縁膜５４、及び絶縁膜５４の上層に積層された積層部５６とを介して、少なくとも１本の幹配線（本実施の形態では幹配線５１ｄ）と交差して配されている。分岐配線５２ａ・５２ｂ・５２ｃ・５２ｄは、絶縁膜５４、及び積層部５６が形成されてから、その上に形成される。例えば、スパッタリング法によって分岐配線５２ａ・５２ｂ・５２ｃ・５２ｄのそれぞれとするための配線材料を絶縁膜５４、及び積層部５６上に成膜し、この成膜した配線材料をフォトリソグラフィー法によってパターニングすることにより絶縁膜５４、及び積層部５６上に、分岐配線５２ａ・５２ｂ・５２ｃ・５２ｄを形成する（第２配線形成工程）。 Each of the branch wirings 52a, 52b, and 52c is connected to at least one trunk wiring (the trunk wiring 51d in the present embodiment) via the insulating film 54 and the stacked portion 56 stacked on the insulating film 54. Crossed. The branch wirings 52a, 52b, 52c, and 52d are formed on the insulating film 54 and the stacked portion 56 after the insulating film 54 and the stacked portion 56 are formed. For example, a wiring material for forming each of the branch wirings 52a, 52b, 52c, and 52d is formed on the insulating film 54 and the laminated portion 56 by sputtering, and the formed wiring material is patterned by photolithography. As a result, the branch wirings 52a, 52b, 52c, and 52d are formed on the insulating film 54 and the stacked portion 56 (second wiring forming step).
　分岐配線５２ａの一方の端部は、絶縁膜５４に形成されたコンタクトホール５３ａを介して幹配線５１ａと接続されており、分岐配線５２ａの他方の端部は駆動回路５５の入力端子ＶＳＳと接続されている。分岐配線５２ａは、絶縁膜５４及び積層部５６を介して、幹配線５１ｂ・５１ｃ・５１ｄと交差して配されている。 One end of the branch wiring 52 a is connected to the trunk wiring 51 a through a contact hole 53 a formed in the insulating film 54, and the other end of the branch wiring 52 a is connected to the input terminal VSS of the drive circuit 55. Has been. The branch wiring 52 a is arranged so as to intersect with the trunk wirings 51 b, 51 c, 51 d via the insulating film 54 and the stacked portion 56.
　分岐配線５２ｂの一方の端部は、絶縁膜５４に形成されたコンタクトホール５３ｂを介して幹配線５１ｂと接続されており、分岐配線５２ｂの他方の端部は駆動回路５５の入力端子ＣＫＡと接続されている。分岐配線５２ｂは、絶縁膜５４及び積層部５６を介して、幹配線５１ｃ・５１ｄと交差して配されている。 One end of the branch wiring 52 b is connected to the trunk wiring 51 b through a contact hole 53 b formed in the insulating film 54, and the other end of the branch wiring 52 b is connected to the input terminal CKA of the drive circuit 55. Has been. The branch wiring 52 b is arranged so as to intersect with the trunk wirings 51 c and 51 d via the insulating film 54 and the stacked portion 56.
　分岐配線５２ｃの一方の端部は、絶縁膜５４に形成されたコンタクトホール５３ｃを介して幹配線５１ｃと接続されており、分岐配線５２ｂの他方の端部は駆動回路５５の入力端子ＣＫＢと接続されている。分岐配線５２ｃは、絶縁膜５４及び積層部５６を介して、幹配線５１ｄと交差して配されている。 One end of the branch wiring 52 c is connected to the trunk wiring 51 c through a contact hole 53 c formed in the insulating film 54, and the other end of the branch wiring 52 b is connected to the input terminal CKB of the drive circuit 55. Has been. The branch wiring 52 c is arranged so as to intersect with the trunk wiring 51 d via the insulating film 54 and the stacked portion 56.
　分岐配線５２ｄの一方の端部は、絶縁膜５４に形成されたコンタクトホール５３ｄを介して幹配線５１ｄと接続されており、分岐配線５２ｂの他方の端部は駆動回路５５の入力端子ＣＫＣと接続されている。分岐配線５２ｄは、幹配線５１ａ・５１ｂ・５１ｃ・５１ｄの何れとも交差していない。 One end of the branch wiring 52d is connected to the trunk wiring 51d through a contact hole 53d formed in the insulating film 54, and the other end of the branch wiring 52b is connected to the input terminal CKC of the drive circuit 55. Has been. The branch wiring 52d does not intersect any of the trunk wirings 51a, 51b, 51c, and 51d.
　つまり、分岐配線５２ａ・５２ｂ・５２ｃは、一方の端部が、幹配線５１ａ・５１ｂ・５１ｃの少なくとも何れか１つと絶縁膜５４に形成されたコンタクトホール５３ａ・５３ｂ・５３ｃの何れかを介して接続されており、他方の端部が駆動回路５５の入力端子ＶＳＳ・ＣＫＡ・ＶＫＢの何れかと接続されている。 That is, one end of each of the branch wirings 52a, 52b, and 52c is connected to at least one of the trunk wirings 51a, 51b, and 51c and any one of the contact holes 53a, 53b, and 53c formed in the insulating film 54. The other end is connected to one of the input terminals VSS, CKA, and VKB of the drive circuit 55.
　そして、分岐配線５２ａ・５２ｂ・５２ｃは、駆動回路５５への所定の駆動用の信号の入力配線となっているとともに、幹配線５１ｂ・５１ｃ・５１ｄの他の少なくとも何れか１つと絶縁膜５４及び積層部５６を介して交差して配されているものである。 The branch wirings 52a, 52b, and 52c serve as input wirings for a predetermined driving signal to the driving circuit 55, and at least one of the trunk wirings 51b, 51c, and 51d, the insulating film 54, and the like. They are arranged so as to intersect with each other through the stacked portion 56.
　このように、分岐配線５２ａ・５２ｂ・５２ｃが、何れかの幹配線５１ａ・５１ｂ・５１ｃと、駆動回路５５とを接続していることで、分岐配線５２ａ・５２ｂ・５２ｃと、幹配線５１ｂ・５１ｃ・５１ｄとで交差する領域が形成されることになる。このように交差する領域が形成されることで、駆動回路５５に供給する駆動用の信号の波形の形状が鈍る原因となるクロス容量が発生する。 In this way, the branch wirings 52a, 52b, and 52c connect any of the trunk wirings 51a, 51b, and 51c to the drive circuit 55, so that the branch wirings 52a, 52b, and 52c, A region intersecting with 51c and 51d is formed. By forming the intersecting regions in this way, a cross capacitance that causes the waveform of the driving signal supplied to the driving circuit 55 to become dull is generated.
　そこで、本実施の形態の配線構造５０は、絶縁膜５４の上層であって、少なくとも幹配線５１ｂ・５１ｃ・５１ｄと、分岐配線５２ａ・５２ｂ・５２ｃとの少なくとも何れか１つが交差する領域には、絶縁材料からなる積層部５６が形成されており、分岐配線５２ａ・５２ｂ・５２ｃは、絶縁膜５４及び積層部５６を介して、幹配線５１ｂ・５１ｃ・５１ｄと交差している構成である。 Therefore, the wiring structure 50 according to the present embodiment is an upper layer of the insulating film 54 and is in a region where at least one of the trunk wirings 51b, 51c, 51d and the branch wirings 52a, 52b, 52c intersect. The laminated portion 56 made of an insulating material is formed, and the branch wirings 52 a, 52 b, and 52 c intersect the trunk wirings 51 b, 51 c, and 51 d through the insulating film 54 and the laminated portion 56.
　これにより、幹配線５１ｂ・５１ｃ・５１ｄと、分岐配線５２ａ・５２ｂ・５２ｃとが交差する領域に発生するクロス容量を低減することができる。このため、クロス容量が発生し、分岐配線５２ａ・５２ｂ・５２ｃから出力される駆動用の信号の波形が鈍ることを抑制することができるので、分岐配線５２ａ・５２ｂ・５２ｃから駆動回路５５に供給される駆動用の信号の信頼性を向上させることができる。 Thereby, the cross capacitance generated in the region where the trunk wirings 51b, 51c, 51d and the branch wirings 52a, 52b, 52c intersect can be reduced. For this reason, it is possible to suppress the occurrence of cross capacitance and the dullness of the waveform of the driving signal output from the branch wirings 52a, 52b, and 52c, so that the supply is supplied from the branch wirings 52a, 52b, and 52c to the drive circuit 55. The reliability of the driving signal to be performed can be improved.
　また、分岐配線５２ａ・５２ｂ・５２ｃ・５２ｄは、幹配線５１ａ・５１ｂ・５１ｃ・５１ｄと異なる材質のメタルからなっており、幹配線５１ａ・５１ｂ・５１ｃ・５１ｄがソースバスライン用メタルからなる場合は、分岐配線５２ａ・５２ｂ・５２ｃ・５２ｄは、ゲートバスライン用メタルで形成されている。 The branch wirings 52a, 52b, 52c, and 52d are made of metal of a material different from that of the trunk wirings 51a, 51b, 51c, and 51d, and the trunk wirings 51a, 51b, 51c, and 51d are made of metal for the source bus line. The branch wirings 52a, 52b, 52c, and 52d are formed of metal for gate bus lines.
　また、幹配線５１ａ・５１ｂ・５１ｃ・５１ｄがゲートバスライン用メタルからなる場合は、分岐配線５２ａ・５２ｂ・５２ｃ・５２ｄは、ソースバスライン用メタルで形成されている。 Further, when the trunk lines 51a, 51b, 51c, and 51d are made of gate bus line metal, the branch lines 52a, 52b, 52c, and 52d are made of source bus line metal.
　このように、例えばＴＦＴ２１などに一般的に使用されている材用で、幹配線５１ａ・５１ｂ・５１ｃ・５１ｄ及び分岐配線５２ａ・５２ｂ・５２ｃ・５２ｄを構成することができる。 As described above, for example, the trunk wires 51a, 51b, 51c, and 51d and the branch wires 52a, 52b, 52c, and 52d can be configured for a material generally used for the TFT 21, for example.
　駆動回路５５は、一方の端子が、分岐配線５２ａ・５２ｂ・５２ｃと接続されており、他方の端子はゲートバスラインＧＬと接続されている。駆動回路５５は、基板にモノリシックに作り込まれた表示の駆動回路である。駆動回路５５は、具体的には、例えば、シフトレジスタや、絵素ＰＩＸに電源を供給するための電源回路、ＴＦＴ２１の駆動を制御する駆動回路などである。 The drive circuit 55 has one terminal connected to the branch wirings 52a, 52b, and 52c, and the other terminal connected to the gate bus line GL. The drive circuit 55 is a display drive circuit built monolithically on a substrate. Specifically, the drive circuit 55 is, for example, a shift register, a power supply circuit for supplying power to the picture element PIX, or a drive circuit for controlling the driving of the TFT 21.
　本実施の形態では、駆動回路５５は、入力側の端子ＶＳＳが分岐配線５２ａと接続されており、入力側の端子ＣＫＡが分岐配線５２ｂと接続されており、入力側の端子ＣＫＢが分岐配線５２ｃと接続されており、入力側の端子ＣＫＣが分岐配線５２ｄと接続されている。 In the present embodiment, in the drive circuit 55, the input-side terminal VSS is connected to the branch wiring 52a, the input-side terminal CKA is connected to the branch wiring 52b, and the input-side terminal CKB is connected to the branch wiring 52c. The terminal CKC on the input side is connected to the branch wiring 52d.
　そして駆動回路５５の出力側の端子ＧＯＵＴはゲートバスラインＧＬ１と接続されている。つまり、分岐配線５２ａ・５２ｂ・５２ｃ・５２ｄのそれぞれは、駆動回路５５を介して、ゲートバスラインＧＬ１、及び表示領域２ａの絵素ＰＩＸと接続されている。 The terminal GOUT on the output side of the drive circuit 55 is connected to the gate bus line GL1. That is, each of the branch lines 52a, 52b, 52c, and 52d is connected to the gate bus line GL1 and the picture element PIX in the display area 2a via the drive circuit 55.
　なお、入力端子ＶＳＳから駆動回路５５に対して入力される信号は、電源電圧であってもよいし、駆動用の信号であってもよい。また、駆動回路５５の内部の構成は、一般的な構成を適用することができ、説明を省略する。 Note that the signal input to the drive circuit 55 from the input terminal VSS may be a power supply voltage or a drive signal. Further, a general configuration can be applied to the internal configuration of the drive circuit 55, and a description thereof will be omitted.
　絶縁膜５４は、幹配線５１ａ・５１ｂ・５１ｃ・５１ｄがパターニングされた後、成膜される。絶縁膜５４は、例えば、ＣＶＤ法などによって形成することができる（絶縁膜形成工程）。絶縁膜５４は、ガラス基板５８上であって、幹配線５１ａ・５１ｂ・５１ｃ・５１ｄを覆って形成されている。 The insulating film 54 is formed after the trunk wirings 51a, 51b, 51c and 51d are patterned. The insulating film 54 can be formed by, for example, a CVD method (insulating film forming step). The insulating film 54 is formed on the glass substrate 58 so as to cover the trunk wires 51a, 51b, 51c, and 51d.
　そして、絶縁膜５４を含む絶縁膜は、幹配線５１ｂ・５１ｃ・５１ｄのそれぞれと、分岐配線５２ａ・５２ｂ・５２ｃのそれぞれとが交差する領域の膜厚は、幹配線５１ｂ・５１ｃ・５１ｄのそれぞれと、分岐配線５２ａ・５２ｂ・５２ｃのそれぞれとが交差しない領域の膜厚と比較して、積層部５６が形成されている分、厚く形成されている。 The insulating film including the insulating film 54 has a thickness in a region where each of the trunk lines 51b, 51c, and 51d intersects each of the branch lines 52a, 52b, and 52c, respectively. Compared with the film thickness of the region where each of the branch wirings 52a, 52b, and 52c does not intersect, it is formed thicker because the stacked portion 56 is formed.
　積層部５６は、少なくとも幹配線５１ｂ・５１ｃ・５１ｄのそれぞれと、分岐配線５２ａ・５２ｂ・５２ｃのそれぞれとが交差する領域に設けられていればよく、幹配線５１ｂ・５１ｃ・５１ｄの延設方向に沿って、幹配線５１ｂ・５１ｃ・５１ｄ上に設けられていてもよい。 The stacked portion 56 only needs to be provided in a region where at least each of the trunk wires 51b, 51c, and 51d and each of the branch wires 52a, 52b, and 52c intersect, and the extending direction of the trunk wires 51b, 51c, and 51d And may be provided on the main wirings 51b, 51c, 51d.
　このように、絶縁膜５４を介して、互いに交差する幹配線５１ｂ・５１ｃ・５１ｄと、分岐配線５２ａ・５２ｂ・５２ｃとが交差する領域には、絶縁膜５４に加えて、絶縁材料からなる積層部５６が設けられている。そして、分岐配線５２ａ・５２ｂ・５２ｃは、絶縁膜５４及び積層部５６を介して、幹配線５１ｂ・５１ｃ・５１ｄと交差している。つまり、幹配線５１ｂ・５１ｃ・５１ｄと、分岐配線５２ａ・５２ｂ・５２ｃとが交差する領域の絶縁材料の膜厚は、それ以外の領域の膜厚と比較して、厚く形成されている。 In this manner, in the region where the trunk wirings 51b, 51c, 51d that intersect with each other and the branch wirings 52a, 52b, 52c intersect via the insulating film 54, in addition to the insulating film 54, a laminate made of an insulating material is stacked. A portion 56 is provided. The branch wirings 52a, 52b, and 52c intersect the trunk wirings 51b, 51c, and 51d through the insulating film 54 and the stacked portion 56. That is, the thickness of the insulating material in the region where the trunk wirings 51b, 51c, 51d and the branch wirings 52a, 52b, 52c intersect is formed thicker than the thickness of the other regions.
　ここで、積層部５６の膜厚の下限値は、絶縁膜５４の膜厚の１割程度とすることが好ましい。絶縁膜５４の膜厚は３０００Å～５０００Å程度とした場合、積層部５６の膜厚の下限値は３００Å程度であることが好ましい。また、積層部５６の膜厚の上限値は、例えば、積層部５６をＳＯＧ（スピン　オン　ガラス）膜として形成する際の塗布膜厚から、１μｍ程度であることが好ましい。 Here, the lower limit value of the film thickness of the laminated portion 56 is preferably about 10% of the film thickness of the insulating film 54. When the film thickness of the insulating film 54 is about 3000 to 5000 mm, the lower limit of the film thickness of the laminated portion 56 is preferably about 300 mm. Further, the upper limit value of the film thickness of the laminated part 56 is preferably about 1 μm from the coating film thickness when the laminated part 56 is formed as an SOG (spin-on-glass) film, for example.
　以上より、積層部５６は、３００Å～１μｍで形成されていることが好ましい。つまり、積層部５６が形成されている領域の絶縁膜と、積層部５６が形成されていない領域の絶縁膜の膜厚差（積層部５６の膜厚）は３００Å～１μｍ程度であることが好ましい。これにより、より効果的に、幹配線と、分岐配線とが交差することにより発生するクロス容量を低減することができる。 From the above, it is preferable that the laminated portion 56 is formed with a thickness of 300 to 1 μm. That is, the difference in film thickness between the insulating film in the region where the stacked portion 56 is formed and the insulating film in the region where the stacked portion 56 is not formed (the thickness of the stacked portion 56) is preferably about 300 to 1 μm. . As a result, it is possible to more effectively reduce the cross capacitance generated by the intersection between the main wiring and the branch wiring.
　ここで、絶縁膜５４は、ＳｉＮｘ（シリコン窒化膜）、ＳｉＯ２（二酸化ケイ素）、またはＳＯＧ膜などの絶縁膜から構成されてもよい。 Here, the insulating film 54 may be made of an insulating film such as SiNx (silicon nitride film), SiO 2 (silicon dioxide), or SOG film.
　絶縁膜５４の上層に形成される積層部５６は、絶縁膜５４と同じ絶縁膜材料で形成してもよい。積層部５６を絶縁膜５４と同じ材質で形成する場合は、積層部５６を形成すべき膜厚も含めて、絶縁膜５４を全体的に、膜厚を厚く形成する。そして、エッチングにより、積層部５６の形成領域以外の絶縁膜５４となる絶縁材料のうち、不要な膜厚分の絶縁膜５４となる絶縁材料を除去する（積層部形成工程）。このように、絶縁膜５４上に積層部５６を形成することができる。 The stacked portion 56 formed in the upper layer of the insulating film 54 may be formed of the same insulating film material as the insulating film 54. When the stacked portion 56 is formed of the same material as that of the insulating film 54, the insulating film 54 is formed to be thick as a whole, including the thickness at which the stacked portion 56 is to be formed. Then, the insulating material that becomes the insulating film 54 of an unnecessary film thickness is removed from the insulating material that becomes the insulating film 54 other than the formation region of the stacked portion 56 by etching (stacked portion forming step). As described above, the stacked portion 56 can be formed on the insulating film 54.
　この場合は、絶縁膜５４に、積層部５６を形成しない場合と比較して、エッチング用のマスクが増加することになる。しかし、積層部５６の形成領域である幹配線５１ｂ・５１ｃ・５１ｄのそれぞれと、分岐配線５２ａ・５２ｂ・５２ｃのそれぞれとが交差する領域の絶縁膜を、単層構造とすることができる。 In this case, an etching mask is increased as compared with the case where the stacked portion 56 is not formed in the insulating film 54. However, the insulating film in the region where each of the main wirings 51b, 51c, 51d, which is the formation region of the stacked portion 56, and each of the branch wirings 52a, 52b, 52c intersect can be formed in a single layer structure.
　このように、絶縁膜５４と、積層部５６とを同じ絶縁材料から構成することで、積層部５６を構成するために、絶縁膜５４とは異なる絶縁材料を準備する必要がなく、材料コストが向上することを抑制することができる。 Thus, by forming the insulating film 54 and the laminated portion 56 from the same insulating material, it is not necessary to prepare an insulating material different from the insulating film 54 in order to constitute the laminated portion 56, and the material cost is reduced. Improvement can be suppressed.
　また、絶縁膜５４の上層に形成される積層部５６は、絶縁膜５４と異なる材質の絶縁材料で形成してもよい。例えば、絶縁膜５４をＳｉＮｘで形成した場合、積層部５６を形成する領域に、ＳｉＯ２（二酸化ケイ素）、またはＳＯＧ膜をパターニングすることにより、積層部５６を形成する（積層部形成工程）。このように、積層部５６の形成領域である幹配線５１ｂ・５１ｃ・５１ｄのそれぞれと、分岐配線５２ａ・５２ｂ・５２ｃのそれぞれとが交差する領域の絶縁膜を２層構造としてもよい。 Further, the stacked portion 56 formed on the upper layer of the insulating film 54 may be formed of an insulating material different from that of the insulating film 54. For example, when the insulating film 54 is formed of SiNx, the stacked portion 56 is formed by patterning a SiO 2 (silicon dioxide) or SOG film in a region where the stacked portion 56 is formed (stacked portion forming step). As described above, the insulating film in the region where each of the trunk wirings 51b, 51c, 51d, which is the formation region of the stacked portion 56, and each of the branch wirings 52a, 52b, 52c may have a two-layer structure.
　このように、絶縁膜５４とは異なる絶縁材料を積層部５６として、絶縁膜５４の上層に形成することで、クロス容量を低下させるために選択する絶縁材料の選択の自由度を向上させることができる。 As described above, by forming an insulating material different from the insulating film 54 as the stacked portion 56 in the upper layer of the insulating film 54, the degree of freedom in selecting the insulating material to be selected for reducing the cross capacitance can be improved. it can.
　なお、絶縁膜５４と同じ材質の絶縁材料をパターニングし、積層部５６を形成することにより、絶縁膜５４と、積層部５６とを同じ材質の絶縁膜で形成してもよい。 Note that the insulating film 54 and the stacked portion 56 may be formed of the same material by patterning an insulating material of the same material as the insulating film 54 to form the stacked portion 56.
　このように、絶縁膜５４の上層に積層部５６を形成することにより、幹配線５１ｂ・５１ｃ・５１ｄと、分岐配線５２ａ・５２ｂ・５２ｃとが交差する領域に発生するクロス容量を低減することができる。これにより、クロス容量が発生し、幹配線５１ｂ・５１ｃ・５１ｄ、及び分岐配線５２ａ・５２ｂ・５２ｃから出力される信号の波形が鈍ることを抑制することができるので、幹配線５１ｂ・５１ｃ・５１ｄ、及び分岐配線５２ａ・５２ｂ・５２ｃから出力される信号の信頼性を向上させることができる。 As described above, by forming the laminated portion 56 on the insulating film 54, the cross capacitance generated in the region where the main wirings 51b, 51c, 51d and the branch wirings 52a, 52b, 52c intersect can be reduced. it can. As a result, cross capacitance is generated, and it is possible to suppress the dullness of the waveforms of the signals output from the trunk lines 51b, 51c, and 51d and the branch lines 52a, 52b, and 52c, so that the trunk lines 51b, 51c, and 51d , And the reliability of signals output from the branch wirings 52a, 52b, and 52c.
　つまり、分岐配線５２ａ・５２ｂ・５２ｃから、波形の鈍りが少ない信号や、電源が駆動回路５５に入力される。そして、駆動回路５５には、波形の鈍りが少ない信号や、電源が入力されるので、駆動回路５５からは、内部のトランジスタなどを介して、鈍りが少ないゲート出力を、ゲートバスラインＧＬ１から表示領域２ａに出力することができる。 That is, a signal with less waveform dullness and a power source are input to the drive circuit 55 from the branch wirings 52a, 52b, and 52c. Since the drive circuit 55 is supplied with a signal with less waveform dullness and a power source, the drive circuit 55 displays a gate output with less dullness through the internal transistor from the gate bus line GL1. The data can be output to the area 2a.
　次に、図４～図６を用いて、積層部５６を設けることの具体的な効果について説明する。 Next, a specific effect of providing the stacked portion 56 will be described with reference to FIGS.
　図４は、駆動回路５５の等価回路である。図４に示すように、駆動回路５５内のトランジスタがＯＮしているタイミングで、クロック信号などの信号が入力される。入力されてくる信号が鈍っていると、駆動回路５５から出力されるゲート出力の波形形状も鈍ってしまうことになる。 FIG. 4 is an equivalent circuit of the drive circuit 55. As shown in FIG. 4, a signal such as a clock signal is input at the timing when the transistor in the drive circuit 55 is ON. If the input signal is dull, the waveform shape of the gate output output from the drive circuit 55 will be dull.
　図５は、幹配線５１ｂ・５１ｃ・５１ｄのそれぞれと、分岐配線５２ａ・５２ｂ・５２ｃのそれぞれとが交差する領域の絶縁膜５４上に積層部５６を設けていない、配線構造１００の構成を表す断面図である。 FIG. 5 shows a configuration of the wiring structure 100 in which the laminated portion 56 is not provided on the insulating film 54 in a region where the trunk wirings 51b, 51c, and 51d intersect with the branch wirings 52a, 52b, and 52c, respectively. It is sectional drawing.
　配線構造１００と、配線構造５０との相違点は、配線構造１００の絶縁膜５４上には積層部５６を設けず、絶縁膜を、均一な膜厚の絶縁膜５４からのみ構成している点である。その他は、同様であるので、同様の部材番号を付し、説明を省略する。 The difference between the wiring structure 100 and the wiring structure 50 is that the laminated portion 56 is not provided on the insulating film 54 of the wiring structure 100, and the insulating film is configured only from the insulating film 54 having a uniform thickness. It is. Since others are the same, the same member number is attached | subjected and description is abbreviate | omitted.
　図６は、駆動回路５５からゲート出力として出力されるクロック波形である。図６のクロック波形ａは、上述したように、ゲートドライバ５ａの配線に、配線構造５０用いた場合に、駆動回路５５から出力されるクロック波形である。また、図６のクロック波形ｂは、ゲートドライバ５ａの配線に、配線構造５０に替えて、配線構造１００を用いた場合に、駆動回路５５から出力されるクロック波形である。図６のクロック波形ｂと比較して、クロック波形ａは、波形の鈍りが低減している。 FIG. 6 shows a clock waveform output from the drive circuit 55 as a gate output. The clock waveform a in FIG. 6 is a clock waveform output from the drive circuit 55 when the wiring structure 50 is used for the wiring of the gate driver 5a as described above. 6 is a clock waveform output from the drive circuit 55 when the wiring structure 100 is used instead of the wiring structure 50 for the wiring of the gate driver 5a. Compared with the clock waveform b in FIG. 6, the waveform dullness of the clock waveform a is reduced.
　また、配線構造、駆動回路の個数、幹配線及び分岐配線の本数は、上述した説明以外でも、さまざまに構成することができる。 Also, the wiring structure, the number of drive circuits, the number of trunk wirings and branch wirings can be variously configured in addition to the above description.
　図７、図８は配線構造５０を適用する構成の変形例である。図７は、本実施の形態の配線構造５０を適用する配線構成の第１の変形例を表す平面図である。図８は、本実施の形態の配線構造５０を適用する配線構成の第２の変形例を表す平面図である。 7 and 8 are modifications of the configuration to which the wiring structure 50 is applied. FIG. 7 is a plan view showing a first modification of the wiring configuration to which the wiring structure 50 of the present embodiment is applied. FIG. 8 is a plan view illustrating a second modification of the wiring configuration to which the wiring structure 50 of the present embodiment is applied.
　図７で示す配線構造は、図２で示した幹配線５１ａに替えて、互いに導通がとられて互いに平行に幹配線５１－１ａ・５１－２ａ・５１－３ａが並置されている。そして、分岐配線５２ａの一方の端部は、コンタクトホール５３ａを介して、幹配線５１－１ａと接続されており、他方の端部は、駆動回路５５の入力端子ＶＳＳと接続されている。 In the wiring structure shown in FIG. 7, instead of the trunk wiring 51a shown in FIG. 2, the trunk wirings 51-1a, 51-2a, and 51-3a are juxtaposed in parallel with each other. One end of the branch wiring 52a is connected to the trunk wiring 51-1a via the contact hole 53a, and the other end is connected to the input terminal VSS of the drive circuit 55.
　また、図８は、駆動回路が直列に、複数接続された構成である。幹配線５１－１ａ・５１－２ａ・５１－３ａと、幹配線５１ｂ・５１ｃ・５１ｄとの間に、駆動回路５５ａが配置されている。互いに導通が取られている幹配線５１－１ａ・５１－２ａ・５１－３ａは、５１－３ａを介して、駆動回路５５ａの入力端子ＶＳＳ１と接続されている。 FIG. 8 shows a configuration in which a plurality of drive circuits are connected in series. A drive circuit 55a is arranged between the trunk wirings 51-1a, 51-2a, and 51-3a and the trunk wirings 51b, 51c, and 51d. The trunk lines 51-1a, 51-2a, and 51-3a that are electrically connected to each other are connected to the input terminal VSS1 of the drive circuit 55a via the 51-3a.
　そして、分岐配線５２ａの一方の端子は、駆動回路５５ａの出力端子ＶＳＳ２と接続されており、他方の端子は駆動回路５５ｂの入力端子ＶＳＳ３と接続されている。分岐配線５２ｂの一方の端子は、駆動回路５５ａの出力端子ＣＫＡ１と接続されており、交差する幹配線５１ｂとコンタクトホール５３ｂを介して接続されており、他方の端子は駆動回路５５ｂの入力端子ＣＫＡ２と接続されている。分岐配線５２ｃの一方の端子は、駆動回路５５ａの出力端子ＣＫＢ１と接続されており、交差する幹配線５１ｃとコンタクトホール５３ｃを介して接続されており、他方の端子は駆動回路５５ｂの入力端子ＣＫＢ２と接続されている。分岐配線５２ｄの一方の端子は、コンタクトホール５３ｄを介して接続されており、他方の端子は駆動回路５５の入力端子ＣＫＣと接続されている。また、駆動回路５５ｂの出力端子ＧＯＵＴはゲートバスラインＧＬ１と接続されている。 One terminal of the branch wiring 52a is connected to the output terminal VSS2 of the drive circuit 55a, and the other terminal is connected to the input terminal VSS3 of the drive circuit 55b. One terminal of the branch wiring 52b is connected to the output terminal CKA1 of the drive circuit 55a, and is connected to the intersecting trunk wiring 51b via the contact hole 53b, and the other terminal is the input terminal CKA2 of the drive circuit 55b. Connected with. One terminal of the branch wiring 52c is connected to the output terminal CKB1 of the driving circuit 55a, and is connected to the intersecting trunk wiring 51c via the contact hole 53c, and the other terminal is the input terminal CKB2 of the driving circuit 55b. Connected with. One terminal of the branch wiring 52d is connected via the contact hole 53d, and the other terminal is connected to the input terminal CKC of the drive circuit 55. The output terminal GOUT of the drive circuit 55b is connected to the gate bus line GL1.
　このように、ゲートドライバ５ａやゲートドライバ５ｂ、さらにソースドライバ６などに形成される、さまざまなモノリシック回路に配線構造５０を適用することができる。このような、配線構造５０によると、駆動回路５５や、駆動回路５５ｂに供給される駆動用の信号の波形の鈍りを低減することができるので、表示領域２ａの周辺部に、複数の駆動回路を配置することができ、駆動回路の高密度化を行なうことができる。 As described above, the wiring structure 50 can be applied to various monolithic circuits formed in the gate driver 5a, the gate driver 5b, the source driver 6 and the like. According to such a wiring structure 50, the dullness of the waveform of the drive signal supplied to the drive circuit 55 and the drive circuit 55b can be reduced, so that a plurality of drive circuits are provided around the display area 2a. The drive circuit can be densified.
　〔実施形態２〕
　次に、配線構想５０を表示領域２ａに形成する場合の一例について説明する。 [Embodiment 2]
Next, an example of forming the wiring concept 50 in the display area 2a will be described.
　図３に示した表示領域２ａ内のソースバスラインＳＬと、ゲートバスラインＧＬとの交差部分に、配線構造５０を適用することができる。ここで、絶縁膜（不図示）を介して形成されるソースバスラインＳＬと、ゲートバスラインＧＬとは、何れが上層であっても下層であってもよい。 The wiring structure 50 can be applied to the intersection of the source bus line SL and the gate bus line GL in the display area 2a shown in FIG. Here, the source bus line SL and the gate bus line GL formed via an insulating film (not shown) may be either an upper layer or a lower layer.
　表示領域２ａ内で、絶縁膜（付図示）を介して、ゲートバスラインＧＬが下層であって、ソースバスラインＳＬが上記絶縁膜の上層に配置されている場合は、配線構造５０は以下のように表現できる。 In the display region 2a, when the gate bus line GL is a lower layer and the source bus line SL is disposed in an upper layer of the insulating film through an insulating film (illustrated), the wiring structure 50 has the following structure. Can be expressed as follows.
　つまり、配線構造５０は、ガラス基板５８上に配される複数のゲートバスラインＧＬと、ガラス基板５８の上層であって、複数のゲートバスラインＧＬを覆って形成される絶縁膜（不図示）と、当該絶縁膜の上層であって、当該絶縁膜を介して、複数のゲートバスラインＧＬの少なくとも何れかと交差して配される複数のソースバスラインＳＬとを含んで構成されている。そして、配線構造５０は、上記絶縁膜の上層であって、少なくとも複数のゲートバスラインＧＬと、複数のソースバスラインＳＬとのそれぞれが交差する領域には、絶縁材料からなる積層部５６が形成されている。また、配線構造５０の複数のソースバスラインＳＬのそれぞれは、上記絶縁膜及び積層部５６を介して、複数のゲートバスラインＧＬのそれぞれと交差している構成である。 That is, the wiring structure 50 includes a plurality of gate bus lines GL disposed on the glass substrate 58 and an insulating film (not shown) that is an upper layer of the glass substrate 58 and covers the plurality of gate bus lines GL. And a plurality of source bus lines SL arranged above the insulating film and intersecting at least one of the plurality of gate bus lines GL via the insulating film. The wiring structure 50 is an upper layer of the insulating film, and in the region where at least the plurality of gate bus lines GL and the plurality of source bus lines SL intersect each other, a stacked portion 56 made of an insulating material is formed. Has been. In addition, each of the plurality of source bus lines SL of the wiring structure 50 is configured to intersect with each of the plurality of gate bus lines GL via the insulating film and the stacked portion 56.
　このように、配線構造５０を表示領域２ａ内に設けることにより、ソースバスラインＳＬと、ゲートバスラインＧＬとが交差する領域に発生するクロス容量を抑制することができるので、ゲートバスラインＧＬの容量を小さくすることができる。このようにゲートバスラインＧＬの容量を小さくすることにより、駆動回路５５を小型化することができ、表示領域２ａの周辺部であるパネル額縁領域（ゲートドライバ５ａ・５ｂ、ソースドライバ６が配される領域）を小さくすることができる。 Thus, by providing the wiring structure 50 in the display region 2a, the cross capacitance generated in the region where the source bus line SL and the gate bus line GL intersect can be suppressed. The capacity can be reduced. By reducing the capacity of the gate bus line GL in this way, the drive circuit 55 can be reduced in size, and the panel frame area ( gate drivers 5a and 5b, source driver 6 which is the peripheral part of the display area 2a is arranged. Area) can be reduced.
　また、表示領域２ａ内で、絶縁膜（付図示）を介して、ソースバスラインＳＬが下層であって、ゲートバスラインＧＬが上記絶縁膜の上層に配置されている場合は、配線構造５０は以下のように表現できる。 In the display region 2a, when the source bus line SL is in the lower layer and the gate bus line GL is arranged in the upper layer of the insulating film via the insulating film (illustrated), the wiring structure 50 is It can be expressed as follows.
　つまり、配線構造５０は、ガラス基板５８上に配される複数のソースバスラインＳＬと、ガラス基板５８の上層であって、複数のソースバスラインＳＬを覆って形成される絶縁膜（不図示）と、当該絶縁膜の上層であって、当該絶縁膜を介して、複数のソースバスラインＳＬの少なくとも何れかと交差して配される複数のゲートバスラインＧＬとを含んで構成されている。 That is, the wiring structure 50 includes a plurality of source bus lines SL disposed on the glass substrate 58 and an insulating film (not shown) that is an upper layer of the glass substrate 58 and covers the plurality of source bus lines SL. And a plurality of gate bus lines GL arranged on the insulating film and intersecting at least one of the plurality of source bus lines SL via the insulating film.
　そして、配線構造５０には、上記絶縁膜の上層であって、少なくとも複数のソースバスラインＳＬと、複数のゲートバスラインＧＬとのそれぞれが交差する領域には、絶縁材料からなる積層部５６が形成されている。また、配線構造５０の複数のゲートバスラインＧＬのそれぞれは、上記絶縁膜及び積層部５６を介して、複数のソースバスラインＳＬのそれぞれと交差している構成である。 In the wiring structure 50, a laminated portion 56 made of an insulating material is provided in a region above the insulating film and intersecting at least the plurality of source bus lines SL and the plurality of gate bus lines GL. Is formed. Each of the plurality of gate bus lines GL of the wiring structure 50 is configured to intersect with each of the plurality of source bus lines SL via the insulating film and the stacked portion 56.
　本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。 The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.
　以上のように、上記の課題を解決するために、本発明の配線構造は、基板上に配されている複数の第１配線と、上記基板の上層であって、上記複数の第１配線を覆って形成されている絶縁膜と、上記絶縁膜の上層であって、上記絶縁膜を介して、上記複数の第１配線の少なくとも何れか１つと交差して配されている第２配線とを備え、上記絶縁膜の上層であって、少なくとも上記第１配線と、上記第２配線とが交差する領域には、絶縁材料からなる積層部が形成されており、上記第２配線は、上記絶縁膜及び上記積層部を介して、上記第１配線と交差していることを特徴としている。 As described above, in order to solve the above-described problem, the wiring structure of the present invention includes a plurality of first wirings arranged on a substrate and an upper layer of the substrate, wherein the plurality of first wirings are arranged. An insulating film formed so as to cover, and a second wiring that is an upper layer of the insulating film and is arranged to intersect with at least one of the plurality of first wirings via the insulating film. A stacked portion made of an insulating material is formed at least in a region above the insulating film, where at least the first wiring and the second wiring intersect with each other. It is characterized in that it intersects with the first wiring via the film and the laminated portion.
　上記課題を解決するために、本発明の配線構造の製造方法は、基板上に複数の第１配線をパターニングする第１配線形成工程と、上記第１配線形成工程で形成された上記第１配線を覆って絶縁膜を形成する絶縁膜形成工程と、上記絶縁膜形成工程で形成された上記絶縁膜の上層であって、上記絶縁膜を介して上記第１配線と、当該第１配線とは異なる第２配線とを交差させる領域に、絶縁材料からなる積層部を形成する積層部形成工程と、上記積層部形成工程で形成した積層部と、上記絶縁膜形成工程で形成した絶縁膜とを介して、上記第１配線と交差するように上記第２配線をパターニングする第２配線形成工程とを含むことを特徴としている。 In order to solve the above problems, a method for manufacturing a wiring structure according to the present invention includes a first wiring forming step of patterning a plurality of first wirings on a substrate, and the first wiring formed in the first wiring forming step. An insulating film forming step of forming an insulating film so as to cover the upper surface of the insulating film, and an upper layer of the insulating film formed in the insulating film forming step, wherein the first wiring and the first wiring are interposed through the insulating film, A laminated portion forming step of forming a laminated portion made of an insulating material in a region where different second wirings intersect, a laminated portion formed in the laminated portion forming step, and an insulating film formed in the insulating film forming step And a second wiring forming step of patterning the second wiring so as to intersect the first wiring.
　上記構成によると、上記絶縁膜を介して、互いに交差する第１配線と、第２配線とが交差する領域には、上記絶縁膜に加えて、上記絶縁膜材料からなる積層部が設けられている。そして、上記第２配線は、上記絶縁膜及び上記積層部を介して、上記第１配線と交差している。つまり、上記第１配線と、上記第２配線とが交差する領域の絶縁材料の膜厚は、それ以外の領域の膜厚と比較して、厚く形成されている。 According to the above configuration, in the region where the first wiring and the second wiring intersect with each other via the insulating film, a laminated portion made of the insulating film material is provided in addition to the insulating film. Yes. The second wiring crosses the first wiring through the insulating film and the stacked portion. That is, the thickness of the insulating material in the region where the first wiring and the second wiring intersect is formed thicker than the thickness of the other regions.
　このため、上記第１配線と、第２配線とが交差する領域に発生する容量（クロス容量）を低減することができる。これにより、クロス容量が発生し、上記第１配線、及び上記第２配線から出力される信号の波形が鈍ることを抑制することができるので、第１配線、及び第２配線から出力される信号の信頼性を向上させることができる。 For this reason, it is possible to reduce the capacitance (cross capacitance) generated in the region where the first wiring and the second wiring intersect. As a result, cross capacitance is generated, and it is possible to suppress a dull waveform of signals output from the first wiring and the second wiring. Therefore, signals output from the first wiring and the second wiring. Reliability can be improved.
　上記課題を解決するために、本発明の配線構造は、基板にモノリシックに作り込まれた表示の駆動回路と、基板上に配されるとともに上記駆動回路に駆動用の信号を供給する複数の第１配線と、上記基板の上層であって、上記複数の第１配線を覆って形成されている絶縁膜と、上記絶縁膜の上層であって、上記絶縁膜を介して、上記複数の第１配線の少なくとも何れか１つと上記絶縁膜に形成されたコンタクトホールを介して接続されて上記駆動回路への所定の上記駆動用の信号の入力配線となっているとともに、上記複数の第１配線の他の少なくとも何れか１つと交差して配されている第２配線とを備え、上記絶縁膜の上層であって、少なくとも上記第１配線と、上記第２配線とが交差する領域には、絶縁材料からなる積層部が形成されており、上記第２配線は、上記絶縁膜及び上記積層部を介して、上記第１配線と交差していることを特徴としている。 In order to solve the above-described problems, a wiring structure according to the present invention includes a display driving circuit monolithically formed on a substrate, and a plurality of second driving circuits disposed on the substrate and supplying driving signals to the driving circuit. One wiring, an upper layer of the substrate and covering the plurality of first wirings, and an upper layer of the insulating film, the plurality of first It is connected to at least one of the wirings through a contact hole formed in the insulating film, and serves as an input wiring for a predetermined driving signal to the driving circuit, and the plurality of first wirings A second wiring arranged to intersect with at least one of the other, and is an upper layer of the insulating film, wherein at least an area where the first wiring and the second wiring intersect is insulated A stack of materials is formed Cage, the second wiring through the insulating film and the laminated portion, is characterized in that intersects with the first wiring.
　上記構成によると、上記第１配線と、第２配線とが交差する領域には、絶縁材料からなる積層部が形成されているので、上記第１配線と、第２配線とが交差する領域に発生するクロス容量を低減することができる。これにより、クロス容量の発生によって上記第２配線から上記駆動回路に供給される駆動用の信号の波形の形状が鈍ることを防止できるので、信頼性が高い駆動用の信号を駆動回路に供給することができる。 According to the above configuration, since the laminated portion made of the insulating material is formed in the region where the first wiring and the second wiring intersect, the region where the first wiring and the second wiring intersect. The generated cross capacitance can be reduced. As a result, it is possible to prevent the waveform of the driving signal supplied from the second wiring to the driving circuit from being dull due to the generation of the cross capacitance, so that a highly reliable driving signal is supplied to the driving circuit. be able to.
　上記配線構造は、上記絶縁膜と、上記積層部とは、互いに異なる絶縁材料からなることが好ましい。 In the wiring structure, the insulating film and the stacked portion are preferably made of different insulating materials.
　上記構成により、上記第１配線と、上記第２配線とが交差することにより発生するクロス容量を低下させるために、上記絶縁膜とは異なる絶縁材料を積層部として構成することができる。このため、上記クロス容量を低下させるために選択する絶縁材料の選択の自由度を向上させることができる。 With the above configuration, an insulating material different from that of the insulating film can be configured as a laminated portion in order to reduce cross capacitance generated when the first wiring and the second wiring intersect. For this reason, the freedom degree of selection of the insulating material selected in order to reduce the said cross capacity can be improved.
　上記配線構造は、上記絶縁膜と、上記積層部とは、同じ絶縁材料からなることが好ましい。 In the wiring structure, the insulating film and the stacked portion are preferably made of the same insulating material.
　上記構成により、上記積層部を、上記絶縁膜と同じ絶縁材料で構成することができるので、上記積層部を構成するための絶縁材料を準備する必要がなく、材料コストが向上することを抑制することができる。 With the above configuration, since the stacked portion can be formed of the same insulating material as the insulating film, it is not necessary to prepare an insulating material for forming the stacked portion, and the increase in material cost is suppressed. be able to.
　上記配線構造の上記第１配線は、ゲートバスライン用メタルで形成されており、上記第２配線は、ソースバスライン用メタルで形成されているか、または上記第１配線はソースバスライン用メタルで形成されており、上記第２配線はゲートバスライン用メタルで形成されていることが好ましい。 The first wiring of the wiring structure is formed of a gate bus line metal, and the second wiring is formed of a source bus line metal, or the first wiring is a source bus line metal. Preferably, the second wiring is formed of a gate bus line metal.
　上記構成により、例えばＴＦＴ素子などに一般的に使用されている材用で、上記第１配線及び第２配線を構成することができる。 With the above configuration, the first wiring and the second wiring can be configured for a material generally used for TFT elements, for example.
　上記の課題を解決するために、本発明の配線基板は、上記配線構造を備え、マトリクス状にＴＦＴ素子が形成された表示領域が配さており、上記配線構造は、上記配線基板の上記表示領域と隣接する領域に設けられ、上記第２配線の一方の端部は、上記第１配線と接続され、上記第２配線の他方の端部は、上記ＴＦＴ素子と接続されるゲートバスラインと接続されていることが好ましい。 In order to solve the above problems, a wiring board of the present invention includes the above wiring structure, and a display region in which TFT elements are formed in a matrix is arranged. The one end of the second wiring is connected to the first wiring, and the other end of the second wiring is connected to a gate bus line connected to the TFT element. It is preferable that
　上記構成により、ＴＦＴ素子がマトリクス状に形成された表示領域が配された配線基板であって、上記表示領域と隣接する領域に、上記配線構造を設けることができる。このため、上記表示領域と隣接する領域に、複数の配線や、当該配線から分岐するさまざま分岐配線を設けたとして、クロス容量が小さい配線基板を構成することができる。このため、ＴＦＴ素子を駆動させるための回路を、クロス容量の発生を抑えて、上記表示領域と隣接する領域に配置することができる。 With the above configuration, the wiring structure can be provided in a region adjacent to the display region, which is a wiring substrate on which a display region in which TFT elements are formed in a matrix is arranged. For this reason, a wiring board with a small cross capacitance can be configured by providing a plurality of wirings and various branch wirings branched from the wirings in a region adjacent to the display region. Therefore, a circuit for driving the TFT element can be arranged in a region adjacent to the display region while suppressing the generation of cross capacitance.
　上記の課題を解決するために、本発明の液晶表示パネルは、上記配線基板と、上記配線基板のＴＦＴ素子と対向する領域に対向電極が配され、液晶層を介して上記配線基板と対向配置される対向基板とを備えていることが好ましい。 In order to solve the above-described problems, the liquid crystal display panel of the present invention has a counter electrode disposed in a region facing the TFT element of the wiring substrate and the wiring substrate, and is disposed to face the wiring substrate through a liquid crystal layer. The counter substrate is preferably provided.
　上記構成により、上記第１配線と、上記第２配線とが交差することにより、発生するクロス容量を低下させた液晶表示パネルを構成することができる。 With the above configuration, it is possible to configure a liquid crystal display panel in which cross capacitance generated is reduced by crossing the first wiring and the second wiring.
　本発明は、互いに交差する配線間に形成されている絶縁膜の膜厚を厚くするので、絶縁膜を介して交差して配される配線構造を備える表示パネルに適用することができる。 The present invention increases the film thickness of the insulating film formed between the wirings crossing each other, so that the present invention can be applied to a display panel having a wiring structure arranged so as to cross through the insulating film.
　　１　液晶表示装置
　　２　表示パネル
　２ａ　表示領域
　５ａ・５ｂ　ゲートドライバ
　　６　ソースドライバ
　２１　ＴＦＴ
　５０　配線構造
　５１ａ・５１ｂ・５１ｃ・５１ｄ　幹配線（第１配線）
　５２ａ・５２ｂ・５２ｃ・５２ｄ　分岐配線（第２配線）
　５３ａ・５３ｂ・５３ｃ・５３ｄ　コンタクトホール
　５４　絶縁膜
　５５　駆動回路
　５６　積層部
　５８　ガラス基板（基板）
　ＧＬ　ゲートバスライン（第１配線、第２配線）
　ＳＬ　ソースバスライン（第１配線、第２配線） DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Display panel 2a Display area 5a * 5b Gate driver 6 Source driver 21 TFT
50 Wiring structure 51a / 51b / 51c / 51d Trunk wiring (first wiring)
52a, 52b, 52c, 52d Branch wiring (second wiring)
53a, 53b, 53c, 53d Contact hole 54 Insulating film 55 Drive circuit 56 Laminating part 58 Glass substrate (substrate)
GL gate bus line (first wiring, second wiring)
SL source bus line (first wiring, second wiring)

Claims (8)

  1. 　基板上に配されている複数の第１配線と、
    　上記基板の上層であって、上記複数の第１配線を覆って形成されている絶縁膜と、
    　上記絶縁膜の上層であって、上記絶縁膜を介して、上記複数の第１配線の少なくとも何れか１つと交差して配されている第２配線とを備え、
    　上記絶縁膜の上層であって、少なくとも上記第１配線と、上記第２配線とが交差する領域には、絶縁材料からなる積層部が形成されており、
    　上記第２配線は、上記絶縁膜及び上記積層部を介して、上記第１配線と交差していることを特徴とする配線構造。     A plurality of first wirings disposed on the substrate;
    An insulating film that is an upper layer of the substrate and covers the plurality of first wirings;
    A second wiring that is an upper layer of the insulating film and is arranged to intersect with at least any one of the plurality of first wirings through the insulating film;
    A laminated portion made of an insulating material is formed in an upper layer of the insulating film, at least in a region where the first wiring and the second wiring intersect.
    The wiring structure, wherein the second wiring intersects the first wiring through the insulating film and the stacked portion.
  2. 　基板にモノリシックに作り込まれた表示の駆動回路と、
    　基板上に配されるとともに上記駆動回路に駆動用の信号を供給する複数の第１配線と、
    　上記基板の上層であって、上記複数の第１配線を覆って形成されている絶縁膜と、
    　上記絶縁膜の上層であって、上記絶縁膜を介して、上記複数の第１配線の少なくとも何れか１つと上記絶縁膜に形成されたコンタクトホールを介して接続されて上記駆動回路への所定の上記駆動用の信号の入力配線となっているとともに、上記複数の第１配線の他の少なくとも何れか１つと交差して配されている第２配線とを備え、
    　上記絶縁膜の上層であって、少なくとも上記第１配線と、上記第２配線とが交差する領域には、絶縁材料からなる積層部が形成されており、
    　上記第２配線は、上記絶縁膜及び上記積層部を介して、上記第１配線と交差していることを特徴とする配線構造。     Display drive circuit built monolithically on the substrate,
    A plurality of first wirings disposed on the substrate and supplying a driving signal to the driving circuit;
    An insulating film that is an upper layer of the substrate and covers the plurality of first wirings;
    An upper layer of the insulating film, which is connected to at least one of the plurality of first wirings via a contact hole formed in the insulating film via the insulating film and has a predetermined connection to the driving circuit. A drive signal input wiring, and a second wiring arranged to intersect with at least any one of the plurality of first wirings,
    A laminated portion made of an insulating material is formed in an upper layer of the insulating film, at least in a region where the first wiring and the second wiring intersect.
    The wiring structure, wherein the second wiring intersects the first wiring through the insulating film and the stacked portion.
  3. 　上記絶縁膜と、上記積層部とは、互いに異なる絶縁材料からなることを特徴とする請求項１又は２に記載の配線構造。 3. The wiring structure according to claim 1, wherein the insulating film and the laminated portion are made of different insulating materials.
  4. 　上記絶縁膜と、上記積層部とは、同じ絶縁材料からなることを特徴とする請求項１又は２に記載の配線構造。 3. The wiring structure according to claim 1, wherein the insulating film and the laminated portion are made of the same insulating material.
  5. 　上記第１配線は、ゲートバスライン用メタルで形成されており、上記第２配線は、ソースバスライン用メタルで形成されているか、または上記第１配線はソースバスライン用メタルで形成されており、上記第２配線はゲートバスライン用メタルで形成されていることを特徴とする請求項１～４の何れか１項に記載の配線構造。 The first wiring is made of gate bus line metal, and the second wiring is made of source bus line metal, or the first wiring is made of source bus line metal. The wiring structure according to any one of claims 1 to 4, wherein the second wiring is formed of a metal for a gate bus line.
  6. 　請求項１～５の何れか１項に記載の配線構造を備えている配線基板であって、
    　マトリクス状にＴＦＴ素子が形成された表示領域が配されており、
    　上記配線構造は、上記配線基板の上記表示領域と隣接する領域に設けられ、
    　上記第２配線の一方の端部は、上記第１配線と接続され、上記第２配線の他方の端部は、上記ＴＦＴ素子と接続されるゲートバスラインと接続されていることを特徴とする配線基板。     A wiring board comprising the wiring structure according to any one of claims 1 to 5,
    A display area in which TFT elements are formed in a matrix is arranged,
    The wiring structure is provided in an area adjacent to the display area of the wiring board,
    One end of the second wiring is connected to the first wiring, and the other end of the second wiring is connected to a gate bus line connected to the TFT element. Wiring board.
  7. 　請求項６に記載の配線基板と、
    　上記配線基板のＴＦＴ素子と対向する領域に対向電極が配されており、液晶層を介して上記配線基板と対向配置される対向基板とを備えたことを特徴とする液晶表示パネル。     The wiring board according to claim 6;
    A liquid crystal display panel comprising: a counter electrode disposed in a region facing the TFT element of the wiring substrate; and a counter substrate disposed to face the wiring substrate via a liquid crystal layer.
  8. 　基板上に複数の第１配線をパターニングする第１配線形成工程と、
    　上記第１配線形成工程で形成された上記第１配線を覆って絶縁膜を形成する絶縁膜形成工程と、
    　上記絶縁膜形成工程で形成された上記絶縁膜の上層であって、上記絶縁膜を介して上記第１配線と、当該第１配線とは異なる第２配線とを交差させる領域に、絶縁材料からなる積層部を形成する積層部形成工程と、
    　上記積層部形成工程で形成した積層部と、上記絶縁膜形成工程で形成した絶縁膜とを介して、上記第１配線と交差するように上記第２配線をパターニングする第２配線形成工程とを備えることを特徴とする配線構造の製造方法。     A first wiring forming step of patterning a plurality of first wirings on a substrate;
    An insulating film forming step of covering the first wiring formed in the first wiring forming step and forming an insulating film;
    In an upper layer of the insulating film formed in the insulating film forming step, the insulating material is used to cross the first wiring and a second wiring different from the first wiring through the insulating film. A laminated part forming step of forming a laminated part comprising:
    A second wiring forming step of patterning the second wiring so as to intersect the first wiring through the stacked portion formed in the stacked portion forming step and the insulating film formed in the insulating film forming step; A method for manufacturing a wiring structure, comprising:
PCT/JP2010/000959 2009-05-12 2010-02-16 Wiring structure, wiring substrate, liquid crystal display panel, and method for manufacturing wiring structure WO2010131393A1 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58192090A (en) * 1982-05-06 1983-11-09 セイコーエプソン株式会社 Matrix array
JPH1184427A (en) * 1997-09-11 1999-03-26 Semiconductor Energy Lab Co Ltd Drive circuit for liquid crystal display device
JP2000305111A (en) * 1999-04-26 2000-11-02 Sharp Corp Liquid crystal display device
JP2003046090A (en) * 2001-07-21 2003-02-14 Samsung Electronics Co Ltd Substrate for liquid crystal display panel and method of manufacturing the same
WO2006022259A1 (en) * 2004-08-24 2006-03-02 Sharp Kabushiki Kaisha Active matrix substrate and display unit provided with it
JP2007171736A (en) * 2005-12-26 2007-07-05 Epson Imaging Devices Corp Liquid crystal display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58192090A (en) * 1982-05-06 1983-11-09 セイコーエプソン株式会社 Matrix array
JPH1184427A (en) * 1997-09-11 1999-03-26 Semiconductor Energy Lab Co Ltd Drive circuit for liquid crystal display device
JP2000305111A (en) * 1999-04-26 2000-11-02 Sharp Corp Liquid crystal display device
JP2003046090A (en) * 2001-07-21 2003-02-14 Samsung Electronics Co Ltd Substrate for liquid crystal display panel and method of manufacturing the same
WO2006022259A1 (en) * 2004-08-24 2006-03-02 Sharp Kabushiki Kaisha Active matrix substrate and display unit provided with it
JP2007171736A (en) * 2005-12-26 2007-07-05 Epson Imaging Devices Corp Liquid crystal display device

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