JPH0427920A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To reduce the probability of occurrence of a picture element defect by juxtaposing a common electrode line or a gate electrode line and a pixel electrode to prevent direct short-circuit between the common electrode line or the gate electrode line and the pixel electrode even at the time of short- circuit of one capacity. CONSTITUTION:The pixel electrode 9 and a common electrode 3 are juxtaposed without overlapping, and a floating electrode 12 is so provided that a dielectric film 13 is interposed between the pixel electrode 9 as well as the common electrode 3 and this flowing electrode 12, and by this constitution, electric charge holding capacities 21 and 22 are formed between the floating electrode 12 and the pixel electrode 9 and between the floating electrode 9 and the common electrode 3. Since capacitance coupling between the pixel electrode 9 and the common electrode 3 is available by these serial coupling, the circuit between the common electrode 12 and a drain electrode 8 is not immediately short- circuited even in the case of the occurrence of a short-circuit defect between the floating electrode 12 and the pixel electrode 9 or between the floating electrode 12 and the common electrode 3. Consequently, picture element defects due to short-circuit of electric charge holding capacities are reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The second invention is a thin film transistor array substrate (hereinafter referred to as TP).
It's called T. ), especially TFT
The present invention relates to a liquid crystal display device that reduces the occurrence of pixel defects due to short circuits in charge holding capacitors provided on an array substrate.

[Prior Art] A liquid crystal display device usually has a display material such as a liquid crystal sandwiched between two opposing substrates, and controls transmitted light by applying a voltage to this display material to change its arrangement. , images, etc. are displayed. At this time, pixel electrodes arranged in a 71x pattern are provided on at least one substrate,
In order to selectively operate these pixels, a functional element having nonlinear characteristics such as a field effect I transistor (FET) is provided for each pixel. Furthermore, a charge storage capacitor is provided for each pixel in order to improve image quality.

For example, Figure 22 shows the procedure of 9t.
h INTERN＾Tl0NAL DISPLAY R
ESEARCHHC0NFERENCE (Japan
Display 89) (1989) p514-517
23 is a plan view showing the -pixel portion of the TFT array substrate used in this type of liquid crystal display device shown in FIG.
14 is an equivalent circuit diagram in FIG. 22.

In the figure, 1 is a source electrode line, 2 is a gate electrode line, and 3 is a source electrode line.
is a common electrode line, 4 is a gate insulating film, 5 is one layer of hydrogenated amorphous silicon, 7 is hydrogenated amorphous silicon 0
The TFT array substrate is composed of three layers: 8 is a drain electrode, 9 is a pixel electrode, IO is a protective film, and 14 is a transparent insulating substrate serving as a support. , 18 is a charge holding capacitor formed by laminating the common electrode 3 and the pixel electrode 9 with an insulating film 4 interposed therebetween; 35 is a liquid crystal; 38 is a transparent capacitor sandwiching the liquid crystal 35 together with the transparent insulating substrate 14; A counter electrode is shown.

Such a TFT array substrate is manufactured through the following steps.

First, the gate electrode line 2 and the common electrode line 3 are formed using MoTa on the transparent insulating substrate 14, and then the surfaces of the gate electrode line 2 and the common electrode line 3 are anodized.

Next, the gate insulating film 4, hydrogenated amorphous silicon i
Layer 5. After forming and patterning a hydrated amorphous silicon layer 7, a pixel electrode 9 is formed. Then, a source electrode line l and a drain electrode 8 are formed, and T
Complete PT. By this TPT and the pixel electrode 9, T
FT A1/A is configured. At this time, common electrode #i
! A charge storage capacitor 18 is formed by overlapping the pixel electrode 9 and the pixel electrode 9 with the gate insulating film 4 interposed therebetween.

A liquid crystal display device is constructed by arranging a counter electrode substrate having a color filter and a transparent conductive film so as to face the TFT array substrate thus constructed, with a liquid crystal or the like sandwiched therebetween.

[Problem to be Solved by the Invention 1] In the conventional liquid crystal display device as described above, the common electrode line 3 and the pixel electrode 9 are configured to directly overlap. A short-circuiting defect with the drain electrode 8 is likely to occur, and when such a short-circuiting defect occurs, it becomes difficult to control the voltage of the pixel electrode 9 by TPT, resulting in a decrease in yield as a display device.

Furthermore, the same defects as described above occur when a charge storage capacitor is formed between the gate electrode for the pixel electrode of the primary stage and the pixel electrode.

The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and provides a liquid crystal display device that can reduce the probability of pixel defects caused by short-circuiting of charge storage capacitors.

[Means for Solving the Problem] The liquid crystal display device according to the present invention has a common electrode line and a pixel electrode arranged in parallel, and a floating electrode placed opposite to these electrodes with a dielectric interposed therebetween. A charge storage capacitor including a plurality of capacitors is formed between the common electrode line and the pixel electrode.

Further, in the liquid crystal display device according to the second invention, a gate electrode line and a pixel electrode are arranged side by side, and a floating electrode is arranged facing each other with a dielectric interposed between these electrodes, and the floating electrode, gate electrode line, and pixel electrode are arranged in parallel. A charge holding capacitor consisting of a plurality of capacitors is formed between the electrode and the electrode.

[Function] According to the liquid crystal display device of the present invention, since the common electrode line or the gate electrode line and the pixel electrode are arranged in parallel, even if one of the capacitances is short-circuited, the common electrode line or the gate electrode line and the pixel electrode There is no direct short circuit between the two, and the probability of pixel defects occurring can be reduced.

[Example] Hereinafter, a diagram illustrating an embodiment of the present invention will be described.

FIG. 1 is a plan configuration diagram showing one pixel of a TFT array substrate which is an embodiment of the present invention, and FIG. 2 is an A in FIG. 1.
-A sectional view, FIG. 3 is a circuit configuration diagram in FIG. 1. In the figure, 1 is a source electrode line, 2 is a gate electrode line,
3 is a common electrode line, 4 is a gate insulating film, 5 is a semiconductor i-layer,
6 is an upper insulating film, 7 is a semiconductor n'' layer, 8 is a drain electrode, 9 is a pixel electrode, 10 is a protective film, 12 is a floating electrode, 13
is a dielectric film, 14 is a transparent insulating substrate, 15 is TPT, 16
is the gate-drain parasitic capacitance, and 21 is the charge retention capacitance (
1) and 22 are charge storage capacitors (2).

Such a TFT array substrate is manufactured through the following steps.

First, a transparent conductive film such as ITO is formed on a transparent insulating substrate 14 such as glass by EB evaporation. Next, unnecessary portions of the transparent conductive film are removed by photoetching or the like to form floating electrodes 12 in the form of islands. After that, plasma C
By VD method, sputtering method, etc. = silicon oxide, silicon oxide,
A dielectric film 13 made of tantalum oxide or two or more layers of any of these is formed, and then l is deposited by sputtering or the like.
A transparent conductive thin film such as To is formed. Thereafter, unnecessary portions are removed by photoetching or the like to form the pixel electrode 9.

In case 2, the pixel electrode 9 is overlapped with the dielectric 13 interposed therebetween so as to be located above the floating electrode I2, thereby forming a charge storage capacitor <1> 21.

Next, metal such as Cr or MO is deposited by sputtering or the like, and gate electrode line 2 and common electrode line 3 are formed by photoetching or the like. At this time, the common electrode line 3 is connected to the pixel electrode 9
The common electrode line 3, the dielectric film 13, and the floating electrode 12 form a charge storage capacitor (2) 22.

Next, a gate insulating film 4 made of silicon nitride or the like, a semiconductor layer 5 such as a hydrogenated amorphous silica layer 321, and an upper insulating film 6 are successively deposited by plasma CVD or the like.

Thereafter, the upper insulating film 6 is patterned, and a hydrogenated amorphous silicon n8 layer 7 is formed by plasma CVD or the like and patterned to form a contact hole between the pixel type ffL9 and the drain electrode 8. after that,
A conductive thin film such as AMo is deposited by sputtering or the like and patterned into the sos electrode line 1 and the drain electrode 8. moreover,
Unnecessary semiconductor layer 7 and semiconductor layer 5 are etched off by dry etching, and finally a silicon nitride film or silicon oxide film is deposited by plasma CVD or the like and patterned to form a protective film 10.

A liquid crystal display device is manufactured by sandwiching a display material 35 such as liquid crystal between the TFT array substrate thus formed and a counter electrode substrate 38 having transparent electrodes, color filters, etc.

In this embodiment, the pixel electrode 9 and the common electrode 3 are arranged side by side so as not to overlap, and the floating electrode 12 is provided with the pixel electrode 9 and the common electrode 3 interposed with the dielectric 113. Because of this configuration, charge storage capacitors (1) and (2) can be formed between the floating electrode 12 and the pixel electrode 9, and between the floating electrode 9 and the common electrode 3. Furthermore, by connecting these in series, the pixel electrode 9 and The common electrode 3 can be configured to be capacitively coupled. Therefore, even if a short-circuit defect occurs between the floating electrode 12 and the pixel electrode 9 or between the floating electrode 12 and the common electrode 3, the common electrode can be connected immediately. 12 and the drain electrode 8, and as a result, pixel defects due to shorting of the charge storage capacitor can be reduced.

In the above embodiment, a transparent conductive film is used as the floating electrode 12, but an opaque conductive film such as a metal film may be used as long as it does not interfere with display.
The PT structure may be a structure in which the upper insulating film 6 is not used as shown in FIGS. 4 and 5.

Further, in the above embodiment, the floating electrode 12 is first formed, and then the dielectric film 3, the pixel electrode 9, and the common electrode line 3 are sequentially formed. As shown in FIGS. 8 and 9, a pixel electrode 9 and a common electrode line 3 are formed, an insulating film 4 is formed, and a floating electrode 12 is formed, and a source electrode line 1 and a drain electrode line 8 are formed. In this case, they can be formed simultaneously using the same material. Furthermore, it is also possible to form the floating electrode 12 both above and below the pixel electrode 9 and the common electrode line 3.

Further, in the above embodiment, the floating electrode 12 is one piece, but the floating electrode 12 may be divided into a plurality of pieces as shown in FIGS. 10 and 11.

Next, the second invention will be explained with reference to a diagram which is an embodiment.

FIG. 12 is a plan configuration diagram showing one pixel of a TFT array substrate according to an embodiment of the second invention, FIG. 13 is a sectional view taken along line AA in FIG. 12, and FIG. 14 is a circuit configuration diagram in FIG. 12. It is a diagram. In the figure, the same reference numerals as in FIGS. 1 to 11 indicate the same parts. In this embodiment, the floating electrode 12 is also placed opposite to the gate electrode line 2A of the next stage with the dielectric film 13 interposed therebetween. charge holding capacity<3)2
It is characterized by forming 3.

Such a TFT array substrate is manufactured by the following steps.

First, a transparent conductive film such as ITO is deposited on a transparent insulating substrate 14 made of glass or the like by EB evaporation, and unnecessary portions of the transparent conductive film are removed by a method such as photoetching to form floating electrodes 12 in the form of islands. Next, a dielectric film 13 made of silicon nitride, silicon oxide, tantalum oxide, or two or more layers of any of these is formed by a plasma CVD method or a sputtering method.
form.

Thereafter, a transparent conductive thin film such as T◯ is formed by sputtering or the like, and the pixel electrode 9 is formed by etching or the like.

At this time, the pixel electrode 9 is connected to the floating electrode 1 with the dielectric 13 in between.
2 and overlap it so that it faces the charge holding capacitor (
1) Form 21.

Next, after depositing a metal such as Cr or Mo by sputtering or the like, the gate electrode line 2 and the common electrode line 3 are formed by etching or the like. In this case, the floating electrode 12, the common electrode line 3, and the gate electrode line 2A for the next pixel electrode are arranged so as to overlap with each other with the dielectric film 13 interposed therebetween.
As a result, a charge storage capacitor <2) 22 and a charge storage capacitor (3) 23 are formed.

Thereafter, a gate insulating film 4 such as silicon nitride, a semiconductor layer 5 such as 21 layers of hydrogenated amorphous silicon, and an upper insulating film 6 are successively deposited by plasma CVD or the like.
After patterning the upper insulating film 6, a hydrogenated amorphous/wolfberry 201 layer 7 is formed by plasma CVD or the like, and a contact hole between the pixel electrode 9 and the drain electrode 10 is formed by patterning. After that, a conductive thin film such as AI or MO is deposited by sputtering or the like, and patterned into the source electrode line 1 and drain electrode 8, and unnecessary semiconductor n4 layer 7 and semiconductor 1 layer 5 are etched off by dry etching. Finally, a silicon nitride film, a silicon oxide film, or the like is deposited by plasma CVD or the like, and patterned to form a protective film 10.

In this embodiment, the pixel electrode 9 is arranged in parallel with the gate electrode 2A for the next pixel electrode so as not to overlap, and the floating electrode 12 spanning the pixel electrode 9 and the gate electrode 2 is provided with the dielectric 13 interposed therebetween. By providing this, charge capacitances (1) and (3) are formed by the floating electrode 12 and the pixel electrode 9 and the floating electrode 12 and the gate electrode 2A,
The structure is such that the pixel electrode 9 and the gate electrode 2A are capacitively coupled by these capacitive couplings. For this reason, floating electrode 1
Even if a short-circuit defect occurs between the gate electrode 2 and the pixel electrode 9 or between the floating electrode 12 and the gate electrode 2, there is no immediate short-circuit between the gate electrode 2 and the pixel electrode 9.
Therefore, the occurrence of pixel defects due to short circuits can be suppressed.

In the above embodiment, the gate I electrode overlapping with the floating electrode 12 is for the next pixel @ electrode, but
It may be configured to overlap the gate electrode for the previous pixel electrode. Also.

Although the overlap between the floating electrode 12 and the common electrode 3 was made smaller to make the charge retention capacitance (2>22) smaller,
The overlapping portion may be formed to be large, and furthermore, as shown in FIGS. 15, 16, and 17, the floating electrode 1
2 may be divided into two to provide a charge retention capacitor with the common electrode 3. Furthermore, the floating electrode 12 may be divided into a plurality of parts as shown in FIGS. 18 and 19.

Furthermore, in the above embodiment, after forming the floating electrode 12,
Although the method for forming the dielectric film 13 has been described, the second
As shown in Figure 0 and Figure 21, the floating i! [Electrode] 2 is formed using a source/drain electrode material, and a charge retention capacitor H) 22 and a charge retention capacitor (3) 23 are formed by the floating electrode 12, gate electrode line 2A, pixel electrode 9, and gate insulating film 4. You can also do that. Furthermore, it is also possible to form floating electrodes both above and below the pixel electrode 9 and the gate electrode line 2.

[Effects of the Invention] As described above, according to the second invention, since the common electrode line or the gate electrode line and the pixel electrode are arranged side by side, and the floating electrode is provided between them and the dielectric,
It is possible to suppress short-circuit defects occurring between the common electrode line or the gate electrode line and the pixel electrode. Furthermore, since the charge storage capacitor is formed of a plurality of capacitors, the function as a charge storage capacitor can be maintained even if one of the capacitors is short-circuited.

[Brief explanation of the drawing]

FIG. 1 is a plan configuration diagram showing a TFT array substrate used in a liquid crystal display device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A in FIG. 1, and FIG. Circuit configuration diagrams, FIGS. 4, 6, and 8 are configuration diagrams showing TFT array substrates of other embodiments, FIGS. 5, 7, and 9.
10 and 11 are circuit diagrams and configuration diagrams showing other embodiments of the present invention, and FIGS. 12 and 13 are sectional views taken along line A-A in FIGS. Figure 14 is the second
FIG.
6 and 17 are plan configuration diagrams, cross-sectional views, and circuit diagrams showing TFT array substrates of other embodiments, and FIGS. 18 and 1
9 is a block diagram and a circuit diagram showing another embodiment, FIGS. 20 and 21 are a block diagram and a cross-sectional diagram showing another embodiment, and FIG. 22 is a diagram showing one of the TFT array substrates in a conventional liquid crystal display device. FIG. 23 is a planar configuration diagram showing pixels, FIG. 23 is a sectional view taken along line AA in FIG. 22, and FIG. 24 is an equivalent circuit diagram in FIG. 22. 1 Source electrode line, 2 Gate electrode line, 3 Common electrode line, 4 Gate insulating film, 5 Semiconductor i layer, 6 Upper insulating film, 7 Semiconductor n layer, 8 Drain electrode, 9 Pixel electrode, IO protective film, 12 Floating electrode, 13・Dielectric film, I
4.Transparent insulating substrate, 15-TFT, 16...Gate-drain parasitic capacitance, 17. Light shielding film, 18. Charge storage capacitor, 21.Charge storage capacitor (1>, 22. Charge storage capacitor (2)
), 23 charge retention capacitor (3), 35 liquid crystal, 38 counter electrode. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A plurality of common electrode lines and a plurality of gate electrode lines arranged in parallel on a transparent insulating substrate, a plurality of source electrode lines formed to intersect the common electrode line and the gate electrode line, and the above gate electrode line A TFT array substrate comprising a thin film transistor provided near the intersection of the source electrode line and the source electrode line, a pixel electrode connected to the thin film transistor, a counter electrode substrate provided opposite to the TFT array substrate, and a counter electrode substrate. In a liquid crystal display device comprising a liquid crystal display material sandwiched between the TFT array substrates, the common electrode line or the gate electrode line and the pixel electrode are arranged in parallel, and a floating electrode is provided between these electrodes and a dielectric material. A liquid crystal display device characterized in that it is configured to include electrodes.