JP3031664B2 - TFT array substrate and liquid crystal display device using the same - Google Patents
TFT array substrate and liquid crystal display device using the sameInfo
- Publication number
- JP3031664B2 JP3031664B2 JP3088496A JP3088496A JP3031664B2 JP 3031664 B2 JP3031664 B2 JP 3031664B2 JP 3088496 A JP3088496 A JP 3088496A JP 3088496 A JP3088496 A JP 3088496A JP 3031664 B2 JP3031664 B2 JP 3031664B2
- Authority
- JP
- Japan
- Prior art keywords
- storage capacitor
- line
- signal lines
- scanning signal
- capacitor electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【０００１】[0001]
【発明の属する技術分野】本発明は、薄膜トランジスタ
を画素電極とともに多数配列したアクティブマトリクス
型液晶表示装置に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to an active matrix type liquid crystal display device in which a large number of thin film transistors are arranged together with pixel electrodes.
【０００２】[0002]
【従来の技術】ＴＦＴアレイを用いた液晶表示装置で
は、透明絶縁性基板上に直交するように形成されたゲー
ト電極線とソース電極線の各マトリクスの交点に設けら
れた薄膜トランジスタ（以下ＴＦＴと称する）のスイッ
チング機能により、各画素に画像情報が伝達されるが、
ＴＦＴがオフになり、画像情報が画素部に保持される時
間中に自己放電あるいはＴＦＴのリーク電流が原因で画
像信号が損なわれてしまうという問題が生じる。この問
題を解決するための対策としては、個々の画素に保持容
量を設ける方法がある。保持容量の設置方法としては、
ＩＥＥＥ，Trans.Electron Devices ED-20(1973)pp.9
95〜1001に記載される方法が簡便であり、従来より頻繁
に用いられている。この方法は、保持容量を個々の画素
内で隣接するゲート電極線と画素電極の間に形成するも
のである。ただし、この方法では保持容量の電極とゲー
ト電極線間の接続が個々の画素内で行われているため、
開口率向上の阻害要因となっている。また、ゲート電極
線に対して寄生容量となっているため、ゲート信号遅延
の要因となっていた。2. Description of the Related Art In a liquid crystal display device using a TFT array, a thin film transistor (hereinafter referred to as a TFT) provided at an intersection of each matrix of gate electrode lines and source electrode lines formed orthogonally on a transparent insulating substrate. ), The image information is transmitted to each pixel.
There is a problem that the image signal is damaged due to self-discharge or a leak current of the TFT during a time when the TFT is turned off and the image information is held in the pixel portion. As a measure to solve this problem, there is a method of providing a storage capacitor for each pixel. As a method of setting the storage capacity,
IEEE, Trans. Electron Devices ED-20 (1973) pp.9
The method described in 95-1001 is simple and has been used more frequently than before. In this method, a storage capacitor is formed between an adjacent gate electrode line and a pixel electrode in each pixel. However, in this method, the connection between the electrode of the storage capacitor and the gate electrode line is performed in each pixel,
This is a hindrance to improving the aperture ratio. In addition, the parasitic capacitance with respect to the gate electrode line causes a gate signal delay.
【０００３】そこで、最近では上記の方法に代わり、各
画素共通の保持容量電極線を設ける方法が採用されるよ
うになった。図７は、特開平５−１０７５５９号公報に
示される従来の薄膜トランジスタアレイの画素部の等価
回路図である。図において、１はゲート電極線、２はソ
ース電極線、３はＴＦＴ、４は対向電極、５は液晶容
量、６は保持容量、７は画素電極、８は共通配線である
保持容量電極線をそれぞれ示す。表示部は、ｍ本のゲー
ト電極線１とｎ本のソース電極線２が直交して配置さ
れ、ｍ×ｎ個の表示画素に分割されている。本例では、
保持容量の電極として走査線方向に一本の共通の保持容
量電極線８をゲート電極線１と平行に配置する共通配線
方式を採用しており、ゲート電極線１と保持容量電極線
８との接続を表示面外部で行っているので画素の開口率
を下げることなく、ゲート電極線１に対して寄生容量と
なりにくい。Therefore, recently, a method of providing a common storage capacitor electrode line for each pixel has been adopted instead of the above method. FIG. 7 is an equivalent circuit diagram of a pixel portion of a conventional thin film transistor array disclosed in Japanese Patent Application Laid-Open No. 5-107559. In the figure, 1 is a gate electrode line, 2 is a source electrode line, 3 is a TFT, 4 is a counter electrode, 5 is a liquid crystal capacitor, 6 is a storage capacitor, 7 is a pixel electrode, and 8 is a storage capacitor electrode line which is a common wiring. Shown respectively. In the display section, m gate electrode lines 1 and n source electrode lines 2 are arranged orthogonally, and are divided into m × n display pixels. In this example,
A common wiring method is adopted in which one common storage capacitor electrode line 8 is arranged in the scanning line direction in parallel with the gate electrode line 1 as an electrode of the storage capacitor. Since the connection is made outside the display surface, the capacitance is less likely to be a parasitic capacitance with respect to the gate electrode line 1 without reducing the aperture ratio of the pixel.
【０００４】[0004]
【発明が解決しようとする課題】以上のように構成され
た共通配線方式による保持容量電極を採用したＴＦＴア
レイにおいては、以下に示すような問題点がある。図８
は、従来の共通配線方式によるＴＦＴアレイの画素部の
平面図である。図において、２３はゲート電極、２８は
ソース・ドレイン電極、３０は異物等による層間ショー
ト部、３１は断線部をそれぞれ示す。図に示すように、
従来の共通配線方式では、異物、膜欠損等のプロセス要
因で例えばｋ本目の保持容量電極線８が断線した場合、
および他の導電膜層と短絡した場合、ｋ本目の保持容量
電極線８により容量付加されるべき画素全てにおいて画
素信号の品質が損なわれてしまうという問題点があり、
歩留まり低下の大きな要因となっていた。The TFT array employing the storage capacitor electrodes of the common wiring system configured as described above has the following problems. FIG.
FIG. 2 is a plan view of a pixel portion of a TFT array using a conventional common wiring method. In the figure, 23 is a gate electrode, 28 is a source / drain electrode, 30 is an interlayer short-circuit portion due to foreign matter or the like, and 31 is a disconnection portion. As shown in the figure,
In the conventional common wiring method, for example, when the k-th storage capacitor electrode line 8 is disconnected due to a process factor such as a foreign substance or a film defect,
And when short-circuiting with another conductive film layer, there is a problem that the quality of the pixel signal is impaired in all the pixels to which the capacitance is to be added by the k-th storage capacitor electrode line 8,
This was a major factor in lowering the yield.
【０００５】本発明は以上のような問題点を解消するた
めになされたもので、異物、膜欠損等のプロセス要因に
よる層間短絡および断線等によって歩留まりの低下を生
じにくい共通配線方式の保持容量電極を備えた高開口率
のＴＦＴアレイおよびこれを用いた液晶表示装置を提供
することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a common wiring type storage capacitor electrode which is unlikely to cause a decrease in yield due to interlayer short-circuiting and disconnection due to process factors such as foreign matter and film defects. It is an object of the present invention to provide a TFT array having a high aperture ratio and a liquid crystal display device using the same.
【０００６】[0006]
【課題を解決するための手段】この発明に係わるＴＦＴ
アレイ基板は、透明絶縁性基板上に複数本形成された走
査用信号線と、走査用信号線と交差する複数本のデータ
用信号線と、走査用信号線とデータ用信号線の各交点に
設けられた薄膜トランジスタと、薄膜トランジスタに接
続された透明導電膜よりなる画素電極と、走査用信号線
と平行に配置され、少なくとも画素電極の一部との間に
保持容量絶縁膜を挟んで保持容量を形成する走査線方向
の一連の画素に共通の保持容量電極線と、この保持容量
電極線と平行に配置され、各画素毎に近接の保持容量電
極線との接続部を有し、走査用信号線の上部または下部
に絶縁膜を挟んで形成された保持容量電極冗長線を備え
たものである。また、保持容量電極線と平行に配置さ
れ、各画素毎に近接の上記保持容量電極線との接続部を
有するとともに、上記保持容量電極線との間に前記走査
用信号線を挟んだ位置に配置された保持容量電極冗長線
を備えたものである。 SUMMARY OF THE INVENTION A TFT according to the present invention
The array substrate has a plurality of scanning signal lines formed on a transparent insulating substrate, a plurality of data signal lines intersecting with the scanning signal lines, and an intersection of the scanning signal lines and the data signal lines. The provided thin film transistor, a pixel electrode made of a transparent conductive film connected to the thin film transistor, and a storage capacitor which is arranged in parallel with the scanning signal line and has a storage capacitor insulating film interposed between at least a part of the pixel electrode. A storage capacitor electrode line common to a series of pixels in the scanning line direction to be formed, and a connection portion between the storage capacitor electrode line arranged in parallel with the storage capacitor electrode line and a close storage capacitor electrode line for each pixel, and a scanning signal Top or bottom of line
With a storage capacitor electrode redundant line formed with an insulating film
Is the ash. Also , it is arranged in parallel with the storage capacitor electrode line.
In each pixel, a connection portion with the adjacent storage capacitor electrode line is formed for each pixel.
And the scanning between the storage capacitor electrode line
Storage capacitor electrode redundant line placed at the position sandwiching the signal line for
It is provided with.
【０００７】また、透明絶縁性基板上に複数本形成され
た走査用信号線と、走査用信号線と交差する複数本のデ
ータ用信号線と、走査用信号線とデータ用信号線の各交
点に設けられた薄膜トランジスタと、薄膜トランジスタ
に接続された透明導電膜よりなる画素電極と、走査用信
号線と平行に配置され、少なくとも画素電極の一部との
間に保持容量絶縁膜を挟んで保持容量を形成する走査線
方向の一連の画素に共通の保持容量電極線と、この保持
容量電極線より各画素毎に伸びた突起部で構成されると
共に、走査用信号線と絶縁膜を介して電気的に接続しな
いように重なって配置され、必要に応じて走査用信号線
と短絡させ得るようにした保持容量電極冗長部を備えた
ものである。 Further, a plurality of scanning signal lines formed on a transparent insulating substrate, a plurality of data signal lines intersecting the scanning signal lines, and respective intersections of the scanning signal lines and the data signal lines. , A pixel electrode made of a transparent conductive film connected to the thin film transistor, and a storage capacitor which is disposed in parallel with the scanning signal line and has a storage capacitor insulating film interposed between at least a part of the pixel electrode. Is formed of a storage capacitor electrode line common to a series of pixels in the scanning line direction and a protrusion extending from the storage capacitor electrode line for each pixel, and electrically connected via a scanning signal line and an insulating film. Do not connect
Signal lines for scanning as necessary
And a storage capacitor electrode redundant section that can be short-circuited.
Things.
【０００８】また、透明絶縁性基板上に複数本形成され
た走査用信号線と、走査用信号線と交差する複数本のデ
ータ用信号線と、走査用信号線とデータ用信号線の各交
点に設けられた薄膜トランジスタと、薄膜トランジスタ
に接続された透明導電膜よりなる画素電極と、走査用信
号線と平行に配置され、少なくとも画素電極の一部との
間に保持容量絶縁膜を挟んで保持容量を形成する走査線
方向の一連の画素に共通の保持容量電極線と、走査用信
号線より各画素毎に伸びた突起部で構成されると共に、
保持容量電極線と絶縁膜を介して電気的に接続しないよ
うに重なって配置され、必要に応じて上記保持容量電極
線と短絡させうるようにした走査用信号線冗長部を備え
たものである。さらに、この発明に係る液晶表示装置
は、上記いずれかのＴＦＴアレイ基板と、透明電極およ
びカラーフィルタ等を有する対向電極基板との間に液晶
が配置されているものである。Further, a plurality of scanning signal lines formed on a transparent insulating substrate, a plurality of data signal lines intersecting with the scanning signal lines, and respective intersections of the scanning signal lines and the data signal lines. , A pixel electrode made of a transparent conductive film connected to the thin film transistor, and a storage capacitor which is disposed in parallel with the scanning signal line and has a storage capacitor insulating film interposed between at least a part of the pixel electrode. And a storage capacitor electrode line common to a series of pixels in the scanning line direction, and a projection extending for each pixel from the scanning signal line, and
Do not electrically connect to the storage capacitor electrode line via the insulating film .
Placed on top of each other, if necessary
Equipped with a scanning signal line redundant section that can be short-circuited with the line
Is the ash. Further, the liquid crystal display device according to the present invention are those which liquid crystal is disposed between the counter electrode substrate having the any one of the TFT array substrate, a transparent electrode and a color filter or the like.
【０００９】[0009]
【発明の実施の形態】 実施の形態１．図１は、本発明の実施の形態１である液
晶表示装置のＴＦＴアレイの等価回路図、図２は本実施
の形態によるＴＦＴアレイの画素部の構造を示す断面
図、図３は本実施の形態によるＴＦＴアレイ画素部の平
面図である。図において、１は走査用信号線であるゲー
ト電極線、２はデータ用信号線であるソース電極線、３
はＴＦＴ、４は対向電極、５は液晶容量、６は保持容
量、７は画素電極、８は走査線方向の各画素に共通の保
持容量電極線、９は保持容量電極冗長線、２１は透明絶
縁性基板、２２は保持容量絶縁膜、２３はゲート電極、
２４は層間絶縁膜、２５はｉ−アモルファスシリコン
層、２６は絶縁膜層、２７はｎ−アモルファスシリコン
層、２８はソース・ドレイン電極、２９は保護膜をそれ
ぞれ示す。保持容量電極線８は、ゲート電極線１と近接
して平行に設けられており、少なくとも画素電極７の一
部との間に保持容量絶縁膜２２を挟んで保持容量を形成
し、表示部の外側の周辺部で近接のゲート電極線１と接
続されている。また、本実施の形態では、保持容量電極
冗長線９の設置による開口率の低下が生じないように、
保持容量電極冗長線９をゲート電極線１およびゲート電
極２３の真下に絶縁膜を挟んで形成している。BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1 FIG. 1 is an equivalent circuit diagram of a TFT array of the liquid crystal display device according to the first embodiment of the present invention, FIG. 2 is a cross-sectional view showing a structure of a pixel portion of the TFT array according to the present embodiment, and FIG. It is a top view of the TFT array pixel part by a form. In the figure, 1 is a gate electrode line which is a scanning signal line, 2 is a source electrode line which is a data signal line, 3
Is a TFT, 4 is a counter electrode, 5 is a liquid crystal capacitor, 6 is a storage capacitor, 7 is a pixel electrode, 8 is a storage capacitor electrode line common to each pixel in the scanning line direction, 9 is a storage capacitor electrode redundant line, and 21 is transparent. An insulating substrate, 22 a storage capacitor insulating film, 23 a gate electrode,
Reference numeral 24 denotes an interlayer insulating film, 25 denotes an i-amorphous silicon layer, 26 denotes an insulating film layer, 27 denotes an n-amorphous silicon layer, 28 denotes source / drain electrodes, and 29 denotes a protective film. The storage capacitor electrode line 8 is provided close to and in parallel with the gate electrode line 1, forms a storage capacitor with a storage capacitor insulating film 22 interposed at least between the pixel electrode 7, and forms a storage capacitor. The outer peripheral portion is connected to the adjacent gate electrode line 1. Further, in the present embodiment, in order to prevent a decrease in aperture ratio due to the installation of the storage capacitor electrode redundant line 9,
The storage capacitor electrode redundant line 9 is formed immediately below the gate electrode line 1 and the gate electrode 23 with an insulating film interposed therebetween.
【００１０】本実施の形態におけるＴＦＴアレイの構造
および製造方法を図２について説明する。まず、透明絶
縁性基板２１上に保持容量電極線８および保持容量電極
冗長線９を堆積しパターニングを行う。保持容量電極線
８および保持容量電極冗長線９は、各画素毎に接続箇所
が設けられている。また、この時、保持容量電極冗長線
９は、後に形成するゲート電極線１の真下にくるように
配置する。この上に、保持容量絶縁膜２２、ゲート電極
線１およびゲート電極２３、画素電極７、層間絶縁膜２
４を順に堆積し、パターニングする。次に、ｉ−アモル
ファスシリコン層２５、絶縁膜層２６、ｎ−アモルファ
スシリコン層２７を堆積し、パターニングしてチャネル
領域を形成した後、ソース・ドレイン電極２８を形成
し、保護膜２９を堆積しパターニングする。The structure and manufacturing method of the TFT array according to the present embodiment will be described with reference to FIG. First, the storage capacitor electrode line 8 and the storage capacitor electrode redundant line 9 are deposited on the transparent insulating substrate 21 and patterned. The storage capacitor electrode line 8 and the storage capacitor electrode redundant line 9 are provided with connection portions for each pixel. At this time, the storage capacitor electrode redundant line 9 is arranged so as to be directly below the gate electrode line 1 to be formed later. On this, the storage capacitor insulating film 22, the gate electrode line 1 and the gate electrode 23, the pixel electrode 7, the interlayer insulating film 2
4 are sequentially deposited and patterned. Next, after depositing and patterning an i-amorphous silicon layer 25, an insulating film layer 26, and an n-amorphous silicon layer 27 to form a channel region, a source / drain electrode 28 is formed, and a protective film 29 is deposited. Perform patterning.
【００１１】図３は、本実施の形態による共通配線方式
のＴＦＴアレイの画素部を示す平面図である。図におい
て、３０は異物等により生じた層間ショート部、３１は
プロセストラブル等による保持容量電極線８の断線部を
示す。本実施の形態によるＴＦＴアレイにおいては、共
通配線である保持容量電極線８に異物等により層間ショ
ートが発生した場合、図中ａ、ｂで示したショート発生
部３０の前後をレーザリペア等の装置を用いて切断し、
その部分を孤立させる。この場合にも、ショート発生部
３０の前後の接続部から、保持容量電極冗長線９を迂回
して、保持容量電極線８は電気的に接続を維持できる。
また、プロセストラブル等により保持容量電極線８が断
線した場合であっても、断線部３１の前後の接続部から
保持容量電極冗長線９を迂回して、保持容量電極線８は
電気的に接続を維持できる。FIG. 3 is a plan view showing a pixel portion of the TFT array of the common wiring system according to the present embodiment. In the figure, reference numeral 30 denotes an interlayer short-circuit portion caused by a foreign substance or the like, and 31 denotes a disconnection portion of the storage capacitor electrode line 8 due to a process trouble or the like. In the TFT array according to the present embodiment, when an interlayer short-circuit occurs due to foreign matter or the like in the storage capacitor electrode line 8 which is a common wiring, a device such as a laser repair is provided before and after the short-circuit generating portion 30 shown in FIGS. Cut using
Isolate that part. Also in this case, the storage capacitor electrode line 8 can electrically maintain the connection from the connection portions before and after the short-circuit generating portion 30, bypassing the storage capacitor electrode redundant line 9.
Further, even when the storage capacitor electrode line 8 is disconnected due to a process trouble or the like, the storage capacitor electrode line 8 is electrically connected to the connection portion before and after the disconnection portion 31, bypassing the storage capacitor electrode redundant line 9. Can be maintained.
【００１２】本実施の形態によれば、プロセストラブル
等により、一連の画素の共通配線である保持容量電極線
８の断線または層間ショート等が発生した場合でも、保
持容量電極冗長線９を迂回して電気的に接続を維持でき
るため、同一の保持容量電極線８に連なった画素全てが
保持特性不良等の影響を受けることなく、最小単位の欠
陥におさめることができるので、歩留まりの低下を抑制
でき、高開口率の期待できる共通配線方式の保持容量電
極を備えたＴＦＴアレイ基板およびこれを用いた液晶表
示装置を得ることが可能である。According to the present embodiment, even when the storage capacitor electrode line 8 which is a common wiring of a series of pixels is disconnected or an interlayer short circuit occurs due to a process trouble or the like, the storage capacitor electrode redundant line 9 is bypassed. Electrical connection can be maintained, so that all the pixels connected to the same storage capacitor electrode line 8 can be reduced to the minimum unit of defects without being affected by poor retention characteristics and the like, thereby suppressing a decrease in yield. It is possible to obtain a TFT array substrate having a common wiring type storage capacitor electrode which can be expected to have a high aperture ratio and a liquid crystal display device using the same.
【００１３】実施の形態２．図４は本発明の実施の形態
２であるＴＦＴアレイの画素部の平面図である。前述の
実施の形態１では、保持容量電極冗長線９をゲート電極
線１の真下に形成し、開口率の低下を抑制したが、本実
施の形態では、保持容量電極冗長線９をゲート電極線１
の真下を避け、ゲート電極線１を挟んで隣接する保持容
量電極線８と反対側になるように配置し、実施の形態１
で示した構造よりも寄生容量の減少を図るものである。
なお、図中同一または相当部分には同一符号を付し、説
明を省略する。Embodiment 2 FIG. FIG. 4 is a plan view of a pixel portion of the TFT array according to the second embodiment of the present invention. In the first embodiment described above, the storage capacitor electrode redundant line 9 is formed immediately below the gate electrode line 1 to suppress a decrease in the aperture ratio. However, in the present embodiment, the storage capacitor electrode redundant line 9 is connected to the gate electrode line. 1
Of the storage capacitor electrode line 8 adjacent to the storage capacitor electrode line 8 with the gate electrode line 1 interposed therebetween.
This is intended to reduce the parasitic capacitance as compared with the structure shown in FIG.
In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.
【００１４】本実施の形態におけるＴＦＴアレイの構造
および製造方法を以下に説明する。まず、透明絶縁性基
板２１上に保持容量電極線８および保持容量電極冗長線
９を堆積し、パターニングを行う。保持容量電極線８お
よび保持容量電極冗長線９は、各画素毎に接続箇所が設
けられている。この時、本実施の形態では、保持容量電
極冗長線９は、ゲート電極線１を挟んで隣接する保持容
量電極線８と反対側になるように配置する（図４）。以
下は、実施の形態１と同様に、図２に示すような保持容
量絶縁膜２２、ゲート電極線１およびゲート電極２３、
画素電極７、層間絶縁膜２４を順に堆積し、パターニン
グする。さらに、ｉ−アモルファスシリコン層２５、絶
縁膜層２６、ｎ−アモルファスシリコン層２７を堆積
し、パターニングしてチャネル領域を形成した後、ソー
ス・ドレイン電極２８を形成し、保護膜２９を堆積しパ
ターニングする。The structure and manufacturing method of the TFT array according to the present embodiment will be described below. First, the storage capacitor electrode line 8 and the storage capacitor electrode redundant line 9 are deposited on the transparent insulating substrate 21 and patterned. The storage capacitor electrode line 8 and the storage capacitor electrode redundant line 9 are provided with connection portions for each pixel. At this time, in this embodiment, the storage capacitor electrode redundant line 9 is arranged so as to be on the opposite side to the storage capacitor electrode line 8 adjacent to the gate electrode line 1 (FIG. 4). Hereinafter, similarly to the first embodiment, the storage capacitor insulating film 22, the gate electrode line 1, the gate electrode 23, and the like as shown in FIG.
The pixel electrode 7 and the interlayer insulating film 24 are sequentially deposited and patterned. Further, an i-amorphous silicon layer 25, an insulating film layer 26, and an n-amorphous silicon layer 27 are deposited and patterned to form a channel region. Then, source / drain electrodes 28 are formed, and a protective film 29 is deposited and patterned. I do.
【００１５】本実施の形態によるＴＦＴアレイにおいて
は、共通配線である保持容量電極線８に異物等により層
間ショートが発生した場合、図中ａ、ｂで示したショー
ト発生部３０の前後をレーザリペア等の装置を用いて切
断し、その部分を孤立させる。この場合にも、ショート
発生部３０の前後の接続部から、保持容量電極冗長線９
を迂回して、保持容量電極線８は電気的に接続を維持で
きる。また、プロセストラブル等により保持容量電極線
８が断線した場合であっても、断線部３１の前後の接続
部から、保持容量電極冗長線９を迂回して保持容量電極
線８は電気的に接続を維持できる。In the TFT array according to the present embodiment, when an interlayer short-circuit occurs due to foreign matter or the like in the storage capacitor electrode line 8 which is a common wiring, a laser repair is performed before and after the short-circuit generating portion 30 shown by a and b in FIG. And the like, and the part is isolated. In this case as well, the connection portion before and after the short-circuit generating portion 30 is connected to the storage capacitor electrode redundant line 9.
And the storage capacitor electrode line 8 can maintain the electrical connection. Further, even when the storage capacitor electrode line 8 is disconnected due to a process trouble or the like, the storage capacitor electrode line 8 is electrically connected to the connection portion before and after the disconnection portion 31 by bypassing the storage capacitor electrode redundant line 9. Can be maintained.
【００１６】本実施の形態によれば、プロセストラブル
等により、一連の画素の共通配線である保持容量電極線
８の断線または層間ショート等が発生した場合でも、保
持容量電極冗長線９を迂回して電気的に接続を維持でき
るため、同一の保持容量電極線８に連なった画素全てが
保持特性不良等の影響を受けることなく、最小単位の欠
陥におさめることができるので、歩留まりの低下を抑制
でき、さらに保持容量電極冗長線９をゲート電極線１の
真下を避けて形成したので、寄生容量の負担が少ない共
通配線方式の保持容量電極を備えたＴＦＴアレイ基板お
よび液晶表示装置を得ることが可能である。According to the present embodiment, even when the storage capacitor electrode line 8 which is a common wiring of a series of pixels is disconnected or an interlayer short circuit occurs due to a process trouble or the like, the storage capacitor electrode redundant line 9 is bypassed. Electrical connection can be maintained, so that all the pixels connected to the same storage capacitor electrode line 8 can be reduced to the minimum unit of defects without being affected by poor retention characteristics and the like, thereby suppressing a decrease in yield. In addition, since the storage capacitor electrode redundant line 9 is formed so as not to be directly under the gate electrode line 1, a TFT array substrate and a liquid crystal display device having a common wiring type storage capacitor electrode with less burden of parasitic capacitance can be obtained. It is possible.
【００１７】実施の形態３．図５は本発明の実施の形態
３であるＴＦＴアレイの画素部の平面図である。図にお
いて、１０は保持容量電極冗長部を示す。本実施の形態
では、画素毎に保持容量電極線８より垂直に伸びた突起
部より構成される保持容量電極冗長部１０をゲート電極
線１と一部が重なるように形成し、この重なりの部分を
レーザリペア等の手段で短絡させることにより、ゲート
電極線１と保持容量電極線８が接続できるようにしたも
のである。なお、保持容量電極冗長部１０は保持容量電
極線８より必ずしも垂直に伸びた突起部である必要はな
く、保持容量電極線８に対して傾斜して伸びた突起部で
あってもよい。また、図中同一または相当部分には同一
符号を付し、説明を省略する。Embodiment 3 FIG. 5 is a plan view of a pixel portion of the TFT array according to the third embodiment of the present invention. In the figure, reference numeral 10 denotes a storage capacitor electrode redundant portion. In this embodiment, the storage capacitor electrode redundant portion 10 composed of a projection extending vertically from the storage capacitor electrode line 8 for each pixel is formed so as to partially overlap the gate electrode line 1, and this overlapping portion is formed. Is short-circuited by means such as laser repair, so that the gate electrode line 1 and the storage capacitor electrode line 8 can be connected. Note that the storage capacitor electrode redundant portion 10 does not necessarily need to be a protrusion extending perpendicularly to the storage capacitor electrode line 8, and may be a protrusion extending obliquely with respect to the storage capacitor electrode line 8. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.
【００１８】本実施の形態におけるＴＦＴアレイの構造
および製造方法を以下に説明する。まず、透明絶縁性基
板２１上に保持容量電極線８および保持容量電極冗長部
１０を堆積し、パターニングを行う。この時、保持容量
電極冗長部１０は、画素毎に保持容量電極線８と交差し
て形成され、レーザリペア等の手段を用いてゲート電極
線１と短絡させた場合、ゲート電極線１と電気的に接続
可能な程度に一部が重なるように配置する（図５）。以
下は、実施の形態１と同様に、図２に示すような保持容
量絶縁膜２２、ゲート電極線１およびゲート電極２３、
画素電極７、層間絶縁膜２４を順に堆積し、パターニン
グする。さらに、ｉ−アモルファスシリコン層２５、絶
縁膜層２６、ｎ−アモルファスシリコン層２７を堆積
し、パターニングしてチャネル領域を形成した後、ソー
ス・ドレイン電極２８を形成し、保護膜２９を堆積しパ
ターニングする。The structure and manufacturing method of the TFT array according to the present embodiment will be described below. First, the storage capacitor electrode line 8 and the storage capacitor electrode redundant portion 10 are deposited on the transparent insulating substrate 21 and patterned. At this time, the storage capacitor electrode redundant portion 10 is formed so as to intersect the storage capacitor electrode line 8 for each pixel, and when the gate electrode line 1 is short-circuited by means such as laser repair, the storage capacitor electrode redundant portion 10 is electrically connected to the gate electrode line 1. They are arranged so that they partially overlap so that they can be connected to each other (FIG. 5). Hereinafter, similarly to the first embodiment, the storage capacitor insulating film 22, the gate electrode line 1, the gate electrode 23, and the like as shown in FIG.
The pixel electrode 7 and the interlayer insulating film 24 are sequentially deposited and patterned. Further, after depositing and patterning an i-amorphous silicon layer 25, an insulating film layer 26, and an n-amorphous silicon layer 27 to form a channel region, a source / drain electrode 28 is formed, and a protective film 29 is deposited and patterned. I do.
【００１９】本実施の形態によるＴＦＴアレイにおいて
は、共通配線である保持容量電極線８に異物等により層
間ショートが発生した場合、図中ａ、ｂで示したショー
ト発生部３０の前後をレーザリペア等の装置を用いて切
断し、その部分が孤立するようにした後、その前後の保
持容量電極冗長部１０をゲート電極線１と短絡すること
により、ゲート電極線１を迂回して保持容量電極線８は
電気的に接続を維持できる。また、プロセストラブル等
により保持容量電極線８が断線した場合、断線部３１の
前後の保持容量電極冗長部１０をレーザリペア等の手段
を用いてゲート電極線１と短絡することにより、ゲート
電極線１を迂回して保持容量電極線８は電気的に接続を
維持できる。In the TFT array according to the present embodiment, when an interlayer short circuit occurs due to a foreign substance or the like in the storage capacitor electrode line 8 which is a common wiring, laser repair is performed before and after the short generating section 30 shown by a and b in FIG. Then, the storage capacitor electrode redundant portion 10 is short-circuited to the gate electrode line 1 by cutting the storage capacitor electrode redundant portion 10 before and after the cut, thereby bypassing the gate electrode line 1 and cutting the storage capacitor electrode. The line 8 can maintain an electrical connection. When the storage capacitor electrode line 8 is disconnected due to a process trouble or the like, the storage capacitor electrode redundant portion 10 before and after the disconnection portion 31 is short-circuited with the gate electrode line 1 by using a means such as laser repair. 1, the storage capacitor electrode line 8 can maintain the electrical connection.
【００２０】本実施の形態によれば、プロセストラブル
等により、一連の画素の共通配線である保持容量電極線
８の断線または層間ショート等が発生した場合でも、保
持容量電極冗長部１０とゲート電極線１を接続すること
で、ゲート電極線１を迂回して電気的に接続を維持でき
るため、同一の保持容量電極線８に連なった画素全てが
保持特性不良等の影響を受けることなく、最小単位の欠
陥におさめることができるので、歩留まりの低下を抑制
でき、さらに冗長部分を短い突起のような形状にするこ
とで冗長線自体のプロセストラブルの発生を抑え、寄生
容量の負担が少ない共通配線方式の保持容量電極を備え
たＴＦＴアレイ基板および液晶表示装置を得ることが可
能である。According to this embodiment, even when the storage capacitor electrode line 8 which is a common line for a series of pixels is disconnected or an interlayer short circuit occurs due to a process trouble or the like, the storage capacitor electrode redundant portion 10 and the gate electrode By connecting the line 1, the connection can be maintained electrically bypassing the gate electrode line 1, so that all the pixels connected to the same storage capacitor electrode line 8 can be minimized without being affected by poor holding characteristics or the like. Since it can be reduced to unit defects, it is possible to suppress the reduction in yield, and furthermore, by making the redundant part like a short protrusion, the occurrence of process troubles in the redundant line itself is suppressed, and the common wiring with less burden of parasitic capacitance It is possible to obtain a TFT array substrate and a liquid crystal display device having a storage capacitor electrode of the system.
【００２１】実施の形態４．図６は本発明の実施の形態
４であるＴＦＴアレイの画素部の平面図である。図にお
いて、１１はゲート電極線冗長部を示す。本実施の形態
では、画素毎にゲート電極線１より垂直に伸びた突起部
より構成されるゲート電極線冗長部１１を保持容量電極
線８と一部が重なるように形成し、この重なりの部分を
レーザリペア等の手段で短絡させることにより、保持容
量電極線８とゲート電極線１が接続できるようにしたも
のである。なお、ゲート電極線冗長部１１はゲート電極
線１より必ずしも垂直に伸びた突起部である必要はな
く、ゲート電極線１に対して傾斜して伸びた突起部であ
ってもよい。また、図中同一または相当部分には同一符
号を付し、説明を省略する。Embodiment 4 FIG. FIG. 6 is a plan view of a pixel portion of a TFT array according to Embodiment 4 of the present invention. In the figure, reference numeral 11 denotes a gate electrode line redundant portion. In the present embodiment, a gate electrode line redundant portion 11 composed of a projection extending vertically from the gate electrode line 1 for each pixel is formed so as to partially overlap the storage capacitor electrode line 8, and this overlapping portion is formed. Is short-circuited by means such as laser repair, so that the storage capacitor electrode line 8 and the gate electrode line 1 can be connected. Note that the gate electrode line redundant portion 11 does not necessarily need to be a protrusion extending vertically from the gate electrode line 1, and may be a protrusion extending obliquely with respect to the gate electrode line 1. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.
【００２２】本実施の形態によるＴＦＴアレイの構造お
よび製造方法を以下に説明する。まず、透明絶縁性基板
２１上に保持容量電極線８を堆積し、パターニングを行
う。この上に、保持容量絶縁膜２２、ゲート電極線１、
ゲート電極２３およびゲート電極線冗長部１１を形成す
る。この時、ゲート電極線冗長部１１は、画素毎にゲー
ト電極線１と交差して形成され、レーザリペア等の手段
を用いて保持容量電極線８と短絡させた場合、保持容量
電極線８と電気的に接続可能な程度に一部が重なるよう
に形成する（図６）。以下は、実施の形態１と同様に、
図２に示すような画素電極７、層間絶縁膜２４を順に堆
積し、パターニングする。さらに、ｉ−アモルファスシ
リコン層２５、絶縁膜層２６、ｎ−アモルファスシリコ
ン層２７を堆積し、パターニングしてチャネル領域を形
成した後、ソース・ドレイン電極２８を形成し、保護膜
２９を堆積しパターニングする。The structure and manufacturing method of the TFT array according to the present embodiment will be described below. First, the storage capacitor electrode line 8 is deposited on the transparent insulating substrate 21 and patterned. On this, the storage capacitor insulating film 22, the gate electrode line 1,
The gate electrode 23 and the gate electrode line redundant portion 11 are formed. At this time, the gate electrode line redundant portion 11 is formed so as to intersect the gate electrode line 1 for each pixel, and when the storage capacitor electrode line 8 is short-circuited by means such as laser repair, It is formed so as to partially overlap so as to be electrically connectable (FIG. 6). The following is similar to the first embodiment,
The pixel electrode 7 and the interlayer insulating film 24 as shown in FIG. 2 are sequentially deposited and patterned. Further, an i-amorphous silicon layer 25, an insulating film layer 26, and an n-amorphous silicon layer 27 are deposited and patterned to form a channel region. Then, source / drain electrodes 28 are formed, and a protective film 29 is deposited and patterned. I do.
【００２３】本実施の形態によるＴＦＴアレイにおいて
は、共通配線である保持容量電極線８に異物等により層
間ショートが発生した場合、図中ａ、ｂで示したショー
ト発生部３０の前後をレーザリペア等の装置を用いて切
断し、その部分が孤立するようにした後、その前後のゲ
ート電極線冗長部１１を保持容量電極線８と短絡するこ
とにより、ゲート電極線１を迂回して保持容量電極線８
は電気的に接続を維持できる。また、プロセストラブル
等により保持容量電極線８が断線した場合、断線部３１
の前後のゲート電極線冗長部１１をレーザリペア等の手
段を用いて保持容量電極線８と短絡することにより、ゲ
ート電極線１を迂回して保持容量電極線８は電気的に接
続を維持できる。In the TFT array according to the present embodiment, when an interlayer short-circuit occurs due to a foreign substance or the like in the storage capacitor electrode line 8 which is a common wiring, a laser repair is performed before and after the short-circuit generating portion 30 shown in FIGS. And the like, and the portion is isolated, and then the gate electrode line redundant portion 11 before and after the portion is short-circuited with the storage capacitor electrode line 8, thereby bypassing the gate electrode line 1 and holding the storage capacitor. Electrode wire 8
Can maintain an electrical connection. When the storage capacitor electrode line 8 is disconnected due to a process trouble or the like, the disconnection portion 31
Is short-circuited to the storage capacitor electrode line 8 by means of laser repair or the like before and after the storage capacitor electrode line 8 can bypass the gate electrode line 1 and maintain the electrical connection. .
【００２４】本実施の形態によれば、プロセストラブル
等により、一連の画素の共通配線である保持容量電極線
８の断線または層間ショート等が発生した場合でも、ゲ
ート電極線冗長部１１と保持容量電極線８を接続するこ
とで、ゲート電極線１を迂回して電気的に接続を維持で
きるため、同一の保持容量電極線８に連なった画素全て
が保持特性不良等の影響を受けることなく、最小単位の
欠陥におさめることができるので、歩留まりの低下を抑
制できる。また、冗長部分を短い突起のような形状にす
ることで冗長線自体のプロセストラブルの発生を抑え、
寄生容量の負担が少ない共通配線方式の保持容量電極を
備えたＴＦＴアレイ基板および液晶表示装置を得ること
が可能である。さらに、ゲート電極線冗長部１１は、ゲ
ート電極線１のプロセストラブルに対する冗長としても
使用することができる。According to the present embodiment, even when a disconnection or interlayer short-circuit of the storage capacitor electrode line 8 which is a common wiring of a series of pixels occurs due to a process trouble or the like, the gate electrode line redundant portion 11 and the storage capacitor By connecting the electrode lines 8, the connection can be maintained electrically bypassing the gate electrode line 1, so that all the pixels connected to the same storage capacitor electrode line 8 are not affected by poor holding characteristics or the like. Since defects can be reduced to the minimum unit, a decrease in yield can be suppressed. In addition, by making the redundant part a shape like a short projection, the occurrence of process trouble on the redundant line itself is suppressed,
It is possible to obtain a TFT array substrate and a liquid crystal display device provided with a common wiring type storage capacitor electrode with less burden of parasitic capacitance. Further, the gate electrode line redundant portion 11 can be used as a redundancy for a process trouble of the gate electrode line 1.
【００２５】なお、上記実施の形態１〜４ではいずれも
保持容量電極線８、保持容量電極冗長線９および保持容
量電極冗長部１０等をゲート電極線１よりも下層に形成
したが、適用デバイス構造によりゲート電極線１より上
層に形成してもよく、同様の効果が得られる。In each of the first to fourth embodiments, the storage capacitor electrode line 8, the storage capacitor electrode redundant line 9, the storage capacitor electrode redundant portion 10, and the like are formed below the gate electrode line 1. Depending on the structure, it may be formed in a layer above the gate electrode line 1, and the same effect is obtained.
【図１】 この発明の実施の形態１であるＴＦＴアレイ
の等価回路図である。FIG. 1 is an equivalent circuit diagram of a TFT array according to a first embodiment of the present invention.
【図２】 この発明の実施の形態１であるＴＦＴアレイ
画素部の部分断面図である。FIG. 2 is a partial sectional view of a TFT array pixel portion according to the first embodiment of the present invention;
【図３】 この発明の実施の形態１であるＴＦＴアレイ
画素部の平面図である。FIG. 3 is a plan view of a TFT array pixel portion according to the first embodiment of the present invention;
【図４】 この発明の実施の形態２であるＴＦＴアレイ
画素部の平面図である。FIG. 4 is a plan view of a TFT array pixel portion according to a second embodiment of the present invention.
【図５】 この発明の実施の形態３であるＴＦＴアレイ
画素部の平面図である。FIG. 5 is a plan view of a TFT array pixel portion according to a third embodiment of the present invention.
【図６】 この発明の実施の形態４であるＴＦＴアレイ
画素部の平面図である。FIG. 6 is a plan view of a TFT array pixel portion according to a fourth embodiment of the present invention.
【図７】 従来の共通配線方式のＴＦＴアレイの等価回
路図である。FIG. 7 is an equivalent circuit diagram of a conventional common wiring type TFT array.
【図８】 従来の共通配線方式のＴＦＴアレイ画素部の
平面図である。FIG. 8 is a plan view of a conventional common wiring type TFT array pixel portion.
１ ゲート電極線、２ ソース電極線、３ 薄膜トラン
ジスタ（ＴＦＴ）、４ 対向電極、５ 液晶容量、６
保持容量、７ 画素電極、８ 保持容量電極線、９ 保
持容量電極冗長線、１０ 保持容量電極冗長部、１１
ゲート電極線冗長部、２１ 透明絶縁性基板、２２ 保
持容量絶縁膜、２３ ゲート電極、２４ 層間絶縁膜、
２５ ｉ−アモルファスシリコン層、２６ 絶縁膜層、
２７ ｎ−アモルファスシリコン層、２８ ソース・ド
レイン電極、２９ 保護膜、３０ 異物等による層間シ
ョート部、３１ 断線部。1 gate electrode line, 2 source electrode line, 3 thin film transistor (TFT), 4 counter electrode, 5 liquid crystal capacitance, 6
Storage capacitor, 7 pixel electrode, 8 storage capacitor electrode line, 9 storage capacitor electrode redundant line, 10 storage capacitor electrode redundant section, 11
Gate electrode line redundant portion, 21 transparent insulating substrate, 22 storage capacitor insulating film, 23 gate electrode, 24 interlayer insulating film,
25 i-amorphous silicon layer, 26 insulating film layer,
27 n-amorphous silicon layer, 28 source / drain electrodes, 29 protective film, 30 interlayer short-circuit part due to foreign matter, 31 disconnection part.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平３−141325（ＪＰ，Ａ) 特開 平２−310536（ＪＰ，Ａ) 特開 平５−289106（ＪＰ，Ａ) 特開 平５−107559（ＪＰ，Ａ) 特開 平３−59542（ＪＰ，Ａ) 特開 平３−77922（ＪＰ，Ａ) 特開 平４−265945（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) G02F 1/136 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-141325 (JP, A) JP-A-2-310536 (JP, A) JP-A-5-289106 (JP, A) JP-A-5-289106 107559 (JP, A) JP-A-3-59542 (JP, A) JP-A-3-77922 (JP, A) JP-A-4-265945 (JP, A) (58) Fields investigated (Int. 7 , DB name) G02F 1/136
Claims (5)
査用信号線、 上記走査用信号線と交差する複数本のデータ用信号線、 上記走査用信号線とデータ用信号線の各交点に設けられ
た薄膜トランジスタ、 上記薄膜トランジスタに接続された透明導電膜よりなる
画素電極、 上記走査用信号線と平行に配置され、少なくとも上記画
素電極の一部との間に保持容量絶縁膜を挟んで保持容量
を形成する走査線方向の一連の画素に共通の保持容量電
極線、 この保持容量電極線と平行に配置され、各画素毎に近接
の上記保持容量電極線との接続部を有し、走査用信号線
の上部または下部に絶縁膜を挟んで形成された保持容量
電極冗長線を備えたことを特徴とするＴＦＴアレイ基
板。1. A plurality of scanning signal lines formed on a transparent insulating substrate, a plurality of data signal lines intersecting with the scanning signal lines, and respective intersections of the scanning signal lines and the data signal lines. A pixel electrode made of a transparent conductive film connected to the thin film transistor, disposed in parallel with the scanning signal line, and held with a storage capacitor insulating film interposed between at least a part of the pixel electrode. A storage capacitor electrode line common to a series of pixels in a scanning line direction forming a capacitor, arranged in parallel with the storage capacitor electrode line, each pixel has a connection portion with the adjacent storage capacitor electrode line , Signal line
Storage capacitor formed above or below the insulator with an insulating film interposed
A TFT array substrate comprising an electrode redundant line .
査用信号線、 上記走査用信号線と交差する複数本のデータ用信号線、 上記走査用信号線とデータ用信号線の各交点に設けられ
た薄膜トランジスタ、 上記薄膜トランジスタに接続された透明導電膜よりなる
画素電極、 上記走査用信号線と平行に配置され、少なくとも上記画
素電極の一部との間に保持容量絶縁膜を挟んで保持容量
を形成する走査線方向の一連の画素に共通の保持容量電
極線、 この保持容量電極線と平行に配置され、各画素毎に近接
の上記保持容量電極線との接続部を有するとともに、上
記保持容量電極線との間に前記走査用信号線を挟んだ位
置に配置された保持容量電極冗長線を備えたことを特徴
とするＴＦＴアレイ基板。2. A plurality of scanning signal lines formed on a transparent insulating substrate, a plurality of data signal lines intersecting with the scanning signal lines, and respective intersections of the scanning signal lines and the data signal lines. A pixel electrode made of a transparent conductive film connected to the thin film transistor, disposed in parallel with the scanning signal line, and held with a storage capacitor insulating film interposed between at least a part of the pixel electrode. A storage capacitor electrode line common to a series of pixels in the scanning line direction forming a capacitor, arranged in parallel with the storage capacitor electrode line, each pixel having a connection portion with the adjacent storage capacitor electrode line ,
Between the storage capacitor electrode line and the scanning signal line.
Characterized by having a storage capacitor electrode redundant line arranged in
TF T array substrate to be.
査用信号線、 上記走査用信号線と交差する複数本のデータ用信号線、 上記走査用信号線とデータ用信号線の各交点に設けられ
た薄膜トランジスタ、 上記薄膜トランジスタに接続された透明導電膜よりなる
画素電極、 上記走査用信号線と平行に配置され、少なくとも上記画
素電極の一部との間に保持容量絶縁膜を挟んで保持容量
を形成する走査線方向の一連の画素に共通の保持容量電
極線、 この保持容量電極線より各画素毎に伸びた突起部で構成
されると共に、上記走査用信号線と絶縁膜を介して電気
的に接続しないように重なって配置され、必要に応じて
上記走査用信号線と短絡させ得るようにした保持容量電
極冗長部を備えたことを特徴とするＴＦＴアレイ基板。3. A plurality of scanning signal lines formed on a transparent insulating substrate, a plurality of data signal lines intersecting with the scanning signal lines, and respective intersections of the scanning signal lines and the data signal lines. A pixel electrode made of a transparent conductive film connected to the thin film transistor, disposed in parallel with the scanning signal line, and held with a storage capacitor insulating film interposed between at least a part of the pixel electrode. A storage capacitor electrode line common to a series of pixels in a scanning line direction forming a capacitor, a projection portion extending for each pixel from the storage capacitor electrode line, and via a scanning signal line and an insulating film. Electricity
Are placed so that they do not connect
TFT array substrate, comprising the hold capacitor electrode redundant part which is adapted capable of short-circuiting between the scanning signal lines.
査用信号線、 上記走査用信号線と交差する複数本のデータ用信号線、 上記走査用信号線とデータ用信号線の各交点に設けられ
た薄膜トランジスタ、 上記薄膜トランジスタに接続された透明導電膜よりなる
画素電極、 上記走査用信号線と平行に配置され、少なくとも上記画
素電極の一部との間に保持容量絶縁膜を挟んで保持容量
を形成する走査線方向の一連の画素に共通の保持容量電
極線、 上記走査用信号線より各画素毎に伸びた突起部で構成さ
れると共に、上記保持容量電極線と絶縁膜を介して電気
的に接続しないように重なって配置され、必要に応じて
上記保持容量電極線と短絡させうるようにした走査用信
号線冗長部を備えたことを特徴とするＴＦＴアレイ基
板。4. A plurality of scanning signal lines formed on a transparent insulating substrate, a plurality of data signal lines intersecting with the scanning signal lines, and respective intersections of the scanning signal lines and the data signal lines. A pixel electrode made of a transparent conductive film connected to the thin film transistor, disposed in parallel with the scanning signal line, and held with a storage capacitor insulating film interposed between at least a part of the pixel electrode. common storage capacitor electrode line to a series of pixels in the scanning direction to form a capacitor, with consists of projections extending to each pixel from the scanning signal lines, via the storage capacitor electrode lines and the insulating film Electricity
Are placed so that they do not connect
A scanning signal that can be short-circuited with the storage capacitor electrode line
TFT array substrate, wherein the this with the Route redundancy portion.
載のＴＦＴアレイ基板と、透明電極およびカラーフィル
タ等を有する対向電極基板との間に液晶が配置されてい
ることを特徴とする液晶表示装置。5. A TFT array substrate according to claim 1 to claim 4, whichever is paragraph (1) that the liquid crystal is disposed between the counter electrode substrate having a transparent electrode and a color filter, etc. Characteristic liquid crystal display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3088496A JP3031664B2 (en) | 1996-02-19 | 1996-02-19 | TFT array substrate and liquid crystal display device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3088496A JP3031664B2 (en) | 1996-02-19 | 1996-02-19 | TFT array substrate and liquid crystal display device using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09222615A JPH09222615A (en) | 1997-08-26 |
| JP3031664B2 true JP3031664B2 (en) | 2000-04-10 |
Family
ID=12316169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3088496A Expired - Fee Related JP3031664B2 (en) | 1996-02-19 | 1996-02-19 | TFT array substrate and liquid crystal display device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3031664B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100477143B1 (en) * | 1997-11-11 | 2005-08-01 | 삼성전자주식회사 | Pixel repair method of liquid crystal display |
| KR100430773B1 (en) * | 1998-07-14 | 2004-05-10 | 가부시끼가이샤 도시바 | Active matrix type liquid crystal displ ay |
| JP4401488B2 (en) * | 1998-09-01 | 2010-01-20 | キヤノン株式会社 | Photoelectric conversion device |
| JP2002303881A (en) * | 2001-04-04 | 2002-10-18 | Toshiba Corp | Electrode substrate, display panel, and repairing method therefor |
| KR100763171B1 (en) * | 2001-11-07 | 2007-10-08 | 엘지.필립스 엘시디 주식회사 | An active matrix organic light emitting device and a method of fabricating thereof |
| JP4088619B2 (en) | 2004-01-28 | 2008-05-21 | シャープ株式会社 | Active matrix substrate and display device |
| JP4693781B2 (en) | 2004-11-17 | 2011-06-01 | シャープ株式会社 | Active matrix substrate and display device |
| EP1837842B1 (en) | 2004-12-16 | 2014-01-22 | Sharp Kabushiki Kaisha | Active matrix substrate, method for manufacturing active matrix substrate, display, liquid crystal display and television system |
| JP2008152156A (en) | 2006-12-20 | 2008-07-03 | Sony Corp | Display apparatus and method for manufacturing the same |
| KR101522239B1 (en) * | 2007-06-15 | 2015-05-22 | 엘지디스플레이 주식회사 | Liquid crystal display device and repairing method thereof |
| TWI331247B (en) | 2007-12-13 | 2010-10-01 | Au Optronics Corp | Pixel sturctur and repairing method thereof |
-
1996
- 1996-02-19 JP JP3088496A patent/JP3031664B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09222615A (en) | 1997-08-26 |
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