JP2677237B2 - Manufacturing method of liquid crystal display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device using a field effect transistor. 2. Description of the Related Art Recently, a large area display device using a matrix array has been very actively developed, and it is expected to have a wide range of applications such as a small information device and a handy type television. As a flat type large-capacity display device, a device in which switching elements are arranged in a matrix array is considered to be most promising. FIG. 1 is a layout diagram showing an example of the structure of an active matrix array substrate in which non-linear switching elements are arranged in a matrix array. A region surrounded by l in the drawing is a display region, and the non-linear elements 2 are arranged in a matrix therein. Reference numeral 3 is a data signal line (source line) to the non-linear element 2, and 4 is a timing signal line (gate line) to the non-linear element 2. Defects that are likely to occur when a matrix array substrate is constructed as shown in FIG. 1 include pattern defects that occur when patterning each line and a non-linear element, as well as insulation defects and non-insulations at intersections of source lines and gate lines. Insulation failure of the linear element 2 may be mentioned. Among these, the number of defects can be reduced to a very low level by improving the process and eliminating dust, etc., whereas for defective insulation, the quality of the insulating layer is improved and the thickness is increased. Although it is possible to reduce the number of defects at an early stage due to the above-mentioned factors, static insulation or the like often causes defective insulation between lines after completion of the rematrix array. As can be seen from FIG. 1, this defect due to static electricity receives static electricity outside the display area of the panel as the source line or the gate line, resulting in poor insulation at the intersection of the line and the line orthogonal to the result. As a result, the data signal leaks to the gate line, the timing signal leaks to the source line, and the display of all the pixels on the line including the defective insulation point becomes defective, resulting in a so-called line defect, which significantly impairs the display characteristics. . The method of repairing when such insulation failure occurs is not only by cutting the source line or gate line before and after the insulation failure, but such a repair method may cause the source line or gate line to break. All of the pixels connected to the disconnected line remain as non-lighting defects and the line defect cannot be removed. When the matrix array is formed on a single-crystal silicon substrate, it is possible to protect the matrix array from static electricity by forming diodes and resistors for static protection in the silicon substrate. When an array is formed, it is difficult to provide a static electricity protection circuit, so that a large amount of the above-described insulation failure is likely to occur, and mass production of a matrix array is difficult. FIG. 2 shows an example of a matrix array using a MOS field effect transistor as a non-linear element, and shows an equivalent circuit of 1 pixel of a matrix array liquid crystal display device. . Reference numeral 5 denotes a MOS field effect transistor for switching a redata signal. A condenser 6 is used for holding a redeed signal. 7 is a liquid crystal panel, 7-1 is a liquid crystal driving electrode formed corresponding to the liquid crystal driving element, and 7-2
Is an upper glass panel. FIGS. 3 (a) and 3 (b) show specific examples of the matrix array in the example of FIG.
(A) is a plan view, and (b) is a cross-sectional view cut along the dashed-dotted line in (a). This is an example of forming a thin film thin film transistor on a glass substrate 15 to form a lima matrix array. The surface of polycrystalline silicon 8 is thermally oxidized to form a gate insulating film 13 and then a second layer. By forming the polycrystalline silicon and patterning, the gate line and the gate electrode 9 of the transistor and one electrode 12 of the charge storage capacitor are simultaneously formed. Further, the impurities are diffused into the second-layer polycrystalline silicon 9 and 12 and at the same time, the impurities are diffused into a region of the first-layer polycrystalline silicon 8 which is not covered with the gate electrode 9, and the source of the transistor is -Form a drain. Next, after forming an interlayer insulating film 14 on the entire surface, contact holes are formed in the source / drain regions of the transistor. Finally, the source line 10 and the pixel drive electrode 11 are formed to complete the matrix array. In this case, the interlayer insulating film 14 not only insulates the gate line 9 and the source line 10 but also serves as the insulating film of the charge storage capacitor composed of the electrodes 11 and 12, and therefore must be made as thin as possible. The capacity of this capacitor cannot be sufficient. For example, when the size of one pixel is 1 mm square, the size of the capacitor is from the brightness of the screen to about 200 μm 2, and when the insulating film is silicon oxide and the thickness is 5000 angstroms. The capacity of the condenser is only about 2.5 picofarads. On the other hand, the capacitance of the pixel liquid crystal is about 9 picofarads when the liquid crystal thickness is 10 microns. The capacity of the condenser is at least as large as the capacity of the liquid crystal and has no value. Ideally, it is required to be two to three times. Therefore, for this purpose, the thickness of the interlayer insulating film is set to 1/5 to 1/10.
It must be thinned or the area must be 5 to 10 times larger. As mentioned above, the area cannot be larger than the above size due to the brightness of the panel, and the only way to make the interlayer insulating film is thin. In this case, the silicon oxide film has a film thickness of 1,000 angstroms or less. In addition, even if a silicon nitride film having a large relative dielectric constant is used, the dielectric constant is at most twice that of the silicon oxide film, so the film thickness is 1000.
It must be as thin as about 2000 angstroms. On the other hand, considering the gate insulating film l3 of the transistor, this thickness is usually l even if it is thin.
2,000 to 2,000 angstroms, and in some cases, 5000 angstroms or more may be required depending on the withstand voltage of the transistor. When the breakdown voltages of the interlayer insulating film and the gate insulating film of the transistor are compared with each other, the gate insulating film is a thermal oxide film of silicon, so that it is different from that of the interlayer insulating film. Compared with the silicon oxide film formed by the vapor phase epitaxy method, the withstand voltage is about twice as high when the film thickness is the same. Since the breakdown voltage is lower, the breakdown point when static electricity enters the gate line or the source line is always the case where the source line and the gate line cross each other, as shown in FIG. 3, the capacitor capacity decreases. The effect of inserting one capacitor is lost. The present invention provides a gate line, a source line intersecting with the gate line, a thin film transistor connected to the gate line and the source line, and the thin film transistor. A method of manufacturing a liquid crystal display device, comprising: a display region having a charge holding capacitor electrically connected to a substrate, the display region being a first electrode of the gate line and the charge holding capacitor. Forming a wiring layer; forming a first insulating film on the entire surface of the display area where the gate line and the wiring layer serving as the first electrode are formed; and forming a second insulating film on the entire surface of the display area. After forming the first insulating film, at least the step of removing the second insulating film on the wiring layer serving as the first electrode, and the step of interposing the first insulating film and the second insulating film so as to intersect the gate line. And a step of forming the source line, and a step of forming a second electrode of the charge holding capacitor with the first insulating film interposed on the wiring layer serving as the first electrode. And Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 4 shows an embodiment of the present invention, in which (a) is a sectional view at the same position as the sectional view of FIG. 3 (b) and (b) is. FIG. 5 is a plan view showing only the vicinity of the intersection of the source line 10 and the gate line 9. Each member number in FIG. 4 is the same as that in FIG. 3, and the manufacturing method is the same as the example in FIG. 3 up to the formation of the gate line 9 and the capacitor electrode 12 and the diffusion of impurities. The interlayer insulating film is formed by first forming the first layer of silicon oxide film l4-1 on the entire surface of the substrate, and then forming the second layer of silicon oxide film on the entire surface of the substrate by photoetching technique l4 of FIG. The second-layer silicon oxide film other than the intersection region between the gate line 9 and the source line 10 is etched away as shown in FIG. Next, similarly to the example of FIG. 3, a contact hole is opened in the silicon oxide film of the first source / drain region of the transistor and the source line 10 is formed to complete the process. The thickness of the first-layer silicon oxide film l4-1 is 1000 angstroms or less to secure the capacitance of the capacitor, and the thickness of the second-layer silicon oxide film is between the gate line and the source line. Considering the breakdown voltage, 5000 Å or more is preferable. This makes it possible to obtain a sufficient capacity of the re-condenser and make the breakdown voltage at the intersection of the gate line and the source line higher than the gate breakdown voltage of the transistor. In the example shown in FIG. 4, the interlayer insulating films 14-1 formed on the entire surface of the substrate are first formed, and then the interlayer insulating film 14-2 provided only in the intersection region of the source line and the gate line is formed. The order may be reversed, especially when both insulating films are formed of the same material such as a silicon oxide film.
-2 is thicker and therefore easier to etch. Also, FIG.
When the insulating film 14-1 is first formed as described above, if it is formed of a silicon nitride film and the insulating film 14-2 is formed of a silicon oxide film, there is etching selectivity in the patterning as shown in FIG. Better. FIGS. 5A and 5B show another embodiment of the present invention, in which FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along the dashed-dotted line Hani in FIG. The manufacturing process is the same as in the example of FIG. 4, and the thermal oxide film 13 is formed on the surface of the silicon thin film 8.
Is grown, and the second silicon thin films 9 and 12 are grown thereon.
Is formed and patterned. Further, the second silicon thin films 9 and 1
2 and diffusion of the impurity into the region of the silicon thin film 8 which is not covered with the silicon thin film 9. After this, first, the second-layer interlayer insulating film 14-2 is removed by etching, and only the first interlayer insulating film 14-1 is formed on the surface of the silicon thin film 12 used as one electrode of the capacitor. Next, contact holes are opened in the interlayer insulating film on the source / drain regions of the transistors, the source lines 10 and the pixel drive electrodes 11 are formed, and the array is completed. As in the case of the example of FIG. 4, if the film thickness of the interlayer insulating film l4-1 is set to about 1000 angstroms and the film thickness of the interlayer insulating film l4-2 is set to 5000 angstroms or more, the source line and the gate are still formed. The breakdown voltage between the two lines at the intersection of the lines can be made higher than the gate breakdown voltage of the transistor, and the capacitance of the pixel capacitor can be set to a sufficient value. In the case of FIG. 5, since the thick interlayer insulating film also covers the transistor, it is useful for the protection of the device and the reliability is improved. The thick interlayer insulating film l4-2 is the broken line l6 in FIG.
As shown in, it is not necessary to remove it from the capacitor electrode, and the periphery of the capacitor electrode may be covered. However, the larger the area where the interlayer film 14-2 is removed by etching, the larger the capacity of the capacitor can be. Two interlayer insulating films l4-1 and l4-2
The material is generally a silicon oxide film, but may be a silicon nitride film, alumina, or the like. It goes without saying that the two layers may be formed first in the same order as in the example of FIG. . Further, in the embodiment of FIG. 5, the dead space of the pixel driving electrode is reduced, and the contrast is improved. As described above, the gate line 9 can cover the transistor 8 with the pixel drive electrode 11 even when the insulating film is only 14 l. However, due to the existence of the thicker insulating film l4-2, a short film etc. The defects are reduced and effective. As described above, according to the present invention, the gate line, the source line intersecting with the gate line, the thin film transistor connected to the gate line and the source line, and the thin film transistor. A method of manufacturing a liquid crystal display device, comprising: a display region having a charge holding capacitor electrically connected to a substrate, the display region being a first electrode of the gate line and the charge holding capacitor. Forming a wiring layer; forming a first insulating film on the entire surface of the display area where the gate line and the wiring layer serving as the first electrode are formed; and forming a second insulating film on the entire surface of the display area. After the formation of the first insulating film, at least the step of removing the second insulating film on the wiring layer serving as the first electrode, and the step of interposing the first insulating film and the second insulating film so as to intersect the gate line. And the step of forming the source line and the step of forming the second electrode of the charge holding capacitor with the first insulating film interposed on the wiring layer serving as the first electrode. It has the following effect. A) Since the insulating film in the intersection region of the gate line and the source line is formed by stacking two insulating layers, even if one insulating layer has a pinhole, the other insulating layer is insulated. It is extremely unlikely that a pinhole will be formed at the same location in a layer. Therefore, short-circuit defects between lines can be almost completely prevented. B) Since there is a charge holding capacitor,
The retention characteristics of the data signal of the matrix array are improved. Further, a part of the plurality of insulating films formed at the intersection of the gate line and the source line and the dielectric film of the storage capacitor can be formed by the same film, so that the process can be simplified. The application of the present invention is not limited to the matrix array in which the capacitor electrodes are independently provided in the above-described embodiment, but may be a type in which the gate lines of adjacent pixels are shared with the capacitor electrodes of the pixels. It can also be applied to matrix matrices.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a layout diagram showing a configuration example of a matrix array. FIG. 2 is a wiring diagram showing an equivalent circuit of an example of a matrix array display device using liquid crystal for a display body. 3A and 3B are a plan view and a cross-sectional view illustrating a specific example of the example of FIG. 2; FIGS. 4A and 4B are a plan view and a cross-sectional view showing an embodiment of the present invention. FIGS. 5A and 5B are a plan view and a cross-sectional view showing another embodiment of the present invention.

Claims (1)

(57) [Claims] A gate line, a source line intersecting with the gate line, a thin film transistor connected to the gate line and the source line, and a charge retention capacitor electrically connected to the thin film transistor. A method of manufacturing a liquid crystal display device, wherein a display region is formed on a substrate, the method comprising: forming a wiring layer to be the first electrode of the charge holding capacitor; and the gate line and the first wiring layer. A step of forming a first insulating film on the entire surface of the display region in which a wiring layer to be an electrode is formed, and a step of forming a second insulating film on the entire surface of the display region, Removing the upper second insulating film; forming the source line so as to cross the gate line and interposing the first insulating film and the second insulating film; Method of manufacturing a liquid crystal display device characterized by a step of forming a second electrode of said first said charge holding capacitor by interposing an insulating film on the electrode and becomes the wiring layer.