JPH0638426Y2 - 多電源素子用パッケージ - Google Patents

多電源素子用パッケージ

Info

Publication number
JPH0638426Y2
JPH0638426Y2 JP1988116284U JP11628488U JPH0638426Y2 JP H0638426 Y2 JPH0638426 Y2 JP H0638426Y2 JP 1988116284 U JP1988116284 U JP 1988116284U JP 11628488 U JP11628488 U JP 11628488U JP H0638426 Y2 JPH0638426 Y2 JP H0638426Y2
Authority
JP
Japan
Prior art keywords
power supply
package
substrate
loop
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1988116284U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0238736U (en, 2012
Inventor
貴稔 瀧川
寛彦 井原
貴雄 前田
正晴 安原
正策 山中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP1988116284U priority Critical patent/JPH0638426Y2/ja
Publication of JPH0238736U publication Critical patent/JPH0238736U/ja
Application granted granted Critical
Publication of JPH0638426Y2 publication Critical patent/JPH0638426Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1988116284U 1988-09-02 1988-09-02 多電源素子用パッケージ Expired - Lifetime JPH0638426Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988116284U JPH0638426Y2 (ja) 1988-09-02 1988-09-02 多電源素子用パッケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988116284U JPH0638426Y2 (ja) 1988-09-02 1988-09-02 多電源素子用パッケージ

Publications (2)

Publication Number Publication Date
JPH0238736U JPH0238736U (en, 2012) 1990-03-15
JPH0638426Y2 true JPH0638426Y2 (ja) 1994-10-05

Family

ID=31358681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988116284U Expired - Lifetime JPH0638426Y2 (ja) 1988-09-02 1988-09-02 多電源素子用パッケージ

Country Status (1)

Country Link
JP (1) JPH0638426Y2 (en, 2012)

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
浅香寿一著「ボンディング技術」昭和４５年３月３１日日刊工業新聞社発行Ｐ．７１図５・１３（ａ）

Also Published As

Publication number Publication date
JPH0238736U (en, 2012) 1990-03-15

Similar Documents

Publication Publication Date Title
US5800958A (en) Electrically enhanced power quad flat pack arrangement
JPH07231069A (ja) 半導体装置及びその製造方法及びこれに使用されるリードフレーム
JPS60137041A (ja) 樹脂封止形半導体装置
JPH0638426Y2 (ja) 多電源素子用パッケージ
JPS61144855A (ja) 半導体回路のためのパツケージ
JPH0831490B2 (ja) ガラス封止型セラミックパッケージ
JPH0625007Y2 (ja) 多電源素子用パツケージ
JPH069508Y2 (ja) 多電源素子用パツケージ
JPH0622985Y2 (ja) 多電源素子用パッケージ
JPH03280453A (ja) 半導体装置及びその製造方法
US7038305B1 (en) Package for integrated circuit die
JPH0622984Y2 (ja) 多電源素子用パッケージ
JP2612468B2 (ja) 電子部品搭載用基板
JPS6130742B2 (en, 2012)
JP2530193B2 (ja) 高熱伝導半導体実装構造体
JP3521931B2 (ja) 半導体装置及びその製造方法
JPH0878461A (ja) 放熱板付き半導体装置及びその製造方法
JP2551349B2 (ja) 樹脂封止型半導体装置
JPH04144162A (ja) 半導体装置
JPH07221211A (ja) 半導体装置
JPH08316376A (ja) 放熱部材及び該放熱部材を備えた半導体装置
JPS5928364A (ja) リ−ドフレ−ム
JPH04124860A (ja) 半導体パッケージ
JPH04196471A (ja) 半導体装置
JPH06275761A (ja) 半導体装置