JPH0622230B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having multi-layer wiring.

[Conventional technology]

As an interlayer insulating film of a semiconductor device having multi-layer wiring, a silicon oxide film formed by atmospheric pressure CVD (Chemical Vapor Deposition) method or a silicon oxide film containing phosphorus (PSG)
Generally, a film), a silicon oxide film formed by a plasma CVD method, a silicon nitride film, or the like is used.

4 (a) to 4 (c) are cross-sectional views of a semiconductor chip, which are shown in the order of steps for explaining a conventional method for manufacturing a semiconductor device.

As shown in FIG. 4A, a diffusion region 2 of the opposite conductivity type is provided on the surface of the one conductivity type silicon substrate 1, and a silicon oxide film 3 is provided on the surface including the diffusion region 2. Next, a wiring connection window is selectively provided in the silicon oxide film 3 on the diffusion region 2, aluminum is deposited on the surface including the window, and selectively etched to connect with the diffusion region 2 of the window. The lower layer wiring 4 is provided. Next, plasma CVD is performed on the surface including the lower layer wiring 4.
A silicon oxide film 11 is deposited to a thickness of 1 μm by the method.

Next, as shown in FIG. 4B, the opening 8 is formed by selectively etching the silicon oxide film 11 on the lower layer wiring 4.

Next, as shown in FIG. 4 (c), aluminum is deposited on the surface including the opening 8 and selectively etched to form the opening 8
An upper layer wiring 9 connected to the lower layer wiring 4 is formed.

[Problems to be solved by the invention]

The conventional semiconductor device manufacturing method described above uses plasma CVD
There is a problem that the side wall of the opening becomes steep in the step of forming the opening in the silicon oxide film formed by the method, and the upper layer wiring is likely to be broken due to the step at the upper end of the opening.

Further, if the film thickness of the upper layer wiring is increased in order to prevent disconnection, it is difficult to form fine wiring.

[Means for solving problems]

A method of manufacturing a semiconductor device of the present invention comprises a step of providing an insulating film having a wiring connection window of the semiconductor element region on a semiconductor substrate having a semiconductor element region, and depositing a metal layer on the surface including the window. A step of selectively etching and providing a lower layer wiring connected to the element region of the window, and an interlayer in which a silicon oxide film is deposited on the surface including the lower layer wiring while changing the gas pressure of the sputtering method stepwise or continuously. A step of forming an insulating film; a step of selectively etching the interlayer insulating film on the lower layer wiring to provide a mortar-shaped opening; and a step of selectively depositing a metal layer on the surface including the opening. And etching to form an upper layer wiring connected to the lower layer wiring of the opening.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1A, a diffusion region 2 of the opposite conductivity type is provided on the surface of a one conductivity type silicon substrate 1, and a silicon oxide film 3 is provided on the surface including the diffusion region 2. Next, a wiring connection window is selectively provided in the silicon oxide film 3 on the diffusion region 2, aluminum is deposited on the surface including the window, and selectively etched to connect with the diffusion region 2 of the window. The lower layer wiring 4 is provided.

Next, as shown in FIG. 1 (b), a silicon oxide film 5 having a thickness of 0.5 μm in Ar gas at a pressure of 5 × 10 ⁻³ Torr and a pressure of 1 × are formed on the surface including the lower wiring 4 by a sputtering method. 1
A 0.5 μm thick silicon oxide film 6 is sequentially laminated in an Ar gas of 0 ⁻² Torr to form an interlayer insulating film.

Next, as shown in FIG. 1C, a photoresist film 7 having a connection pattern for the lower layer wiring 4 is formed on the surface of the silicon oxide film 6, and the silicon oxide films 6 and 7 are formed using the photoresist film 7 as a mask. A mortar-shaped opening 8 is formed by sequentially etching with buffered hydrofluoric acid, which has a higher etching rate as the Ar gas pressure is higher during the formation of the silicon oxide film.

Next, as shown in FIG. 1D, the photoresist film 7 is removed, and an aluminum layer is deposited on the silicon oxide film 6 including the opening 8 and selectively etched to form the opening 8 An upper layer wiring 9 connected to the lower layer wiring 4 and extending on the silicon oxide film 7 is formed.

2 (a) to 2 (d) are sectional views of a semiconductor chip showing the order of steps for explaining the second embodiment of the present invention.

As shown in FIG. 2A, a diffusion region 2 of the opposite conductivity type is provided on the surface of the one conductivity type silicon substrate 1, and a silicon oxide film 3 is provided on the surface including the diffusion region 2. Next, a wiring connection window of the silicon oxide film 3 is selectively provided on the diffusion region 2, aluminum is deposited on the surface including the window, and selectively etched to connect with the diffusion region 2 of the window to form a lower layer. Wiring 4 is provided. Next, the pressure of Ar gas is changed from 3 × 10 ⁻³ Torr to 1.5 × 1 on the surface including the lower wiring 4 by a sputtering method.
The silicon oxide film 10 is deposited to a thickness of 1 μm to form an interlayer insulating film while continuously changing to 0 ⁻² Torr.

Next, as shown in FIG. 2B, a photoresist film 7 having a connection pattern for the lower wiring 4 is formed on the silicon oxide film 10, and the silicon oxide film 10 is anisotropically formed using the photoresist film 7 as a mask. Etching is performed to form the opening 8.

Next, as shown in FIG. 2 (c), the silicon oxide film 10 is etched with buffered hydrofluoric acid for several minutes using the photoresist film 7 as a mask to form a mortar-shaped opening 8a.

Next, as shown in FIG. 2 (d), the photoresist film 7 is removed, an aluminum layer is deposited on the silicon oxide film 10 including the opening 8a, and the opening 8a is selectively etched.
An upper layer wiring 9 connected to the lower layer wiring 4 and extending on the silicon oxide film 10 is formed.

FIG. 3 is a diagram showing the relationship between the Ar gas pressure when forming a silicon oxide film by the sputtering method and the etching rate of buffered hydrofluoric acid of the silicon oxide film formed by the above sputtering method.

〔The invention's effect〕

As described above, according to the present invention, the interlayer insulating film is formed by depositing a silicon oxide film while changing the pressure of the sputtering Ar gas as the interlayer insulating film stepwise or continuously from the lower side to the higher side. The etching rate is changed above and below the film, and the shape of the opening for connection with the lower layer wiring provided in the interlayer insulating film is made into a mortar shape, which has the effect of preventing disconnection of the upper layer wiring that tends to occur at the upper end of the opening.

[Brief description of drawings]

1 (a) to 1 (d) and 2 (a) to (d) are cross-sectional views of a semiconductor chip in order of steps for explaining the first and second embodiments of the present invention. The figure shows the relationship between the Ar gas pressure when forming a silicon oxide film by the sputtering method and the etching rate of the silicon oxide film formed by the sputtering method with buffered hydrofluoric acid, FIG.
(c) is a sectional view of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor device. 1 ... Silicon substrate, 2 ... Diffusion region, 3 ... Silicon oxide film, 4 ... Lower layer wiring, 5, 6 ... Silicon oxide film,
7 ... Photoresist film, 8, 8a ... Opening, 9 ... Upper layer wiring, 10, 11 ... Silicon oxide film.

Claims (1)

[Claims] 1. A step of providing an insulating film having a wiring connection window of the semiconductor element region on a semiconductor substrate having a semiconductor element region, and a metal layer is deposited on a surface including the window and selectively etched. A step of providing a lower layer wiring connected to the element region of the window, and forming an interlayer insulating film in which a silicon oxide film is deposited while changing the gas pressure of the sputtering method stepwise or continuously on the surface including the lower layer wiring. A step of selectively etching the interlayer insulating film on the lower layer wiring to form a mortar-shaped opening, and depositing a metal layer on the surface including the opening, and selectively etching the metal layer. And a step of forming an upper layer wiring connected to the lower layer wiring of the opening portion.