JPH06209009A - 半導体素子のゲート絶縁膜形成方法 - Google Patents

半導体素子のゲート絶縁膜形成方法

Info

Publication number
JPH06209009A
JPH06209009A JP5284230A JP28423093A JPH06209009A JP H06209009 A JPH06209009 A JP H06209009A JP 5284230 A JP5284230 A JP 5284230A JP 28423093 A JP28423093 A JP 28423093A JP H06209009 A JPH06209009 A JP H06209009A
Authority
JP
Japan
Prior art keywords
oxide film
film
forming
gate insulating
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5284230A
Other languages
English (en)
Japanese (ja)
Inventor
Hyun-Sang Hwang
ヒョン・サン・ヘン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Goldstar Electron Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Goldstar Electron Co Ltd filed Critical Goldstar Electron Co Ltd
Publication of JPH06209009A publication Critical patent/JPH06209009A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP5284230A 1992-10-20 1993-10-20 半導体素子のゲート絶縁膜形成方法 Pending JPH06209009A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019920019239A KR960002066B1 (ko) 1992-10-20 1992-10-20 옥시 나이트라이드 제조방법
KR19239/1992 1992-10-20

Publications (1)

Publication Number Publication Date
JPH06209009A true JPH06209009A (ja) 1994-07-26

Family

ID=19341412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5284230A Pending JPH06209009A (ja) 1992-10-20 1993-10-20 半導体素子のゲート絶縁膜形成方法

Country Status (4)

Country Link
JP (1) JPH06209009A (it)
KR (1) KR960002066B1 (it)
DE (1) DE4335457A1 (it)
TW (1) TW228613B (it)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8053826B2 (en) 2007-09-10 2011-11-08 Renesas Electronics Corporation Non-volatile semiconductor memory device and method of manufacturing the same
US8084315B2 (en) 2008-11-20 2011-12-27 Hitachi Kokusai Electric Inc. Method of fabricating non-volatile semiconductor memory device by using plasma film-forming method and plasma nitridation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8053826B2 (en) 2007-09-10 2011-11-08 Renesas Electronics Corporation Non-volatile semiconductor memory device and method of manufacturing the same
US8084315B2 (en) 2008-11-20 2011-12-27 Hitachi Kokusai Electric Inc. Method of fabricating non-volatile semiconductor memory device by using plasma film-forming method and plasma nitridation

Also Published As

Publication number Publication date
DE4335457A1 (de) 1994-04-21
KR940010209A (ko) 1994-05-24
KR960002066B1 (ko) 1996-02-10
TW228613B (it) 1994-08-21

Similar Documents

Publication Publication Date Title
US5258333A (en) Composite dielectric for a semiconductor device and method of fabrication
JP4001960B2 (ja) 窒化酸化物誘電体層を有する半導体素子の製造方法
US6566281B1 (en) Nitrogen-rich barrier layer and structures formed
EP0617461B1 (en) Oxynitride dielectric process for IC manufacture
JP2871530B2 (ja) 半導体装置の製造方法
US6448127B1 (en) Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets
EP0690487A1 (en) Methods for forming oxide films
JP2001502115A (ja) 信頼できる極薄酸窒化物形成のための新規なプロセス
KR100455737B1 (ko) 반도체소자의게이트산화막형성방법
JP3558565B2 (ja) 不揮発性半導体装置の製造方法
JP3593340B2 (ja) 集積回路デバイスの製造方法
JPH06209009A (ja) 半導体素子のゲート絶縁膜形成方法
JPH03257828A (ja) 半導体装置の製造方法
KR0147432B1 (ko) 반도체 소자의 게이트 절연막 형성방법
JP3041065B2 (ja) 絶縁膜形成方法
US6407008B1 (en) Method of forming an oxide layer
JP3041066B2 (ja) 絶縁膜形成方法
KR0119965B1 (ko) 반도체 소자의 산화막 형성방법
KR0162900B1 (ko) 산화물 형성 방법
KR100247904B1 (ko) 반도체 장치의 제조방법
US20010034090A1 (en) Methods for forming a gate dielectric film of a semiconductor device
JP2739593B2 (ja) 半導体装置の製造法
KR970000704B1 (ko) 반도체 소자 캐패시터 유전층 제조방법
US6794312B2 (en) Layering nitrided oxide on a silicon substrate
KR0132381B1 (ko) 화학기상증착법에 의한 산화막 형성방법

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20060124

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20060201

A072 Dismissal of procedure [no reply to invitation to correct request for examination]

Free format text: JAPANESE INTERMEDIATE CODE: A072

Effective date: 20060725