JPH06202589A - Liquid crystal driving circuit - Google Patents

Abstract

PURPOSE:To provide a liquid crystal driving circuit capable of reducing a trailing thread phenomenon due to a glitch and obtaining an excellent image display. CONSTITUTION:This circuit is provided with a scanning electrode driving circuit 16 outputting a scanning electrode driving signal for a liquid crystal display pannel 15 and a signal electrode driving circuit 14 outputting a halftone signal electrode impression waveform with only a rise as a signal electrode driving signal. A liquid crystal applied voltage generation circuit 17 is provided which applies the voltages V2, V4 setting a scan driving signal for the scanning electrode driving circuit 16, and applies the voltages V1, V3 setting the amplitude of the signal electrode driving signal for the signal electrode driving circuit 14, and a capacitor 18 is connected between the terminals of the output voltages V1 and V2 of the liquid crystal applied voltage generation circuit 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention When the period required for expressing a plurality of gray scales from the minimum gray scale to the maximum gray scale is one gray scale period, the on-voltage during the one gray scale period is The present invention relates to a liquid crystal drive circuit that expresses a plurality of gradations according to the ratio of off-voltage.

[0002]

2. Description of the Related Art Conventionally, since a halftone is displayed on a liquid crystal display panel used in a liquid crystal television or a personal computer, a period required to express a plurality of grayscales from a minimum grayscale to a maximum grayscale is 1 When the gradation period is set,
A liquid crystal driving method is used in which a plurality of gray levels are expressed by the ratio of the on voltage and the off voltage during the gray level period. In this case, 1
The grayscale period is generally one scanning period, but there are some that determine the grayscale by taking a plurality of scanning periods as in the frame thinning method of a personal computer.

FIG. 5 shows an example in which a certain halftone is displayed on the entire screen. Scan electrode drive signals X1 and X are shown.
2, a signal electrode drive signal Yn for alternately inverting the ratio of the on-voltage and the off-voltage to X3 is applied. However, according to such a liquid crystal driving method, display unevenness due to so-called whiskers may appear in the output waveform of the signal electrode driving circuit. FIG. 6 shows an example in which a pure white circle is displayed on a dark background when driven by an 8-chip signal electrode drive circuit. In this case, the brightness of the background black becomes different depending on the area covered by each signal electrode drive circuit, and the brightness changes in the order of area 6 → area 2, 7 → area 3 → areas 1, 4, 5, 8. The correct values are the brightness of areas 1, 4, 5, and 8 without circles.

Therefore, in order to drive the liquid crystal display panel, the scan electrode drive circuit generates the scan electrode drive signal, and the signal electrode drive circuit generates the signal electrode drive signal.
FIG. 7 shows an output buffer for selecting V1 and V3 as the signal electrode drive signal Yn in the conventional signal electrode drive circuit. In this case, the liquid crystal display panel
Since it is driven by AC, V1 is off voltage and V3 for a certain period.
Is the on-voltage, and V1 is the on-voltage and V3 in the other period.
Is the off voltage.

However, in such a case, for example,
When the signal electrode drive signals Y1 and Y2 are as shown in FIG.
Y1 is affected at the rising edge of, and whiskers (a) are generated, and whiskers (a) are generated at Y2 at the falling edge of Y1. Similarly, the signal electrode drive signals Y1 and Y2 are shown in FIG.
In such a case, the whiskers (c) are generated on Y1 at the falling edge of Y2, and the whiskers (d) are generated on Y2 at the rising edge of Y1. The size of each whisker is more affected by rising than falling, and the voltage at that time is larger at the V1 level than at the V3 level.

The cause will be examined below. Figure 7 above
In the output buffer of, N type FETs 1 and 2 and P type FE
It is composed of T3 and inverters 4 and 5. Here, the N-type FET and the P-type FET have symmetrical characteristics as shown in FIG. Now, for the sake of explanation, consider only the left part of the dotted line in FIG. That is, each FET
If the output sides of 1, 2, and 3 are considered to be open, the point a in the figure changes from L level to H when the signal electrode pole drive waveform rises.
At the level, the N-type FET1 changes from the open state to V1
Become a level. On the other hand, when the point b in the figure changes from the H level to the L level, the P-type FET 3 changes from the open state to the V1 level, and the N-type FET 2 changes from the V3 level to the open state.

In this case, since the inverter 5 is connected between points a and b in the figure, the timing of the level change at each point a and b is delayed, which causes the P-type FE.
The timings of changes in the outputs of the T3 and the N-type FET 2 are largely deviated. FIG. 11 shows this state, and as is clear from the figure, there is a period in which V1 and V3 are simultaneously turned on at the rising edge of the signal electrode drive waveform in the figure A part, and this is the through state. It causes the so-called "beard" called glitch. However, at the trailing edge of the signal electrode drive waveform in the portion c in the figure, there is no period in which V1 and V3 are simultaneously turned on,
No "beard" is generated. Further, in the above description, the relationship between the N-type FET 1, the P-type FET 3, and the N-type FET 2 is described. However, the P-type FET 3 and the N-type FET 2 also have some through states at the portions (a) and (d) in the figure, but the N-type F
Compared to the relationship between ET1 and P-type FET 3 and N-type FET 2, it is negligible.

As described above, in the conventional signal electrode driving circuit, a large whisker may be generated in the rising operation of the signal electrode driving waveform due to a problem in the circuit configuration.
This may cause uneven brightness on the screen of the liquid crystal display panel, resulting in deterioration of image quality.

[0009]

As described above, in the conventional signal electrode drive circuit, a large whisker is generated in the rising operation of the signal electrode drive waveform, and the whisker may cause uneven brightness on the liquid crystal display panel. However, there is a drawback that the image quality on the liquid crystal display panel is significantly deteriorated. The present invention is
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal drive circuit that can reduce the occurrence of so-called whiskers and can obtain a high-quality screen display.

[0010]

A liquid crystal drive circuit according to the present invention comprises a first voltage generator for generating a selection voltage as a scan electrode drive signal and a second voltage generator for generating a non-selection voltage as a scan electrode drive signal. The generator includes a generator, a third voltage generator that generates a high-level voltage as a signal electrode drive signal, and a fourth voltage generator that generates a low-level voltage as a signal electrode drive signal. When the period required to express a plurality of gradations up to the gradation is one gradation period,
At the timing in the middle of the gradation period excluding the switching timing of the period, only one of the change of the signal electrode drive signal from the low level voltage to the high level voltage or the change from the high level voltage to the low level voltage is performed. It is configured such that it exists and has a capacitor connected between the second voltage generating section and one of the third voltage generating section and the fourth voltage generating section.

[0011]

As a result, according to the present invention, when the halftone signal electrode applied waveform of only rising is output as the signal electrode drive signal, the glitch generated in the scan electrode applied waveform and the signal electrode drive signal are generated. If the glitches generated in the high-level voltage waveform are in opposite directions and are actuated by the capacitors so that they do not cause glitches, and if the signal electrode drive signal is a falling edge only halftone signal electrode applied waveform, The glitch generated in the scan electrode applied waveform and the glitch generated in the waveform of the low level voltage as the signal electrode drive signal have opposite directions, and the capacitors act to prevent glitches from each other, and the glitch is suppressed and reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of the same embodiment. In the figure, the composite video signal is represented by a sync separation circuit 12.
After the vertical and horizontal synchronizing signals .phi.v, .phi.H and the video signal V are separated by the video signal V, the video signal V is converted by the A / D converter 13 into image data D1 to D4 which are digitized into predetermined bits, for example, 4 bits. . The digitized image data D1 to D4 are input to the signal electrode drive circuit 14.
The signal electrode drive circuit 14 includes a liquid crystal applied voltage generation circuit 17
The voltages V1 and V3 are supplied to the image data D1
The voltages V1 and V3 are selected in accordance with .about.D4 to generate a signal electrode drive signal Yn, which is applied to the signal electrode of the liquid crystal panel 15.

A scan electrode drive circuit 16 is supplied with voltages V0, V2, and V4 from the liquid crystal applied voltage generation circuit 17, and these voltages are appropriately selected to select the scan electrode drive signal Xn.
To drive the scan electrodes of the liquid crystal panel 15. 11
Is a controller for controlling the overall timing, and is supplied with vertical and horizontal synchronizing signals φv and φH from the sync separation circuit 11, and the sampling clock φs is supplied to the A / D converter 13 in synchronization with these synchronizing signals φv and φH.
To the signal electrode drive circuit 14 with the timing signal CKFS,
P / N, φc and the timing signal CKFC are supplied to the scan electrode drive circuit 16, respectively. The timing signal CKFS is a signal for AC driving the liquid crystal display panel and is inverted every scanning period. Timing signal P /
N is a signal in which the phase of the timing signal CKFC is inverted. The timing signal CKFS is a signal which is always "H". The timing signal .phi.c is a signal for forming a PMW waveform and is generated 15 times during one scanning period. The controller 11 generates various other timing signals (not shown) to control each circuit.

FIG. 2 shows a schematic configuration of the liquid crystal applied voltage generating circuit 17, which has a reference voltage generating unit 171, operational amplifier circuits 172 to 174, and the above-mentioned output voltages V0 to V0.
V4 is generated. Here, the voltage V1 is
The high level voltage V3 for driving the signal electrodes is a low level voltage V3 for driving the signal electrodes. Further, the voltage V4 is the selection voltage for driving the scan electrodes, and the voltage V2.
Is a non-selection voltage for driving the scan electrodes.

A capacitor 18 is connected between the output voltage V1 and V2 terminals of the liquid crystal applied voltage generating circuit 17. Next, the operation of the embodiment configured as described above will be described. The video signal V taken out through the sync separation circuit 12 is sampled by the A / D converter 13 at the sampling clock φs to obtain the 4-bit image data D.
The signal is converted into 1 to D4 and further converted into a signal electrode drive signal Yn by the signal electrode drive circuit 14 and supplied to the liquid crystal display panel 15.

On the other hand, the scan electrode drive circuit 16 generates a scan electrode drive signal Xn and supplies it to the liquid crystal display panel 15 to scan the scan electrodes. The non-selection voltage of the scan electrode drive signal Xn is V2, and the selection voltage is switched between V0 and V4 in synchronization with the timing signal CKFC which is inverted every scanning period. Now, with respect to the timing signal CKFC shown in FIG.
It is assumed that the signal electrode drive signal Yn from the signal No. 4 is a halftone signal electrode application waveform Y having only a rising edge, as shown in FIG. Then, at the time of switching of the signal electrode applied waveform Y, glitches (a) to (v) are generated in the scan electrode applied waveform X (V2) as shown in FIG. 7C, of which the signal electrode applied waveform Y rises. The upward glitches (a), (d), (f), and (k) that occur at the time of producing a difference in effective voltage, which causes stringing.

In this case, in the signal electrode drive circuit 14, when the signal electrode applied waveform Y is switched, as an operation peculiar to the CMOS which constitutes the signal electrode drive circuit 14 as described above, between the power source voltages V1 and V3. Since a through current flows in the voltage V1, the waveforms of the voltages V1 and V3 have glitches (pulled inward) at the time of switching the signal electrode applied waveform Y, as shown in FIGS. 1) to (9) have occurred.

In this case, since the capacitor 18 is connected between the terminals of the output voltages V1 and V2 of the liquid crystal applied voltage generation circuit 17, the scanning electrode applied waveform X (V2) shown in FIG. Of the glitches (1) to (9) generated in the waveform of the voltage V1 shown in FIG. 3D and the glitches (2) and (9). 4), (6), and (8), which are generated in the direction opposite to each other, act so as not to generate glitches with each other, and as a result, the scan electrode applied waveform X (V2) shown in FIG. Glitches that occur in
(D), (f), and (h) are suppressed and become smaller, and the phenomenon of stringing can be reduced.

In the above description, the case where the signal electrode drive signal Yn of the signal electrode drive circuit 14 outputs the signal electrode application waveform Y in the halftone of only the rising edge has been described. For example, it is shown in FIG. It can also be applied to the case where the signal electrode drive signal Yn of the signal electrode drive circuit 14 with respect to the timing signal CKFC is a halftone signal electrode applied waveform Y of only a falling edge as shown in FIG.

In this case, at the time of switching the signal electrode applied waveform Y, the scan electrode applied waveform X (V
2) glitches (a) to (k) occur, and among these, the downward glitches (a), (d), (f), and (k) that occur when the signal electrode applied waveform Y falls are stringed. Cause of. Therefore, here, a capacitor 18 is connected between the terminals of the output voltages V2 and V3 of the liquid crystal applied voltage generating circuit 17. Then, the capacitor 18 causes glitches (a), (d), (f), and (k) generated in the scan electrode applied waveform X (V2) shown in FIG. 4 (c) and the voltage V3 shown in FIG. 4 (d). Among the glitches (1) to (9) generated in the waveform of the above, the respective clits generated in the opposite relationship of the glitches (2), (4), (6), and (8) do not generate glitches with each other. And as a result, a glitch (a) generated in the scan electrode applied waveform X (V2) shown in FIG. 4 (c),
(D), (f), and (h) are reduced, and the phenomenon of stringing can be reduced.

As a result, the stringing phenomenon can be suppressed, the occurrence of uneven brightness on the screen of the liquid crystal display panel due to the stringing phenomenon can be prevented, and a good quality screen display can be obtained on the liquid crystal display panel. Will be done. In addition, the present invention is not limited to the above-mentioned embodiments, and can be carried out by appropriately modifying it without departing from the scope of the invention.

[0022]

According to the present invention, when a halftone signal electrode applied waveform of only rising is output as the signal electrode drive signal, a glitch generated in the scan electrode applied waveform,
The glitch that occurs in the high-level voltage waveform as the signal electrode drive signal is in the opposite direction, and the capacitors act so that they do not cause glitches. When is output, the glitch generated in the scan electrode applied waveform and the glitch generated in the waveform of the low level voltage as the signal electrode drive signal are in opposite directions, and the capacitors act so as not to cause glitches, Glitch is suppressed and reduced, the phenomenon of stringing is reduced, and good image display can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a liquid crystal applied voltage generation circuit used in an embodiment.

FIG. 3 is a diagram for explaining the operation of the embodiment.

FIG. 4 is a diagram for explaining the operation of another embodiment of the present invention.

FIG. 5 is a diagram for explaining the operation of a conventional signal electrode drive circuit.

FIG. 6 is a diagram showing a display example on a liquid crystal display panel when a conventional signal electrode drive circuit is used.

FIG. 7 is a diagram showing a schematic configuration of an input buffer used in a conventional signal electrode drive circuit.

FIG. 8 is a diagram for explaining a signal electrode drive waveform by a conventional signal electrode drive circuit.

FIG. 9 is a diagram for explaining a signal electrode drive waveform by a conventional signal electrode drive circuit.

FIG. 10 is a diagram for explaining the input buffer of FIG.

11 is a time chart for explaining the input buffer of FIG.

[Explanation of symbols]

11 ... Controller, 12 ... Sync separation circuit, 13 ... A /
D converter, 14 ... Signal electrode drive circuit, 141-144 ...
EX OR circuit, 145 ... PWM circuit, 146 ... EOR,
147 ... Output buffer, 15 ... Liquid crystal display panel, 16 ...
Scan electrode driving circuit, 17 ... Liquid crystal applied voltage generating circuit, 18
… Capacitor.

Claims (1)

[Claims] 1. A first voltage generator that generates a selection voltage as a scan electrode drive signal, a second voltage generator that generates a non-selection voltage as a scan electrode drive signal, and a high-level voltage as a signal electrode drive signal. In order to express a plurality of gray levels from the minimum gray level to the maximum gray level, a third voltage generating section that generates a voltage and a fourth voltage generating section that generates a low level voltage as a signal electrode drive signal are provided. When the required period is one gradation period, the signal electrode drive signal changes from the low level voltage to the high level voltage at a timing in the middle of the one gradation period excluding the switching timing of the period. Only one of the changes from the high level voltage to the low level voltage is present, and the connection is provided between the second voltage generating section and one of the third voltage generating section and the fourth voltage generating section. Conde Liquid crystal drive circuit, characterized in that it comprises a support.