JP2504331B2 - Liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal television or the like.
The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art A conventional liquid crystal television is generally constructed as shown in FIG. In the figure, reference numeral 1 denotes a television antenna, and television broadcast radio waves received by the television antenna 1 are input to a tuner 2. This tuner 2
Selects a radio wave of a designated channel from the television reception radio waves, converts it into an intermediate frequency signal, and outputs it to the television linear circuit 3. The television linear circuit 3 amplifies the intermediate frequency signal from the tuner 2 and then detects video to extract a video signal, and also performs sync separation to extract a vertical sync signal and a horizontal sync signal to convert the video signal into an A / D signal. To conversion circuit 4,
The sync signal is output to the sync control circuit 5, respectively.

The sync control circuit 5 creates various timing signals from the vertical sync signal and the horizontal sync signal, and
It outputs to the / D conversion circuit 4, the segment electrode drive circuit 6, and the common electrode drive circuit 7. Further, the segment electrode drive circuit 6 and the common electrode drive circuit 7 are supplied with liquid crystal drive voltages of multi-valued levels from the liquid crystal drive voltage generation circuit 8.
Then, the A / D conversion circuit 4 converts the video signal into, for example, 3-bit digital data in synchronization with the sampling clock .phi.S1 from the synchronization control circuit 5, and outputs it to the segment electrode drive circuit 6. The segment electrode drive circuit 6 creates a gradation signal according to the data from the A / D conversion circuit 4 and drives the segment electrodes of the LCD panel 9 for display, as will be described later in detail. Further, the common electrode drive circuit 7 generates a common electrode drive signal according to the timing signal from the synchronization control circuit 5, and selectively drives the common electrodes of the LCD panel 9 sequentially.

Therefore, the segment electrode drive circuit 6
Is configured as shown in FIG. In the figure, 11
Is a 3-bit n-stage shift register, which is the 3-bit digital data D1 sent from the A / D conversion circuit 4 of FIG.
.About.D3 are read in synchronism with the shift clock .phi.S2 and are shifted as indicated by arrow a. The shift clock φS2
Have the same frequency as the sampling clock .phi.S1 and differ only in phase by 180 DEG. When one line of data D1 to D3 is read into the shift register 11,
The data is latched in the buffer 12 by the latch pulse φN shown in the timing chart of FIG. 6 given from the synchronization control circuit 5 and further sent to the gradation signal generating circuit 13. The latch pulse φN is output in synchronization with the horizontal synchronizing signal. Further, the gradation signal creating circuit 13 has
From the brightness modulation pulse generation circuit 14, the brightness modulation pulse P1,
P2 and P3 are given. The luminance modulation pulse generating circuit 14 divides the basic clock φ2 to generate the luminance modulation pulses P1 to P3 shown in FIG.
It is reset each time N is given. The gradation signal generation circuit 13 is provided with the data held in the buffer 12 and the brightness modulation pulse P1 from the brightness modulation pulse generation circuit 14.
.About.P3, eight-level gradation signals S1 to Sn are created and output to the drive circuit section 15. FIG. The gradation signal Si in FIG.
Indicates that the i-th digit data has a gradation of "5" in the X-th frame,
An example of gradation "3" is shown in the (X + 1) th frame. The drive circuit section 15 selects the liquid crystal bias voltages V _SH and V _SL according to the frame switching signal φf and the gradation signals S1 to Sn, and the segment drive signals Y1 to Yn.
To drive the segment electrodes of the LCD panel 9.

The segment electrodes are driven as described above, and an image is displayed on the LCD panel 9. However, in the above-mentioned conventional circuit, the digital data D1 to D3 A / D converted by the A / D conversion circuit 4 are directly transferred to the shift register 1
1 and read through the buffer 12 to create a gradation signal generation circuit 1
3 is output, and no particular correction processing is performed.

[0006]

However, a liquid using a liquid crystal display panel having a relatively large number of scanning lines, such as a liquid crystal television, is used .
In the crystal display device, there is a problem in that the image quality is not sufficient because the contrast is lowered due to the reduction of the operation margin and the influence of the response speed.

The present invention has been made in view of the above circumstances, and it is possible to improve the contrast and obtain a high-quality image even in a liquid crystal display device using a liquid crystal display panel having a relatively large number of scanning lines such as a liquid crystal television. With the goal.

[0008]

In order to achieve the above object, the present invention provides a common electrode driving circuit and a segment electrode driving circuit.
Drive circuit, common electrode drive circuit to common electrode drive
Outputs voltage and segments from the segment electrode drive circuit
In a liquid crystal display device that outputs an electrode drive voltage,
Image data is sequentially input to the segment electrode drive circuit.
And a shift register that holds one line
Image data for one line was stored in the soft register
After that, the image data for the one line is collectively transferred.
Floor and the image data stored in the above buffer.
Tone signal creating circuit for creating the tone signal and the above tone signal creating circuit.
The segment electrode drive voltage is generated from the gradation signal created by the synthesis circuit.
And a liquid crystal drive unit that creates pressure.
Image data from the data supply means and from the shift register
The output image data delayed by one line is input.
Contour determined by these two input image data
Image data that has been corrected to emphasize
Image output from the bull memory and the table memory
Means for supplying data to the shift register .

[0009]

[0010]

With the above-described structure, the image data supplied from the image data supplying means is not displayed as it is, but the gradation change is emphasized in comparison with the delayed image data. Since the display is corrected based on and the image is displayed based on the corrected image data, the contrast can be improved.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described below with reference to the drawings when the present invention is applied to a liquid crystal television. First, an embodiment for performing vertical contour correction will be described with reference to FIG. FIG. 1 shows the details of the segment electrode drive circuit portion. The same parts as those of the circuit of FIG. 5 are designated by the same reference numerals and detailed description thereof will be omitted.

In FIG. 1, reference numeral 21 is a ROM for data correction.
Then, the 3-bit digital data D1 to D3 output from the A / D conversion circuit 4 are given as a row address, and the final shift output of the shift register 11 is given as a digit address. Then, the data read from the ROM 21 is input to the shift register 11.

The ROM 21 for data correction described above is provided in FIG.
As shown in, each address has 3-bit data "0" ~
"7" is written. That is, the ROM 21 basically outputs data corresponding to the data from the A / D conversion circuit 4, but the data from the A / D conversion circuit 4 and the data from the shift register 11 are separated by two or more gradations. When the data from the A / D conversion circuit 4 is shifted by one gradation, that is, when the data from the A / D conversion circuit 4 is larger by two gradations or more, the data from the A / D conversion circuit 4 is output by one gradation. Is 2
When the gradation is smaller than the gradation, data which is smaller by one gradation is output. However, when the output data of the A / D conversion circuit 4 is "0" and "1", the data is output as it is.

Therefore, the shift register 11 is a ROM
The data read from 21 is read in synchronization with the shift clock .phi.S2 and is sequentially shifted. The data read into the shift register 11 is stored in the buffer 12
And the final shift output is sent to R as described above.
It is sent as a digit address to OM21. Buffer 1 above
The second and subsequent circuits have the same configuration as the circuit shown in FIG. Next, the operation of the above embodiment will be described.

Image data for one line of the screen is stored in the shift register 11 and transferred to the buffer 12 in synchronization with the latch pulse φN. At this time, the data for one line is left as it is in the shift register 11, and when the image data of the next line is read by the shift clock φS2, it is sequentially output from the last digit, and the ROM 21
Sent as a digit address.

Now, assuming that the data of the n-th line is stored in the shift register 11, next, the A / D conversion circuit 4
The data of the "n + 1" th line is sequentially read in synchronization with the sampling clock .phi.S1 and is given to the ROM 21 as a row address. Therefore, the A / D conversion circuit 4
When the image data of the current line (n + 1 line) is output from the shift register 1, the image data of the previous line (n line) at the same sampling position as this image data is output.
The data is read from 1 and input to the ROM 21.

As a result, in the ROM 21, the data of the current line and the data of the same sampling position of the previous line are compared, and if the difference is within "1", the data D1 to D3 from the A / D conversion circuit 4 remain unchanged. Shift register 11
Is input to However, if the gradation difference between the data of the current line and the data of the previous line is 2 gradations or more, as shown in FIG. 2, the data D1 to D3 from the A / D conversion circuit 4 are changed according to the direction of the difference. It is corrected by one gradation and sent to the shift register 11. For example, the output data D1 ...
When D3 is "3", if the data of the current line is "5", the data of "2" is read, and if the data of the previous line is "1", the data of "4" is read from the ROM 21.

As described above, the output data D1 to D3 of the A / D conversion circuit 4 are corrected by the ROM 21 and sequentially written in the shift register 11. When one line of data is written in the shift register 11, it is transferred to the grayscale signal creation circuit 13 via the buffer 12 by the latch pulse φN, and a grayscale signal is created based on the corrected data. To be done. Thereafter, the same operation is repeated, and vertical line contour correction is performed by comparing data between the lines.

[0019]

Second Embodiment of the Invention Next, a second embodiment of the present invention will be described with reference to FIG. This second embodiment shows a case where horizontal contour correction is performed. As shown in FIG. 3, a one-digit (3-bit) buffer 22 is provided on the output side of the ROM 21, and the data held in this buffer 22 is stored. ROM
21 is given as a digit address. The buffer 22
Is designed to read the output of the ROM 21 in synchronization with the shift clock φS2 and output it in synchronization with the sampling clock φS1. That is, this second embodiment is
Instead of the output of the shift register 11, the data held in the buffer 22 is given to the ROM 21 as a digit address.

In this embodiment, each data output from the ROM 21 is held in the buffer 22 and then compared with the data D1 to D3 output from the A / D conversion circuit 4.
Based on the result, the output data D1 to D3 of the A / D conversion circuit 4 are stored in the ROM 2 in the same manner as in the first embodiment.
It is corrected by 1 and sent to the shift register 11. That is, each data on one line is corrected by comparison with the adjacent data, whereby the horizontal contour correction is performed.

The contents of the correction data stored in the ROM 21 are not limited to those in the above-mentioned embodiment, and it goes without saying that the correction data may be set to other values for data correction.

[0022]

As described in detail above, according to the present invention,
Instead of displaying the image data as it is supplied from the image data supply means, the image data is corrected in such a direction as to emphasize the change in gradation as compared with the delayed image data, and the corrected image data is used as a basis. Since the display is performed on the screen, the contrast can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a diagram showing an example of ROM data setting in FIG. 1;

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing a schematic configuration of a conventional liquid crystal television.

5 is a block diagram showing details of a segment electrode driving circuit in FIG.

6 is a timing chart for explaining the operation of FIG.

[Explanation of symbols]

4 ... A / D conversion circuit, 6 ... Segment electrode drive circuit, 9
... LCD panel, 11 ... Shift register, 12 ... Buffer, 13 ... Gradation signal generating circuit, 14 ... Luminance modulation pulse generating circuit, 15 ... Driving circuit section, 21 ... ROM, 22 ... Buffer.

Claims (1)

(57) [Claims] 1. A common electrode drive circuit and a segment electrode drive
Circuit, and the common electrode drive circuit
Pressure, and the segment electrode drive circuit
In a liquid crystal display device that outputs a polar driving voltage, the segment electrode driving circuit holds image data sequentially shifted and input for one line.
Image data for one line is stored in the shift register and the above shift register.
Then, the image data for the one line is transferred in a batch.
Buffer and a gradation signal from the image data stored in the buffer.
A gradation signal generation circuit for forming, segment from the tone signal generated by the tone signal generator circuit
A liquid crystal drive unit for generating a drive voltage for the input electrodes , and further, the image data from the image data supply unit and the shift register.
Image data delayed by one line output from the
Input and determined by these two input image data
Image data corrected to emphasize the contour
Table memory and the image data output from the table memory
A liquid crystal display device comprising: a means for supplying the liquid crystal to a shift register .