JPH06202593A - Liquid crystal driving method - Google Patents

Abstract

PURPOSE:To reduce a trailing thread phenomenon due to a glitch and to obtain an excellent image display by equalizing the switching period of a signal electrode driving signal from an on voltage to an off voltage and the switching period from the off voltage to the on voltage with the inversion period of a scanning electrode driving signal. CONSTITUTION:By a scanning electrode driving circuit 16, the scanning electrode driving signal Xn is generated, and is supplied to a liquid crystal display pannel 15 to scan a scanning electrode. The scanning electrode driving signal Xn whose nonselective voltage is V2, and whose selective voltage switches between the voltages V0 and V4 synchronizing with timing signal CKFC inverting at every one scanning period. Then, respective image data are inputted to a PWM circuit through an EX OR circuit inputted with the timing signal P/N. In such a case, the timing signal P/N is the signal whose phase is inverted with the timing signal CKFC inverting at every two scanning periods, and respective image data are inverted between '1', '0' synchronizing with the timing signal P/N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention When the period required for expressing a plurality of gray scales from the minimum gray scale to the maximum gray scale is one gray scale period, the on-voltage during the one gray scale period is The present invention relates to a liquid crystal driving method that expresses a plurality of gray levels by the ratio of off-voltage.

[0002]

2. Description of the Related Art Conventionally, since a halftone is displayed on a liquid crystal display panel used in a liquid crystal television or a personal computer, a period required to express a plurality of grayscales from a minimum grayscale to a maximum grayscale is 1 When the gradation period is set,
A liquid crystal driving method is used in which a plurality of gray levels are expressed by the ratio of the on voltage and the off voltage during the gray level period. In this case, 1
The grayscale period is generally one scanning period, but there are some that determine the grayscale by taking a plurality of scanning periods, such as the frame thinning method of a personal computer.

[0003]

However, in such a liquid crystal driving method, the rising and falling edges of the waveform of the signal electrode drive signal are changed to the waveform of the scan electrode drive signal and the waveform of other signal electrode drive signals. Affects and produces a beard called a glitch. For example, the signal electrode drive signal Y
When 1 and Y2 are as shown in Fig. 5, Y1 is generated at the rising edge of Y2.
And the whiskers (A) are generated, and the whiskers (A) are generated on Y2 at the falling edge of Y1. Similarly, when the signal electrode drive signals Y1 and Y2 are as shown in FIG. 6, a whisker (c) is generated on Y1 at the falling edge of Y2 and a whisker (d) is generated on Y2 at the rising edge of Y1. The rise of the whiskers is more affected than the fall of each whisker, and the voltage at that time is larger at the V1 level than at the V3 level.

Due to the glitch, there is a problem that so-called stringing crosstalk occurs, resulting in deterioration of image quality. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal driving method that can reduce the stringing phenomenon caused by glitches and can obtain a high-quality image display.

[0005]

The present invention is a liquid crystal driving method for driving a liquid crystal panel by a scan electrode driving signal and a signal electrode driving signal, and expresses a plurality of gradations from a minimum gradation to a maximum gradation. When the period required for this is one gradation period, a plurality of gradations are expressed by the ratio of the ON voltage and the OFF voltage in the one gradation period, and the scan electrode drive signal is inverted at a predetermined cycle. In a liquid crystal driving method that performs AC driving, the scan electrode driving signal is inverted in two scanning periods, and the signal electrode driving signal is switched between an on-voltage and an off-voltage and an off-voltage to an on-voltage. By making it the same as the inversion period of the scan electrode drive signal, the change from the on voltage to the off voltage and the change from the off voltage to the off voltage are performed at the timing in the middle of the two scanning periods excluding the switching timing of the period. Change to voltage is set to be less than 1 times.

[0006]

As a result, according to the present invention, the glitch of the scanning drive signal generated by switching the output waveform corresponding to the image signal of the signal electrode drive signal can be suppressed, the fluctuation of the effective voltage can be reduced, and so-called stringing can be performed. You can improve.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display device adopting the driving method of the present invention. In the figure, a composite video signal is separated into vertical and horizontal synchronizing signals φv and φH and a video signal V by a sync separation circuit 12, and then the video signal V is digitally converted into a predetermined bit, for example, 4 bits, by an A / D converter 13. The converted image data D1 to D4 are converted. The digitized image data D1 to D4 are input to the signal electrode drive circuit 14. Signal electrode drive circuit 14
Are supplied with voltages V1 and V3, and the image data D
The voltages V1 and V3 are selected according to 1 to D4 to generate the signal electrode drive signal Yn, which is applied to the signal electrode of the liquid crystal display panel 15.

Reference numeral 16 is a scan electrode drive circuit, which has voltages V0 and V0.
2, V4 are supplied, and these voltages are appropriately selected to generate the scan electrode drive signal Xn to generate the liquid crystal display panel 15
Drive the scan electrodes. Reference numeral 11 denotes a controller for controlling the overall timing, and the sync separation circuit 1
The vertical and horizontal synchronizing signals φv and φH are supplied from 1
The A / D converter 13 is synchronized with the synchronizing signals φv and φH.
To the signal electrode drive circuit 14
To the timing signals CKFS, P / N, CKN, φc,
Then, the timing signal CKF is sent to the scan electrode drive circuit 16.
Supply C respectively. The timing signal CKFC is a signal for AC driving the liquid crystal display panel, and is inverted every two scanning periods. The timing signal P / N is a signal in which the phase of the timing signal CKFC is inverted. The timing signal CKN is a signal that determines one gradation period. The timing signal φc is a signal for forming a PMW waveform, and is PWM-modulated depending on the pulse width from the generation of the timing signal CKN to the counting of the timing signal φc. Further, the timing signal CKFS is a signal which is inverted in one scanning period cycle.

The controller 11 generates other timing signals (not shown) to control each circuit. FIG. 2 is a circuit diagram showing a main part of the signal electrode drive circuit 14. 4 digitized by A / D converter 13
The bit image data is input to one input terminal of an exclusive OR circuit (hereinafter, simply referred to as EX OR circuit) 141 to 144, and these EX OR circuits 141 to 144 are input.
The timing signal P / N is input to the other end of 144.

Then, these EX OR circuits 141 to 14
The output of No. 4 is given to the PWM circuit 145. The PWM circuit 145 outputs the EX signal based on the timing signals CKN and φc.
A PWM signal having a pulse width corresponding to 4-bit image data provided via the OR circuits 141 to 144 is generated. For example, if the input data is "0001", a period for counting one timing signal φc, "0002"
Then, the period of counting the timing signal φc twice,
Each generates a PWM signal having a pulse width of "H". When the input data is "0000", the pulse width is all "L", and when the input data is "1111", the pulse width is all "H".
It is said that

The output of the PWM circuit 145 is supplied to one input terminal of the EX OR circuit 146, and the timing signal CKFS is applied to the other end of the EX OR circuit 146. The output of the EX OR circuit 146 is supplied to the output buffer 47, selects the voltage V1 or V3, and is supplied to the signal electrode of the liquid crystal display panel 15 as the signal electrode drive signal Yn.

Next, the operation of the embodiment configured as described above will be described. Now, as the liquid crystal display panel 15, FIG.
It is assumed that the liquid crystal display panel 15 has 5 × 10 5 pixels and the same halftone is displayed in the areas A to C of the liquid crystal display panel 15 and different halftones are displayed in the area D. The video signal V taken out through the sync separation circuit 12 is sampled by the A / D converter 13 at the sampling clock φs to obtain the 4-bit image data D1.
.About.D4, and further converted into a signal electrode drive signal Yn by the signal electrode drive circuit 14 and supplied to the liquid crystal display panel 15.

On the other hand, the scan electrode drive circuit 16 generates a scan electrode drive signal Xn and supplies it to the liquid crystal display panel 15 to scan the scan electrodes. The non-selection voltage of the scan electrode drive signal Xn is V2, and the selection voltage is switched between V0 and V4 in synchronization with the timing signal CKFC which is inverted every scanning period. Then, the signal electrode drive circuit 14
, The image data D1 to D4 are the timing signals P /
It is input to the PWM circuit 145 via the EX OR circuits 141 to 144 to which N is input. Timing signal P /
N is a signal whose phase is inverted with respect to the timing signal CKFC which is inverted every two scanning periods as shown in FIGS. 3A and 3C, and the image data D1 to D4 are synchronized with this timing signal P / N. "1" and "0" are inverted.

As a result, the EX OR circuits 141 to 144
Then, when the timing signal P / N is at H level, A / D
The image data from the converter 13 is inverted and the PWM circuit 14 is inverted.
5 on the other hand, while at the L level, the A / D converter 1
The image data from 3 has the same polarity as the PWM circuit 1
I will give it to 45. In the PWM circuit 145, as shown in FIG.
Pulse width modulation is performed according to the timing signal CKN shown in (d). In this case, the timing signal CKN delays the timing of the timing signal P / N having a period of two scanning periods by one scanning period.

As a result, in the PWM circuit 145, P /
When the N signal is in the H level period, a PWM signal having an off voltage period and an on voltage period corresponding to the data is generated from the data obtained by inverting the image data from the A / D converter 13 within one scanning period, and P During the L level period of the / N signal, the PWM signal having the off voltage period and the on voltage period corresponding to the image data from the A / D converter 13 is output within one scanning period.

The output from the PWM circuit 145 is E
Although it is supplied to the output buffer 46 via the X-OR circuit 146, since the EX OR circuit 146 receives the timing signal CKFS of one scanning period cycle, the EX OR circuit 146 functions as an inverter every other scanning period. Get to work. Then, the potentials V1 to V3 are output from the output buffer 46.
The signal electrode drive signal Yn having the amplitude of is generated and output to the liquid crystal display panel 15.

In this way, when the signal electrode application waveform X1 shown in FIG. 3 (g) is output as the signal electrode drive signal Xn with respect to the timing signal CKFC shown in FIG. 3 (a), the signal electrode drive signal Yn is output. As a result, the signal electrode applied waveforms Y1 to Y7 shown in FIG. 7E and the signal electrode applied waveforms Y8 to Y10 shown in FIG. , X1 -Y8 (
The applied waveforms of (~ Y10) are as shown in (h) and (i) of FIG.

In this case, the signal electrode applied waveforms Y1 to Y7,
At the time of switching from Y8 to Y10, glitches a to d are generated in the common applied waveform X1 as shown in FIG. 3 (g), and X1 to Y1 (to Y7) and X1 to Y8 (... Glitches a to d are also generated in the applied waveform of Y10). Of these, the liquid crystal display panel 15
In X1-Y1 (to Y7), the glitches b and c appear on the waveform, but since the polar directions are reversed, the fluctuation of the effective voltage can be almost eliminated, while the liquid crystal display panel 1
Even with X1 -Y8 (to Y10) of 5, glitches a and d appear on the waveform, but in this case as well, the polar directions are reversed, so that fluctuations in the effective voltage can be almost eliminated.

Therefore, in this way, the timing signal CKFS is inverted in one scanning period cycle and the timing signal CKFC is inverted in two scanning period cycles, and the timing signal P / N is changed to two.
By reversing in the scanning period cycle, at the timing in the middle of the two scanning periods except the switching timing of the period,
Since the change from the ON voltage to the OFF voltage and the change from the OFF voltage to the ON voltage of the signal electrode drive signal are set to be once or less respectively, a large whisker is not generated in the signal electrode drive waveform, and this whisker is not generated. It is possible to prevent the occurrence of uneven brightness on the screen of the liquid crystal display panel, which results in a good screen display on the liquid crystal display panel.

The present invention is not limited to the above-mentioned embodiments, and can be carried out by appropriately modifying it without changing the scope of the invention.

[0021]

According to the liquid crystal driving method of the present invention, it is possible to suppress the glitch of the scanning drive signal caused by the switching of the output waveform corresponding to the image signal of the signal electrode drive signal and reduce the fluctuation of the effective voltage. That is, so-called stringing can be improved and a high quality image display can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a signal electrode drive circuit used in an embodiment.

FIG. 3 is a waveform diagram for explaining the operation of the embodiment.

FIG. 4 is a diagram showing a display example of a liquid crystal display panel.

FIG. 5 is a diagram for explaining a signal electrode drive waveform by a conventional signal electrode drive circuit.

FIG. 6 is a diagram for explaining a signal electrode drive waveform by a conventional signal electrode drive circuit.

[Explanation of symbols]

11 ... Controller, 12 ... Sync separation circuit, 13 ... A /
D converter, 14 ... Signal electrode drive circuit, 141-144 ...
EX OR circuit, 145 ... PWM circuit, 146 ... EOR,
147 ... Output buffer, 15 ... Liquid crystal display panel, 16 ...
Scan electrode drive circuit.

Claims (1)

[Claims] 1. A liquid crystal driving method for driving a liquid crystal display panel by a scan electrode driving signal and a signal electrode driving signal,
When a period required for expressing a plurality of gradations from the minimum gradation to the maximum gradation is one gradation period, a plurality of gradations are expressed by a ratio of an on voltage and an off voltage in the one gradation period. In addition, in the liquid crystal driving method in which the scan electrode drive signal is inverted at a predetermined cycle to perform AC drive, the scan electrode drive signal is inverted in two scanning periods, and the signal electrode drive signal is turned from the ON voltage to the OFF voltage. By setting the switching cycle of 1 and the switching cycle from the off voltage to the on voltage to be the same as the inversion cycle of the scan electrode drive signal, the on voltage can be changed from the on voltage at a timing in the middle of the two scanning periods excluding the switching timing. And a turn-off voltage, and a turn-off voltage to a turn-on voltage are controlled once or less, respectively.