JPH06202591A - Liquid crystal driving circuit - Google Patents

Abstract

PURPOSE:To provide a liquid crystal driving circuit capable of reducing the so-called trailing thread phenomenon due to a glitch and obtaining an excellent image display. CONSTITUTION:This circuit is provided with a signal electrode driving circuit outputting a signal electrode driving signal according to an image signal and a scanning electrode driving circuit outputting a scanning electrode driving signal for a liquid crystal display pannel, and the output buffer 142 in the signal electrode driving circuit is constituted of MOS transistors 143-145, and capacitors 151, 152 are connected so as to delay a changeover speed in the switching of these MOS transistors 143-145.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit for driving a matrix type liquid crystal display panel.

[0002]

2. Description of the Related Art Conventionally, as a liquid crystal driving circuit for driving a liquid crystal display panel, an image signal is converted into a digital signal of a plurality of bits, and this is given to a signal electrode driving circuit to generate a predetermined signal electrode driving signal by pulse modulation. However, there is a device which can display an image having a halftone by giving it to a liquid crystal display panel together with a scan electrode drive signal.

FIG. 4 shows an output circuit of a signal electrode driving circuit of such a liquid crystal driving circuit. The output buffer 2 connected to the signal electrode driving circuit body 1 is a p channel M.
The OS transistor 21 and the p-channel MOS transistor 22 are connected in parallel, the source S thereof is connected to the drain D of the n-channel MOS transistor 23, the output terminal OUT is connected to this connection point, and each gate G is common. The output terminal of the signal electrode drive circuit body 1 is connected to this connection point, and this output terminal is connected to the p-channel MOS transistor 2 via the inverter 24.
In addition, the power source V1c is connected to the drains D of the p-channel MOS transistors 21 and 22 and the power source V3 is connected to the source S of the n-channel MOS transistor 23.

In such an output buffer 2, the operation of the p-channel MOS transistor 21 and the operations of the p-channel MOS transistor 22 and the n-channel MOS transistor 23 are alternately switched by the output from the signal electrode drive circuit main body 1 and the output terminal The signal electrode drive signal is output to OUT.

[0005]

However, the output buffer 2 as an output circuit of such a signal electrode driving circuit is used.
Since the transistors 21, 22, and 23 are designed to perform switching operation at high speed, the output terminal OUT
The transitional time of switching of the output signal electrode drive signal, that is, the rise and fall of the signal electrode drive signal waveform may affect the waveform of the scan electrode drive signal via the liquid crystal circuit. For example, when the signal electrode drive signal waveform as shown in FIG. 5A is output, the rising and falling of the signal electrode drive signal waveform causes a scan electrode drive signal waveform as shown in FIG. 5B. There is a problem that glitch a may occur, and the glitch a causes crosstalk called so-called stringing, which causes a remarkable deterioration in image quality.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal drive circuit which can reduce a so-called stringing phenomenon caused by glitches and can obtain a high quality image display.

[0007]

According to the present invention, in a liquid crystal drive circuit for supplying a scan electrode drive signal and a signal electrode drive signal to a liquid crystal display panel, a circuit for generating a signal electrode drive signal selects a plurality of voltages. For this purpose, a switching circuit using a MOS transistor is provided and means for delaying the switching speed of the switching of the MOS transistor is provided.

[0008]

As a result, according to the present invention, the signal electrode drive circuit intentionally delays the switching speed of the MOS transistor forming the output circuit thereof, and makes the rise and fall of the signal electrode drive signal waveform slow. By doing so, it becomes possible to reduce the glitch generated in the scan electrode drive signal waveform.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of the same embodiment. In the figure, the composite video signal is represented by a sync separation circuit 12.
After the vertical and horizontal synchronizing signals .phi.v, .phi.H and the video signal V are separated by the video signal V, the video signal V is converted by the A / D converter 13 into image data D1 to D4 which are digitized into predetermined bits, for example, 4 bits. . The digitized image data D1 to D4 are input to the signal electrode drive circuit 14.
The signal electrode drive circuit 14 includes a liquid crystal applied voltage generation circuit 17
The voltages V1 and V3 are supplied to the image data D1
The voltages V1 and V3 are selected in accordance with .about.D4 to generate a signal electrode drive signal Yn, which is applied to the signal electrode of the liquid crystal panel 15. Reference numeral 16 denotes a scan electrode drive circuit, which is supplied with voltages V0, V2, and V4 from a liquid crystal applied voltage generation circuit 17,
These voltages are appropriately selected to generate the scan electrode drive signal Xn to drive the scan electrodes of the liquid crystal panel 15.

Reference numeral 11 denotes a controller for controlling the overall timing, which is supplied with the vertical and horizontal synchronizing signals φv and φH from the sync separation circuit 11 and is supplied to the A / D converter 13 in synchronization with these synchronizing signals φv and φH. The sampling clock φs, the timing signals CKFS, P / N, and φc are supplied to the signal electrode drive circuit 14, and the timing signal CKFC is supplied to the scan electrode drive circuit 16. The timing signal CKFS is a signal for AC driving the liquid crystal display panel and is inverted every scanning period. The timing signal P / N is a signal in which the phase of the timing signal CKFC is inverted. Also, the timing signal CKFC
Is a signal which is always "H". The timing signal φc is
This is a signal for creating a PMW waveform and is generated 15 times during one scanning period.

The controller 11 generates various other timing signals (not shown) to control each circuit. FIG. 2 shows a schematic configuration of the signal electrode drive circuit 14. In this case, 141 is a signal electrode drive circuit body, and an output buffer 142 is connected to the signal electrode drive circuit body 141.

In this output buffer 142, a p-channel MOS transistor 143 and a p-channel MOS transistor 144 are connected in parallel, the drain S of the n-channel MOS transistor 145 is connected to their sources S, and the output terminal OUT is connected to this connection point. In addition, the respective gates G are connected in common, the output terminal of the signal electrode drive circuit body 141 is connected to this connection point, and this output terminal is connected via the inverter 146 to the p channel MO.
It is connected to the gate G of the S transistor 145, and p
The drain D of each of the channel MOS transistors 143 and 144 has a power source V1c and n channel MOS transistor 14
The power source V3 is connected to the source S of 5.

Further, the p channel MOS transistor 1
A capacitor 151 is connected in parallel with 43 and 144, and a capacitor 152 is connected in parallel with the n-channel MOS transistor 145. Next, the operation of the embodiment configured as described above will be described. Sync separation circuit 12
The video signal V taken out via the A / D converter 1
3 is sampled by the sampling clock .phi.s, converted into 4-bit image data D1 to D4, further converted into the signal electrode drive signal Yn by the signal electrode drive circuit 14 and supplied to the liquid crystal display panel 15.

On the other hand, the scan electrode drive circuit 16 generates a scan electrode drive signal Xn and supplies it to the liquid crystal display panel 15 to scan the scan electrodes. The non-selection voltage of the scan electrode drive signal Xn is V2, and the selection voltage is switched between V0 and V4 in synchronization with the timing signal CKFC which is inverted every scanning period. Then, the signal electrode drive circuit 14
Then, by the output from the signal electrode drive circuit body 141, p
Operation of Channel MOS Transistor 143, p Channel MOS Transistor 144 and n Channel MO
The operation of the S-transistor 145 is alternately switched, and a predetermined signal electrode drive signal is output to the output terminal OUT.

In this case, the operation of the p-channel MOS transistor 143 and the p-channel MOS transistor 14
Although the 4 and n channel MOS transistors 145 perform switching operation at high speed, here,
The capacitor 151 is connected in parallel to the p-channel MOS transistors 143 and 144, and the capacitor 152 is connected in parallel to the n-channel MOS transistor 145. The switching speed of is intentionally delayed.

Therefore, it takes a long transition time when the signal electrode drive signal output from the output terminal OUT is switched, so that the signal electrode drive signal waveform rises.
The falling edge becomes slow as shown in FIG. As a result, the influence on the scan electrode drive signal waveform is reduced through the liquid crystal circuit, and the glitch a generated in the scan electrode drive signal waveform becomes extremely small as shown in FIG. It is possible to reduce the crosstalk phenomenon called so-called string pull, which is caused by a.

Therefore, in this way, the signal electrode drive circuit 14 has the MOS constituting the output buffer 142 thereof.
The capacitors 151, 1 are configured to intentionally delay the switching speed of the switching of the transistors 143-145.
By connecting 52 to make the rise and fall of the signal electrode drive signal waveform slow, the glitch generated in the scan electrode drive signal waveform can be reduced, and crosstalk called thread pulling that is caused by this can be reduced. The phenomenon can be reduced and a high quality image display can be obtained.

The present invention is not limited to the above-mentioned embodiments, but can be carried out by appropriately modifying it within the scope of the invention.
For example, in the above-described embodiment, the capacitors 151, 15
2 is used to slow down the switching speed of each of the MOS transistors 143 to 145 so that the switching of the signal electrode drive signal waveform is moderated to reduce the glitch generated in the scan electrode drive signal waveform. Each M
By intentionally reducing the area of the MOS of the OS transistors 143 to 145 and increasing the conduction resistance, the switching of the signal electrode drive signal waveform is moderated to reduce the glitch generated in the scan electrode drive signal waveform. it can.

[0019]

According to the present invention, the switching speed of the switching of the MOS transistor forming the output circuit of the signal electrode drive circuit is intentionally delayed, and the rising and falling of the signal electrode drive signal waveform is slowed down. This reduces glitches generated in the scan electrode drive signal waveform,
It is possible to reduce the crosstalk phenomenon called so-called stringing, which is caused by the glitch, and it is possible to obtain a high-quality image display.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a signal electrode drive circuit used in an embodiment.

FIG. 3 is a waveform chart for explaining the operation of the embodiment.

FIG. 4 is a diagram showing a schematic configuration of a signal electrode drive circuit used in a conventional liquid crystal drive circuit.

5 is a waveform diagram for explaining the signal electrode drive circuit of FIG.

[Explanation of symbols]

11 ... Controller, 12 ... Sync separation circuit, 13 ... A /
D converter, 14 ... Signal electrode drive circuit, 141 ... Signal electrode drive circuit main body, 142 ... Output buffer, 143-145
... MOS transistor, 146 ... Inverter, 15 ... Liquid crystal display panel, 16 ... Scan electrode driving circuit, 151, 15
2 ... Capacitor.

Claims (1)

[Claims] 1. A liquid crystal drive circuit for supplying a scan electrode drive signal and a signal electrode drive signal to a liquid crystal display panel, wherein the circuit for generating the signal electrode drive signal is a switching circuit using MOS transistors for selecting a plurality of voltages. A liquid crystal drive circuit comprising: a means for delaying the switching speed of the switching of the MOS transistor.