JPH0667148A - Liquid crystal pannel drive circuit - Google Patents

Abstract

PURPOSE:To realize a liquid crystal pannel drive circuit capable of improving a response speed in a liquid crystal. CONSTITUTION:In a scanning electrode drive circuit 10, gate circuits 13a-13d are operated according to a frame signal phiF and a timing signal phiS, and a bias voltage is selected and sent to a multiplexer 12. By a signal electrode drive circuit 20, video data from a shift register 21 is latched by a latch/ gradation signal having circuit 22, and the same gradation signal m times in each selection period in a scanning electrode is formed and outputted to the multiplexer 23. By the multiplexer 23, the bias voltage is selected according to the gradation signal and outputted to a liquid crystal pannel 30 as a signal electrode drive signal Ym. The liquid crystal pannel 30 is driven by a synthesized waveform (Xn-Ym) between a scanning electrode drive signal Xn and the signal electrode drive signal Ym. By varying the pulse height value of the drive signal Xn for each scanning electrode at every divided period, a peak voltage in the synthesized waveform (Xn-Ym) becomes higher value than as usual, and then responsiveness is quickened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal panel drive circuit for driving a liquid crystal panel in which scanning electrodes and signal electrodes are arranged in a matrix.

[0002]

2. Description of the Related Art In general, a liquid crystal display device has a problem that the response speed is slow. In order to improve the response speed, improvement of a driving method, improvement of material, liquid crystal cell or the like has been considered conventionally. Has been.

However, conventionally, in the liquid crystal panel drive circuit for driving the liquid crystal panel in which the scan electrodes and the signal electrodes are arranged in a matrix, the scan electrode drive signal Xn and the signal electrode drive which show the signal waveforms shown in FIG. The liquid crystal panel is driven by the signal Ym. That is, the scan electrode drive signal Xn generates a bias voltage of V0 or V4 at a constant level according to the frame signal φF and sequentially applies it to the scan electrodes, and the signal electrode drive signal Ym has a level of V1 or V3 depending on the video signal. A bias voltage is selected and applied to the signal electrode. Therefore, the composite voltage of "Xn-Ym" shown in FIG. 7 is applied between the scan electrode and the signal electrode, and the signal electrode corresponding to the scan electrode selected by the scan electrode drive signal is driven. Although the liquid crystal panel is driven as described above, the conventional liquid crystal panel driving method cannot sufficiently improve the response speed of the liquid crystal. The present invention has been made in view of the above circumstances, and an object thereof is to provide a liquid crystal panel drive circuit capable of improving the response speed of liquid crystal.

[0004]

According to the present invention, in a liquid crystal panel drive circuit for driving a liquid crystal panel in which scanning electrodes and signal electrodes are arranged in a matrix, a selection period of one scanning electrode is divided by m. The same data is displayed once, and the crest value is made different for each of the divided periods with respect to the scan electrode drive signal.

Further, according to the present invention, in a liquid crystal panel drive circuit for driving a liquid crystal panel in which scanning electrodes and signal electrodes are arranged in a matrix, a selection period of one scanning electrode is m.
The display is performed by dividing the same data m times, and the crest value of the signal electrode drive signal is made different for each divided period.

Further, according to the present invention, in a liquid crystal panel drive circuit for driving a liquid crystal panel in which scanning electrodes and signal electrodes are arranged in a matrix, a selection period of one scanning electrode is divided into m and display is performed by the same data m times. The crest value of the scan electrode drive signal and the signal electrode drive signal is made different for each divided period.

[0007]

As described above, the peak voltage during the scan electrode period becomes higher than in the conventional case by making the peak value different for each of the divided electrode periods for the scan electrode drive signal and / or the signal electrode drive signal. The response speed of the liquid crystal can be improved.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, 10 is a scan electrode drive circuit,
Reference numeral 20 is a signal electrode driving circuit, and 30 is a liquid crystal panel in which N scanning electrodes and M signal electrodes are arranged in a matrix. The scan electrode drive circuit 10 mainly includes a scan electrode shift register 11 and a multiplexer 12. The scan electrode shift register 11 sequentially reads a vertical timing signal synchronized with a vertical synchronization signal sent from a control unit (not shown) by the horizontal synchronization signal and shifts it, and shifts the shifted signal.
Output to. Further, a bias voltage V2 is directly applied to the multiplexer 12 and the bias voltage V2 is applied.
01, V02, V41 and V42 are applied through the gate circuits 13a to 13d. The bias voltages V01, V02 (V41,
V42) is the bias voltage V0 (V4
) Is set to a value obtained by "±" by a constant voltage v.

The gate circuits 13a to 13d are also provided.
Are controlled by a frame signal .phi.F and a timing signal .phi.S provided via AND circuits 14a to 14d. That is, the frame signal φF is the AND circuit 14
a and 14b are directly input to the AND circuits 14c and 14d via the inverter 15, and the timing signal .phi.S is directly input to the AND circuits 14a and 14c and via the inverter 16 to the AND circuits 14b and 14d.
It is input to d. Then, the AND circuits 14a-14
The gate circuits 13a to 13d are turned on / off by the output signal of d.
The OFF voltage is controlled, and the bias voltages V01, V02, V41, V42 are selected and sent to the multiplexer 12.

The frequency of the timing signal φ S is determined according to the number m of divisions in each scanning electrode selection period.
For example, when the division number m is “2”, the frame signal φF
Is set to twice the frequency. The multiplexer 12
Selects the bias voltage in accordance with the signal from the scan electrode shift register 11, and outputs the scan electrode drive signals X1 and X2.
2, ... XN is output to the liquid crystal panel 30.

On the other hand, the signal electrode driving circuit 20 is composed of a signal electrode driving shift register 21, a latch & gradation signal generating circuit (PWM circuit) 22 and a multiplexer 23. The latch & gradation signal generating circuit 22 includes a frame. Signal φ
F is given to the multiplexer 23 and the bias voltage V
1, V3 is given.

The above-mentioned signal electrode driving shift register 21
Display data sequentially sent from the preceding circuit, for example, 4-bit video data is sequentially read and shifted, and data for one line is read and then transferred to the latch & gradation signal generating circuit 22. This latch & gradation signal creation circuit 22
Latches the data sent from the signal electrode driving shift register 21, creates a gradation signal in accordance with the latched data, and inverts it every time the signal level of the frame signal φF changes to the multiplexer 23. Output.
In this case, the latch & gradation signal generating circuit 22 divides each scanning electrode selection period into m (m ≧ 2), and generates gradation signals m times for the same display data (video data). Output to the multiplexer 23. In this embodiment, "m =
The case where it is set to "2" will be described.

The multiplexer 23 selects the bias voltages V1 and V3 according to the gradation signal sent from the latch & gradation signal generating circuit 22, and outputs the signal electrode drive signal Y1.
~ YM is output to the liquid crystal panel 30.

Next, the operation of the above embodiment will be described with reference to the timing chart of FIG. Scan electrode drive circuit 10
The ON / OFF operation of the gate circuits 13a to 13d is controlled according to the frame signal φF and the timing signal φS, and the bias voltages V01, V02, V41 and V42 are selected and sent to the multiplexer 12.

That is, since the AND circuits 14a and 14b are selected when the frame signal .phi.F is at the high level, the output of the AND circuit 14a becomes "1" when the timing signal .phi.S is at the high level, and the gate circuit 13a is selected. The bias voltage V01 is selected by this, and when the timing signal .phi.S is low level, the output of the AND circuit 14b becomes "1" and the gate circuit 13b selects the bias voltage V02.

In this case, the frequency of the timing signal φS is set according to the number of divisions of the selection period of each scan electrode. When the number of divisions m is 2, the frame signal φF
The frequency is twice as high as the above, and the first half is set to the high level and the second half is set to the low level for each frame. Therefore, when the frame signal .phi.F is at the high level, the bias voltage V01 is selected in the first half and V02 is selected in the latter half and sent to the multiplexer 12.

Further, in the frame in which the frame signal φF is at the low level, the AND circuits 14c and 14d are selected. Therefore, the bias voltage V41 is selected in the first half when the timing signal φS becomes the high level, and the timing signal φS becomes the low level. In the latter half, the bias voltage V42 is selected and sent to the multiplexer 12. The multiplexer 12 is provided with the gate circuit 13a for the scan electrode selected by the scan electrode shift register 11.
In the frame in which the bias voltage applied via the ˜13d, that is, the frame signal φF is high level, V01
Voltage, V02 voltage in the latter half is selected, and in the frame in which the frame signal φF is at low level, the V41 voltage in the first half and V42 in the second half are selected.
The voltage is selected and output to the liquid crystal panel 30 as the scan electrode drive signal Xn. The multiplexer 12 also supplies the bias voltage V2 to the other non-selected scan electrodes.

On the other hand, in the signal electrode drive circuit 20,
A gradation signal is created by the latch & gradation signal creating circuit 22 based on the video data input to the signal electrode driving shift register 21. In this case, the latch & gradation signal generation circuit 22 latches the video data sent from the signal electrode driving shift register 21, and m times, for example, twice in each selection period of the scan electrodes with respect to this latched data. The same gradation signal is created and output to the multiplexer 23. As shown in FIG. 2, the multiplexer 23 selects the bias voltages V1 and V3 according to the gradation signal from the latch & gradation signal generating circuit 22 and outputs them as the signal electrode drive signal Ym to the liquid crystal panel 30. Note that FIG. 2 shows a signal waveform when 50% gradation is applied to the video data.

The liquid crystal panel 30 is driven by a composite waveform "Xn-Ym" of the scan electrode drive signal Xn given from the scan electrode drive circuit 10 and the signal electrode drive signal Ym given from the signal electrode drive circuit 20.

The peak voltage in the composite waveform "Xn-Ym" is ".vertline.V01 + V1.vertline." In the frame in which the frame signal .phi.F is at the high level, and "-V01 + V1.vertline." In the frame at the low level.
| V01 + V1 | ”. In this case, the scan electrode drive signal Xn is set so that the level is different for each divided period as described above, but if the liquid crystal material is the same, the liquid crystal drive effective voltage is the same as in the conventional case and the bias voltage thereof is the same. V
The relationship between 01 and V0 is "V0 <V01". Therefore, as shown in FIG. 2, the peak voltage │V01 + V1│ during the scan electrode period in the composite waveform "Xn-Ym" has a higher value than before. It is generally said that liquid crystal is driven by an effective value, but from a microscopic point of view, the molecules seem to start moving due to the voltage applied instantly. For this reason, the peak voltage applied to the liquid crystal becomes high, and the responsiveness becomes fast. [Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG.

In the first embodiment described above, the peak level (when selected) of the scan electrode drive signal is changed. In the second embodiment, the peak level is changed with respect to the signal electrode drive signal. It is the one.

That is, as shown in FIG. 3, the scan electrode drive circuit 10 is mainly composed of a scan electrode shift register 11 and a multiplexer 12, and the multiplexer 12
Is directly inputted with the bias voltage V2, and the bias voltages V01 and V4 are inputted via the gate circuits 17a and 17b. Then, the gate circuit 17a outputs the frame signal φ.
F is directly input to the gate terminal, and the frame signal φ F is input to the gate circuit 17b via the inverter 18.

Therefore, when the frame signal .phi.F is at the high level, the gate circuit 17a selects the bias voltage V0, and when the frame signal .phi.F is at the low level, the gate circuit 17b selects the bias voltage V4 to the multiplexer 12. Sent. This multiplexer 12
Selects the bias voltages V0 and V4 together with the bias voltage V2 based on the electrode selection signal sent from the scan electrode shift register 11, and scan electrode drive signals X1 to XN.
To the liquid crystal panel 30. That is, the multiplexer 12 outputs the bias voltage V0 or V4 to the scan electrode selected by the scan electrode shift register 11, and outputs the bias voltage V2 to the other non-selected electrodes.

On the other hand, the signal electrode driving circuit 20 is composed of a signal electrode driving shift register 21, a latch & gradation signal generating circuit 22 and a multiplexer 23. The bias voltage V11, V12, V31,
V32 is supplied through the gate circuits 24a to 24d.
The bias voltages V11 and V12 are values obtained by dividing the bias voltage V1 by a constant voltage v, and the bias voltages V31 and V32.
Is set to a value obtained by plus or minus a constant voltage v with respect to the bias voltage V3.

The timing signal .phi.S is directly input to the gate circuits 24a to 24c, and the gate circuit 2
The timing signal .phi.S is supplied to the inverter 2 at 4b and 24d.
Input via. Therefore, when the frame signal φF is at the high level, the gate circuits 24a and 24c select the bias voltages V11 and V31, respectively, and the frame signal φF is selected.
Is low level, the bias voltages V12 and V32 are selected by the gate circuits 24b and 24d and supplied to the multiplexer 23. The multiplexer 23 selects the bias voltage based on the gradation signal from the latch & gradation signal generating circuit 22, and outputs it to the liquid crystal panel 30 as the signal electrode drive signals Y1 to YM.

FIG. 4 is a timing chart showing the operation of the second embodiment. In FIG. 3, the scan electrode driving circuit 10 includes a gate circuit 1 according to the frame signal φF.
The on / off operation of 7a and 17b is controlled, and the bias voltages V0 and V4 are selected and sent to the multiplexer 12. That is, when the frame signal φF is at the high level, the gate circuit 17a is turned on and the bias voltage V0 is supplied to the multiplexer 12. When the frame signal φF is at the low level, the gate circuit 17b is turned on and the bias voltage is changed. V4 is supplied to the multiplexer 12. Therefore, the multiplexer 12 supplies the bias voltage V0 or V4 to the scan electrode selected by the scan electrode shift register 11 as shown in FIG. 4, and V2 to the other non-selected electrodes. Drive signal X1 ~
Output as XN.

On the other hand, in the signal electrode drive circuit 20,
Gate circuits 24a to 24d according to the timing signal .phi.S.
Thus, the bias voltages V11, V12, V31, V32 are selected and input to the liquid crystal panel 30. That is, when the timing signal φS is at high level, the gate circuits 24a,
24c is turned on and the bias voltages V11 and V31 are selected,
When the timing signal .phi.S is low level, the gate circuits 24b and 24d are turned on and the bias voltages V12 and V12.
32 is selected and input to the liquid crystal panel 30. Therefore,
The composite waveform "Xn-Ym" shown in FIG. 4 is applied between the scanning electrodes of the liquid crystal panel 30 and the peak voltage thereof is "| V0.
+ V11 | ”. As a result, the peak voltage │V0 + V11│ during the scan electrode period in the composite waveform "Xn-Ym" becomes higher than in the conventional case, and the response speed is improved, as in the first embodiment. [Third Embodiment] FIG. 5 shows a third embodiment of the present invention.

The third embodiment is the same as the first embodiment and the second embodiment.
In the first embodiment, the scan electrode driving circuit 10 is combined with the first embodiment.
The embodiment and the signal electrode drive circuit 20 have the same configuration as that of the second embodiment. Therefore, as shown in the timing chart of FIG. 6, the scan electrode drive signal and the signal electrode drive signal have signal waveforms that change in synchronization with the timing signal φS. Therefore, in the combined waveform "Xn-Ym" of the scan electrode drive signal and the signal electrode drive signal, the peak voltage during the scan electrode selection period is "| V01 + V11 |", which is different from the cases of the first and second embodiments. It becomes higher, and the response of the liquid crystal can be further improved.

[0030]

As described in detail above, according to the present invention, in a liquid crystal panel drive circuit for driving a liquid crystal panel in which scan electrodes and signal electrodes are arranged in a matrix, the selection period of one scan electrode is m. Since the display is performed by dividing the same data m times and the peak value is made different for each of the divided periods with respect to one or both of the scan electrode drive signal and the signal electrode drive signal, the peak value during the scan electrode period is reduced. The peak voltage becomes higher than in the past, and the response speed of the liquid crystal can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the embodiment.

FIG. 5 is a block diagram showing the configuration of a third embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the embodiment.

FIG. 7 is a timing chart for explaining a conventional liquid crystal panel driving method.

[Explanation of symbols]

10 ... Scan electrode drive signal, 11 ... Scan electrode shift register, 12 ... Multiplexer, 13a to 13d, 17a
-17d ... Gate circuit, 20 ... Signal electrode drive circuit, 21
... Signal electrode driving shift register, 22 ... Latch & gradation signal creating circuit, 23 ... Multiplexer, 24a to 24d
... Gate circuit, 30 ... Liquid crystal panel.

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[Procedure amendment]

[Submission date] March 30, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

[0003] Thus, conventionally, in the liquid crystal panel driving circuit and the scanning electrodes and signal electrodes to drive the liquid crystal panel are arranged in a matrix form, scan electrode driving signal Xn and signal electrodes showing a signal waveform in FIG. 7 The liquid crystal panel is driven by the drive signal Ym. That is, the scan electrode drive signal Xn generates a bias voltage of V0 or V4 at a constant level according to the frame signal φF and sequentially applies it to the scan electrodes, and the signal electrode drive signal Ym has a level of V1 or V3 depending on the video signal. A bias voltage is selected and applied to the signal electrode. Therefore, the composite voltage of "Xn-Ym" shown in FIG. 7 is applied between the scan electrode and the signal electrode, and the signal electrode corresponding to the scan electrode selected by the scan electrode drive signal is driven. Although the liquid crystal panel is driven as described above, the conventional liquid crystal driving method cannot sufficiently improve the response speed of the liquid crystal. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal drive panel drive circuit capable of improving the response speed of liquid crystal.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (3)

[Claims] 1. In a liquid crystal panel drive circuit for driving a liquid crystal panel in which scanning electrodes and signal electrodes are arranged in a matrix, a selection period of each scanning electrode is divided into m and display is performed by the same data m times. A liquid crystal panel drive circuit comprising: a control means; and a crest value control means for varying a crest value of a drive signal for each scan electrode for each divided period. 2. In a liquid crystal panel drive circuit for driving a liquid crystal panel in which scan electrodes and signal electrodes are arranged in a matrix, a selection period of each scan electrode is divided into m and display is performed by the same data m times. A liquid crystal panel drive circuit comprising: a control means; and a crest value control means for varying a crest value of a drive signal for each of the signal electrodes for each of the divided periods. 3. In a liquid crystal panel drive circuit for driving a liquid crystal panel in which scanning electrodes and signal electrodes are arranged in a matrix, a selection period of each scanning electrode is divided into m and display is performed by the same data m times. A liquid crystal panel drive circuit comprising: a control means; and a crest value control means for varying a crest value of a drive signal for the scan electrode and the signal electrode for each divided period.