JP2985017B2 - Driving method of electro-optical display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a flat-type electro-optical display device, particularly a matrix-type liquid crystal display device.

[0002]

2. Description of the Related Art FIG. 4 is a matrix diagram of a conventional liquid crystal display device. FIG. 5 is a conventional drive waveform diagram. FIG.
In the display device, the first electrode group and the second electrode group have a matrix structure, and the first electrode group is scanned and driven by the common electrode driving circuit 32. The second electrode group is driven by the segment drive circuit 31 with a signal corresponding to display data. The display data signal D is input to the segment drive circuit 31. The display data signal D is shifted by a shift clock signal (not shown), latched by a latch signal CP1, and drives the second electrode drive electrode by a drive signal corresponding to the display data. The common electrode drive circuit 32 converts the frame signal FLM into the shift signal C
This is a method of driving a display device by performing line-sequential scanning by shifting by P1 (the latch signal).

[0003]

However, in the case of the conventional display method, the larger the size of the display device and the higher the display density, the larger the width of the electrode patterns of the first and second electrode groups. Since the electrode pattern becomes narrow, the resistance value of the electrode pattern increases.
Therefore, there has been a problem that the difference between the display contrast near the drive circuit of the display panel and the display contrast at the other end is clearly recognized. For this reason, there have been problems such as the narrowing of the optimum driving voltage range and the inability to uniformly display the gradation display over the entire screen.

Accordingly, an object of the present invention is to provide a visually uniform display contrast even if the resistance value of the electrode pattern is high, in order to solve the conventional problems as described above.

[0005]

According to the present invention, a common electrode driving circuit for driving a first electrode group of an electro-optical display device is provided at both ends of a panel. Line-sequential scanning of the group can be alternately driven by the common drive circuits at both ends.

[0006]

As described above, in the electro-optical display device,
Even if a voltage drop occurs due to the resistance value of the electrode pattern, the contrast level of the display contrast is switched alternately left and right for each line, so that the contrast difference is averaged as a whole.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention.
In FIG. 1, a frequency dividing circuit 1 constitutes first and second display inhibition signal generating circuits, a few constitute first and second scanning shift clock signal generating circuits, Is the first,
A second frame signal generation circuit is configured.

[0008] CP1 is a shift clock signal for shifting the scanning signal. FLM is a frame signal for starting scanning. Next, the operation of this circuit will be described. The frame signal FLM is input to the frame signal generation circuit 5 (one-shot multi-circuit) and
Is output. The output of the frame signal generating circuit 5 is connected to another frame signal generating circuit 6 (W).
Is inputted to-shot multivibrator circuit) outputs the second frame signal EFLM with. Here, the phases of the first and second frame signals OFLM and EFLM are set to 1 by adjusting the time constant.
It is set so as to be shifted during the scanning period. Next, the shift clock signal CP1 is input to the display prohibition signal generation circuit 1 which is a frequency dividing circuit, and outputs a display prohibition signal DE1 of a signal that is divided by ２. The display inhibition signal DE
1 and its inverted signal, and input to the first and second scanning shift clock signal generation circuits (AND circuits) 2 and 3 to generate the first and second shift clock signals OCP1 and ECP.
1 is output.

FIG. 2 is a diagram of a display device showing one embodiment of the present invention. In FIG. 2, reference numeral 21 denotes a segment electrode drive circuit for driving the second electrode group. Reference numeral 22 denotes an odd line common electrode drive circuit for driving odd scan lines of the first electrode group. Reference numeral 23 denotes an even-line common electrode drive circuit that drives an even-numbered scan line. OFLM and EF of the first and second frame signals
LM is a frame signal for the odd-line and even-line common electrodes for starting scanning from the first line.

The first and second shift clock signals OCP1 and ECP1 are shift clock signals for the odd-line and even-line common electrode driving circuits 22 and 23, respectively. D is a display data signal, and CP1 is a latch signal for latching the display data signal.
DE1 and DE2 are display prohibition signals for forcibly prohibiting scanning drive and outputting a non-selection drive signal. The configuration is as described above.

FIG. 3 is a timing chart of signals for explaining the present invention. FLM in FIG. 3 indicates a frame signal of a conventional display panel. Next, the operation of this embodiment will be described. In FIG. 2, the display data signal D is input to the segment electrode drive circuit 21.
Then, data is latched by the latch signal CP1, and a display drive signal is output to the second electrode group. On the other hand, odd-line and even-line frame signals OFLM, EFLM
Are input to the odd line common and even line common electrode drive circuits, respectively. Each of these frame signals is driven by line shift scanning with each of the shift clock signals OCP1 and ECP1. Here, the shift clock signals OCP1 and ECP1 have a cycle twice as long as the display data latch signal CP1, and have a timing that is shifted by one cycle. A display inhibit signal DE which is a frequency-divided signal of the latch signal CP1
1 is input to the odd-numbered line common electrode drive circuit 22. Further, a display inhibition signal of DE2 having a phase opposite to that of DE1 is input to the even-line common electrode drive circuit 23. The display inhibition signals DE1 and DE2 are at the signal level “L”.
At this time, an operation is performed to forcibly prohibit the scanning drive and output the non-selection signal. Therefore, it can be understood that the common electrodes are alternately scanned by the odd line common electrode drive circuit 22 and the even line common electrode drive circuit 23.

[0012]

According to the present invention, as described above, odd-numbered lines and even-numbered lines are divided into common electrode drive circuits and driven from both sides of the panel to reduce the unevenness of contrast caused by line resistance for each line. With the configuration of distributing right and left, the contrast unevenness of the entire panel could be greatly improved. Further, even when performing gradation display, there is an effect that uniform gradation display can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram of a display device showing one embodiment of the present invention.

FIG. 3 is a timing chart of the present invention.

FIG. 4 is a circuit diagram of a conventional display device.

FIG. 5 is a conventional timing chart.

[Explanation of symbols]

1 Divider circuit (first and second display inhibit signal generation circuits) 2, 3 AND circuit (first and second scan shift clock signal generation circuits) 5, 6 One-shot multi-circuit (first and second) Frame signal generation circuit) 21 Segment electrode drive circuit 22 Odd line common electrode drive circuit 23 Even line common electrode drive circuit 24 Matrix panel

Claims (1)

(57) [Claims] 1. A first electrode group for scanning display and a second electrode group for driving according to display data are arranged in a matrix, and intersections thereof are used as display pixels to drive the first electrode group. The driving unit is divided into at least two, a driving unit 1 and a driving unit 2, and the shift unit includes a shift clock signal for shifting a scan line and a frame signal for starting scanning. The first is to divide the clock signal and forcibly prohibit display.
A second display inhibit signal generation circuit, first and second scan shift clock signal generation circuits for generating two scan shift clock signals having a phase twice as long as the period of the scan shift clock signal, and the frame signal; And the first and second frame signal generation circuits for generating frame signals having phases substantially different from each other for one scanning period, and the driving unit 1 and the driving unit 2 are alternately scanned and driven line by line. For driving a dynamic display device.