JPH0546123A - Liquid crystal driving device - Google Patents

Abstract

PURPOSE:To obtain a sufficient write time for liquid crystal even when gate lines increase by scanning odd-numbered and even-num bered gate lines of a liquid crystal panel independently by a 1st and a 2nd gate driver and then making the scanning time of each gate line twice as long as before. CONSTITUTION:In 21 and 22 are the gate drivers. The gate driver 21 is connected to the odd-numbered gate lines 151, 153,...15n-1 among the gate lines 151-15n of the liquid crystal panel and scans them in order and the gate driver 22, on the other hand, is connected to the even-numbered gate lines 152, 154,...15n and scans them in order. The gate drivers 21 and 22 are supplied with start pulses SP1 and SP2 and clock pulse CLK1 and CLK2 generated by a pulse generating circuit 23 to operate. Consequently, the write time of the liquid crystal can be made sufficiently long, which is useful for practical use.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving device, and more particularly to a liquid crystal driving device for driving an active matrix type liquid crystal panel for display.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an example of a conventional liquid crystal driving device. In the figure, 10 is an active matrix type liquid crystal panel, 11 is a data driver for setting data of each line to the data lines 12 _{1 to} 12 _m of the liquid crystal panel 10, and 14 is a gate line corresponding to a scanning line of the liquid crystal panel 10. The gate driver sequentially scans 15 ₁ to 15 _m . Data line 12 _{1 to} 12 _{m of} liquid crystal panel 10
A thin film transistor (TFT) as a switching element is provided at each intersection between the gate line 15 ₁ and the gate line 15 ₁ to 15 _n.
Each TFT is driven according to the data set by the data driver 11 on the gate line of the book, and display is performed.

[0003]

The video signal of the Japanese television standard system has about 240 effective display scanning lines in one field. This video signal is an active matrix type liquid crystal having a gate line number n of 480. In the case of displaying with, the two lines adjacent to each other in the odd field (eg, gate lines 15 ₁ and 15 ₂ ) are driven with the same data as shown in FIG. For example, gate line 15 ₂
And 15 ₃ ) as one set and driven by the same data for non-interlaced display.

[0004] must sequentially scan the gate lines 15 ₁ to 15 _n for each field in this Conventionally device must drive the gate driver at twice the speed of the interlaced display when a liquid crystal panel There has been a problem that the writing time of the liquid crystal becomes insufficient as the number of gate lines increases with the progress of higher definition.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a liquid crystal driving device that can take a sufficient time for writing liquid crystal.

[0006]

A liquid crystal driving device of the present invention is a liquid crystal driving device for driving a display of an active matrix type liquid crystal panel, and a first gate driver for sequentially scanning odd-numbered gate lines of the liquid crystal panel. , A second scan for sequentially scanning the even-numbered gate lines of the liquid crystal panel
And a gate driver.

[0007]

According to the present invention, the first and second gate drivers separately scan the odd-numbered and even-numbered gate lines of the liquid crystal panel, thereby making the scanning time of each gate line twice as long as the conventional one. Even if the number of lines is increased, the liquid crystal writing time can be sufficiently taken.

[0008]

1 is a block diagram of an embodiment of the device of the present invention. 6, those parts which are the same as those corresponding parts in FIG. 6 are designated by the same reference numerals, and a description thereof will be omitted.

In FIG. 1, reference numerals 21 and 22 denote gate drivers, respectively. The gate driver 21 is connected to odd-numbered gate lines 15 ₁ , 15 ₃ , ... 15 _n-1 of the gate lines 15 ₁ to 15 _n of the liquid crystal panel 10 and sequentially scans them, and the gate driver 22 is an even number. the gate lines 15 _2, 15 _4, and is connected to ... 15 _n, to scan them sequentially.

Here, n is an even number, for example, 480.

The gate drivers 21 and 22 are respectively supplied with the start pulses SP1 and SP2 and the clock pulses CLK1 and CLK2 generated by the pulse generation circuit 23 to operate.

FIG. 2 shows a block diagram of the gate driver. In the figure, a start pulse SP and a clock pulse CLK are input to the shift register 30 from terminals 31 and 32, respectively. The shift register 30 has an n / 2-stage configuration, and shifts bits that are sequentially turned on from the first stage to the n / 2-th stage at each rise of the clock pulse CLK after the fall of the start pulse SP. The output of each stage of the shift register 30 is supplied to each stage of the level shifter 33 having an n / 2 stage structure, and the bit turned on here is level-shifted to a voltage V _LCD (for example, 25 V) sufficient to drive the liquid crystal. It Each stage of the level shifter 33 is connected to each of n / 2 gate lines of the liquid crystal panel 10 via buffers 34 _{1 to} 34 _{n / 2} .

Here, the pulse generation circuit 23 shown in FIG.
Start pulses SP1 and SP2 shown in (A) and (B) and clock pulses CLK1 and C having the same phase as shown in FIG.
LK2 is generated and supplied to the gate drivers 21 and 22, respectively. In this case, the gate driver 21 sequentially drives and scans the odd-numbered gate lines 15 ₁ , 15 ₃ , ... 15 _n-1 in the odd field as shown in FIGS. Scans by driving even-numbered gate lines 15 ₂ , 15 ₄ , ... 15 _n sequentially in the even field as shown in FIGS.

[0014] This gate lines 15 ₁ to 15 _n of the liquid crystal panel 10 by the performed scan interlace scanning speed be taken sufficiently 1/2, LCD write time of the conventional apparatus shown in FIG. 6 it can.

Next, in the pulse generation circuit 23, as shown in FIG.
The start pulses SP1 and SP2 shown in FIG.
In-phase clock pulses CLK1 and CLK shown in (C)
2 is generated and supplied to each of the gate drivers 21 and 22. In this case, the gate driver 21 sequentially drives and scans the odd-numbered gate lines 15 ₁ , 15 ₃ , ... 15 _n-1 in the odd and even fields as shown in FIGS. At the same time, the gate driver 22 has even-numbered gate lines 15 ₂ , 15 ₄ , ... In the odd and even fields as shown in FIGS.
15 _n are sequentially driven to scan.

As a result, the two adjacent fields in the odd field
Scanning is performed with a set of lines (for example, gate lines 15 ₁ and 15 ₂ ) as a set, and adjacent two lines (for example, gate lines 15 ₂ and 1 ₂ ) shifted by 1 line in an even field.
The scanning is performed with 5 ₃ ) as one set and non-interlaced scanning is performed. Even in this case, the scanning speed is 1 of that of the conventional device.
It becomes / 2 and the writing time of the liquid crystal can be sufficiently taken.

Further, in the pulse generating circuit 23 shown in FIG.
Start pulses SP1 and SP2 as shown in FIG. 5F, and clock pulse C of opposite phase as shown in FIGS. 5B and 5G.
LK1 and CLK2 to generate gate drivers 21 and 2
Supply to each two. In this case, as in the embodiment of FIG. 4, scanning is performed with two adjacent lines in the odd field (for example, gate lines 15 ₁ and 15 ₂ ) as one set, and in the even field, adjacent two lines shifted by one line (for example, gate lines 15 ₁ and 15 ₂ ). The gate lines 15 ₂ and 15 ₃ ) are used as a set for scanning and non-interlaced scanning is performed, but the scanning of the lower line is always delayed by 1/2 clock cycle from the scanning of the upper line of each set. The scan is performed.

Such scanning is applied by the present applicant to Japanese Patent Application No. 3-55046, entitled "Liquid Crystal Display Device", dated March 19, 1991.

According to the proposed invention, the pixel electrodes arranged along the first to nth display lines and the pixel electrodes arranged in a direction orthogonal to the display lines are connected to the pixel electrodes via a switching element, An active matrix type liquid crystal panel comprising a data electrode for supplying a voltage based on pixel data to the electrode and a gate electrode arranged along the display line for controlling ON / OFF of the switching element. In the liquid crystal display device, the first and second display lines, the second and third display lines ... The (n−1) th and nth display lines, the nth and first display lines, ... A gate electrode driving circuit for driving the gate electrode, and an i-th and an i + 1-th (i = 1)
An integer from ~ n. However, in the case of i = n, when the gate electrode of the display line of i + 1 = 1) is driven, the data electrode is driven based on the pixel data of the i-th display line, and in this case, the i−1-th display line is driven. The difference between the gradation obtained for the pixels of the display line and the gradation obtained for the pixels of the i-th display line is obtained for each pixel, and is determined as the pixel of the (i-1) -th display line in the same vertical column. For the pixels of the i-th display line for which a gray level higher than the obtained gray level is required, a voltage larger than the voltage required to obtain the maximum gray level is applied to the pixel of the i-th display line.
After charging the liquid crystal layer of the pixel of the display line of No. 1 and charging the liquid crystal layer of the pixel of the i-th display line to a target voltage, a voltage larger than the voltage required to obtain the maximum gray scale is applied. The application is stopped, the target voltage is applied, and the gray level lower than the gray level required for the pixel of the (i-1) th display line in the same vertical column is required. For the pixels on the line, a voltage smaller than the voltage required to obtain the minimum gray level is applied to discharge the liquid crystal layer of the pixels on the first display line, and the liquid crystal layer of the pixels on the i th display line is discharged. After discharging to the target voltage, the application of a voltage smaller than the voltage required to obtain the minimum gray level is stopped so that the target voltage is applied, and the i-th column in the same vertical column is Find the same gray level as the gray level found for the pixels on the 1st display line The pixel of the i-th display line is provided with a data electrode drive circuit for driving the data electrode so that a target voltage is applied to the liquid crystal layer of the pixel of the i-th display line from the beginning. Voltage applied to the liquid crystal layer that is greater than the voltage required to obtain the maximum gray level when the liquid crystal layer is charged, and is higher than the voltage required to obtain the minimum gray level when the liquid crystal layer is discharged. A small voltage is applied to the liquid crystal layer to speed up the writing time to the liquid crystal layer.

[0020]

As described above, according to the liquid crystal drive device of the present invention, the writing time of the liquid crystal can be sufficiently taken, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a device of the present invention.

FIG. 2 is a block diagram of a pulse generation circuit.

FIG. 3 is a signal timing chart of the device of the present invention.

FIG. 4 is a signal timing chart of the device of the present invention.

FIG. 5 is a signal timing chart of the device of the present invention.

FIG. 6 is a block diagram of an example of a conventional device.

FIG. 7 is a diagram for explaining non-interlace.

[Explanation of symbols]

10 liquid crystal panel 11 data driver 12 _{1 to} 12 _m data line 15 ₁ to 15 _n gate line 21, 22 gate driver 23 pulse generation circuit

Claims (1)

[Claims] 1. A liquid crystal driving device for driving a display of an active matrix type liquid crystal panel (10), wherein an odd-numbered gate line (15) of the liquid crystal panel (10) is provided.
_{A first} gate driver (21) for sequentially scanning ₁ , 15 ₃ , ... 15 _{n- 1} ) and an even-numbered gate line (15) of the liquid crystal panel (10).
A liquid crystal drive device having a second gate driver (22) that sequentially scans ₂ , 15 ₄ , ... 15 _n ).