JPH0610695Y2 - 半導体素子収納用パッケージ - Google Patents

半導体素子収納用パッケージ

Info

Publication number
JPH0610695Y2
JPH0610695Y2 JP1987145802U JP14580287U JPH0610695Y2 JP H0610695 Y2 JPH0610695 Y2 JP H0610695Y2 JP 1987145802 U JP1987145802 U JP 1987145802U JP 14580287 U JP14580287 U JP 14580287U JP H0610695 Y2 JPH0610695 Y2 JP H0610695Y2
Authority
JP
Japan
Prior art keywords
semiconductor element
metal
heat
package
metal base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987145802U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6450438U (enrdf_load_html_response
Inventor
隆 末吉
正行 馬郡
正広 木島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP1987145802U priority Critical patent/JPH0610695Y2/ja
Publication of JPS6450438U publication Critical patent/JPS6450438U/ja
Application granted granted Critical
Publication of JPH0610695Y2 publication Critical patent/JPH0610695Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
JP1987145802U 1987-09-24 1987-09-24 半導体素子収納用パッケージ Expired - Lifetime JPH0610695Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987145802U JPH0610695Y2 (ja) 1987-09-24 1987-09-24 半導体素子収納用パッケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987145802U JPH0610695Y2 (ja) 1987-09-24 1987-09-24 半導体素子収納用パッケージ

Publications (2)

Publication Number Publication Date
JPS6450438U JPS6450438U (enrdf_load_html_response) 1989-03-29
JPH0610695Y2 true JPH0610695Y2 (ja) 1994-03-16

Family

ID=31414710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987145802U Expired - Lifetime JPH0610695Y2 (ja) 1987-09-24 1987-09-24 半導体素子収納用パッケージ

Country Status (1)

Country Link
JP (1) JPH0610695Y2 (enrdf_load_html_response)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2515672Y2 (ja) * 1990-10-31 1996-10-30 京セラ株式会社 半導体素子収納用パッケージ
US20210134687A1 (en) * 2017-08-25 2021-05-06 Kyocera Corporation Electronic component mounting package and electronic device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5471572A (en) * 1977-11-18 1979-06-08 Fujitsu Ltd Semiconductor device
JPS61168640U (enrdf_load_html_response) * 1985-04-05 1986-10-20
JPH065699B2 (ja) * 1987-09-16 1994-01-19 日本電気株式会社 半導体装置

Also Published As

Publication number Publication date
JPS6450438U (enrdf_load_html_response) 1989-03-29

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