JPH0580695B2 - - Google Patents

Info

Publication number
JPH0580695B2
JPH0580695B2 JP13590487A JP13590487A JPH0580695B2 JP H0580695 B2 JPH0580695 B2 JP H0580695B2 JP 13590487 A JP13590487 A JP 13590487A JP 13590487 A JP13590487 A JP 13590487A JP H0580695 B2 JPH0580695 B2 JP H0580695B2
Authority
JP
Japan
Prior art keywords
control
channel
data
input
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP13590487A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63298660A (ja
Inventor
Kenji Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP13590487A priority Critical patent/JPS63298660A/ja
Publication of JPS63298660A publication Critical patent/JPS63298660A/ja
Publication of JPH0580695B2 publication Critical patent/JPH0580695B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP13590487A 1987-05-29 1987-05-29 入出力インタフェ−ス制御方式 Granted JPS63298660A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13590487A JPS63298660A (ja) 1987-05-29 1987-05-29 入出力インタフェ−ス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13590487A JPS63298660A (ja) 1987-05-29 1987-05-29 入出力インタフェ−ス制御方式

Publications (2)

Publication Number Publication Date
JPS63298660A JPS63298660A (ja) 1988-12-06
JPH0580695B2 true JPH0580695B2 (cs) 1993-11-10

Family

ID=15162543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13590487A Granted JPS63298660A (ja) 1987-05-29 1987-05-29 入出力インタフェ−ス制御方式

Country Status (1)

Country Link
JP (1) JPS63298660A (cs)

Also Published As

Publication number Publication date
JPS63298660A (ja) 1988-12-06

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