JPH0570867B2 - - Google Patents
Info
- Publication number
- JPH0570867B2 JPH0570867B2 JP63058492A JP5849288A JPH0570867B2 JP H0570867 B2 JPH0570867 B2 JP H0570867B2 JP 63058492 A JP63058492 A JP 63058492A JP 5849288 A JP5849288 A JP 5849288A JP H0570867 B2 JPH0570867 B2 JP H0570867B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- storage
- processor
- processors
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Multi Processors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63058492A JPH01232461A (ja) | 1988-03-14 | 1988-03-14 | 並列処理制御装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63058492A JPH01232461A (ja) | 1988-03-14 | 1988-03-14 | 並列処理制御装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01232461A JPH01232461A (ja) | 1989-09-18 |
| JPH0570867B2 true JPH0570867B2 (cs) | 1993-10-06 |
Family
ID=13085922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63058492A Granted JPH01232461A (ja) | 1988-03-14 | 1988-03-14 | 並列処理制御装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01232461A (cs) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61196349A (ja) * | 1985-02-27 | 1986-08-30 | Nec Corp | 共通バス制御方法 |
-
1988
- 1988-03-14 JP JP63058492A patent/JPH01232461A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01232461A (ja) | 1989-09-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4149242A (en) | Data interface apparatus for multiple sequential processors | |
| EP0243085A2 (en) | Coprocessor architecture | |
| JPH0479026B2 (cs) | ||
| JPH01269142A (ja) | 計算機システム | |
| JPS63201851A (ja) | バッファ記憶アクセス方法 | |
| US5440708A (en) | Microprocessor and storage management system having said microprocessor | |
| JPS5868286A (ja) | キヤツシユメモリおよびその作動方法 | |
| US6938118B1 (en) | Controlling access to a primary memory | |
| JPH0570867B2 (cs) | ||
| JPS60205760A (ja) | メモリ制御装置 | |
| JP2643116B2 (ja) | 主記憶制御装置 | |
| JPS63240651A (ja) | キヤツシユメモリ | |
| JP2647092B2 (ja) | マルチプロセツサシステム | |
| JP2778623B2 (ja) | プリフェッチ制御装置 | |
| JP2581144B2 (ja) | バス制御装置 | |
| JPS63142416A (ja) | 入出力制御方式 | |
| JPH07175768A (ja) | デュアルcpuシステム | |
| EP4150467A1 (en) | Two-way interleaving in a three-rank environment | |
| JPH04245346A (ja) | マイクロコンピュータシステム | |
| JPH02114342A (ja) | 情報処理装置 | |
| JPH01154272A (ja) | マルチプロセッサ装置 | |
| JPH0236443A (ja) | 拡張記憶制御方式 | |
| JPS6074074A (ja) | 優先順位制御方式 | |
| JPH04291642A (ja) | キャッシュ制御方式 | |
| JPH0612363A (ja) | メモリ制御装置およびマルチプロセッサシステム |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |