JPH0567070B2 - - Google Patents

Info

Publication number
JPH0567070B2
JPH0567070B2 JP61245823A JP24582386A JPH0567070B2 JP H0567070 B2 JPH0567070 B2 JP H0567070B2 JP 61245823 A JP61245823 A JP 61245823A JP 24582386 A JP24582386 A JP 24582386A JP H0567070 B2 JPH0567070 B2 JP H0567070B2
Authority
JP
Japan
Prior art keywords
wiring board
semiconductor chip
wiring
board
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61245823A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6399559A (ja
Inventor
Myoshi Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61245823A priority Critical patent/JPS6399559A/ja
Publication of JPS6399559A publication Critical patent/JPS6399559A/ja
Publication of JPH0567070B2 publication Critical patent/JPH0567070B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards

Landscapes

  • Combinations Of Printed Boards (AREA)
JP61245823A 1986-10-15 1986-10-15 半導体装置 Granted JPS6399559A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61245823A JPS6399559A (ja) 1986-10-15 1986-10-15 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61245823A JPS6399559A (ja) 1986-10-15 1986-10-15 半導体装置

Publications (2)

Publication Number Publication Date
JPS6399559A JPS6399559A (ja) 1988-04-30
JPH0567070B2 true JPH0567070B2 (enrdf_load_stackoverflow) 1993-09-24

Family

ID=17139384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61245823A Granted JPS6399559A (ja) 1986-10-15 1986-10-15 半導体装置

Country Status (1)

Country Link
JP (1) JPS6399559A (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629459A (ja) * 1992-07-08 1994-02-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3036976B2 (ja) * 1992-07-24 2000-04-24 日本電気株式会社 マルチチップモジュール
JP3057130B2 (ja) 1993-02-18 2000-06-26 三菱電機株式会社 樹脂封止型半導体パッケージおよびその製造方法
US5362986A (en) * 1993-08-19 1994-11-08 International Business Machines Corporation Vertical chip mount memory package with packaging substrate and memory chip pairs
KR100587024B1 (ko) * 1998-12-24 2007-12-12 주식회사 하이닉스반도체 3차원 적층형 마이크로 비지에이 패키지
JP7007012B2 (ja) * 2017-09-12 2022-01-24 Ｎｅｃプラットフォームズ株式会社 電子機器、モジュール基板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713999Y2 (enrdf_load_stackoverflow) * 1977-05-24 1982-03-20

Also Published As

Publication number Publication date
JPS6399559A (ja) 1988-04-30

Similar Documents

Publication Publication Date Title
US6476500B2 (en) Semiconductor device
KR101009121B1 (ko) 삽입 기판에 접속하기 위한 중간 접촉자를 갖는마이크로일렉트로닉 장치, 및 중간 접촉자를 갖는마이크로일렉트로닉 장치를 패키징하는 방법
US6376914B2 (en) Dual-die integrated circuit package
TWI515868B (zh) 可重組的層疊封裝
KR101409946B1 (ko) 적층형 마이크로전자 패키지
JPS6355213B2 (enrdf_load_stackoverflow)
JP2002204053A (ja) 回路実装方法、回路実装基板及び半導体装置
JPS5892230A (ja) 半導体装置
JP4538830B2 (ja) 半導体装置
US20030042591A1 (en) Electronic component with at least two stacked semiconductor chips, and fabrication method
JPH0567070B2 (enrdf_load_stackoverflow)
KR20150122679A (ko) 위치 반전을 갖는 마이크로 전자 유닛 및 패키지
JPH11260999A (ja) ノイズを低減した積層半導体装置モジュール
EP0221496A2 (en) Integrated circuit package
JPH10242380A (ja) 半導体装置およびその製造方法
JPH038110B2 (enrdf_load_stackoverflow)
JPH09107067A (ja) 半導体装置
JPH0582582A (ja) 半導体装置
JPH0621328A (ja) 半導体素子の実装方法
JPH0533829B2 (enrdf_load_stackoverflow)
JP3813489B2 (ja) 積層型半導体装置
JPH0531826B2 (enrdf_load_stackoverflow)
JPS6267828A (ja) 半導体デバイスの実装構造
US20240178185A1 (en) Semiconductor package
KR100352115B1 (ko) 반도체패키지