JPS6399559A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6399559A
JPS6399559A JP61245823A JP24582386A JPS6399559A JP S6399559 A JPS6399559 A JP S6399559A JP 61245823 A JP61245823 A JP 61245823A JP 24582386 A JP24582386 A JP 24582386A JP S6399559 A JPS6399559 A JP S6399559A
Authority
JP
Japan
Prior art keywords
wiring board
wiring
semiconductor
semiconductor chips
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61245823A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0567070B2 (enrdf_load_stackoverflow
Inventor
Miyoshi Yoshida
吉田　美義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61245823A priority Critical patent/JPS6399559A/ja
Publication of JPS6399559A publication Critical patent/JPS6399559A/ja
Publication of JPH0567070B2 publication Critical patent/JPH0567070B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards

Landscapes

  • Combinations Of Printed Boards (AREA)
JP61245823A 1986-10-15 1986-10-15 半導体装置 Granted JPS6399559A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61245823A JPS6399559A (ja) 1986-10-15 1986-10-15 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61245823A JPS6399559A (ja) 1986-10-15 1986-10-15 半導体装置

Publications (2)

Publication Number Publication Date
JPS6399559A true JPS6399559A (ja) 1988-04-30
JPH0567070B2 JPH0567070B2 (enrdf_load_stackoverflow) 1993-09-24

Family

ID=17139384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61245823A Granted JPS6399559A (ja) 1986-10-15 1986-10-15 半導体装置

Country Status (1)

Country Link
JP (1) JPS6399559A (enrdf_load_stackoverflow)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645519A (ja) * 1992-07-24 1994-02-18 Nec Corp マルチチップモジュール
US5362986A (en) * 1993-08-19 1994-11-08 International Business Machines Corporation Vertical chip mount memory package with packaging substrate and memory chip pairs
US5463251A (en) * 1992-07-08 1995-10-31 Mitsubishi Denki Kabushiki Kaisha Power semiconductor package having improved durability
US6191493B1 (en) 1993-02-18 2001-02-20 Mitsubishi Denki Kabushiki Kaisha Resin seal semiconductor package and manufacturing method of the same
KR100587024B1 (ko) * 1998-12-24 2007-12-12 주식회사 하이닉스반도체 3차원 적층형 마이크로 비지에이 패키지
WO2019054190A1 (ja) * 2017-09-12 2019-03-21 Ｎｅｃプラットフォームズ株式会社 電子機器、モジュール基板

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53160750U (enrdf_load_stackoverflow) * 1977-05-24 1978-12-16

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53160750U (enrdf_load_stackoverflow) * 1977-05-24 1978-12-16

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463251A (en) * 1992-07-08 1995-10-31 Mitsubishi Denki Kabushiki Kaisha Power semiconductor package having improved durability
JPH0645519A (ja) * 1992-07-24 1994-02-18 Nec Corp マルチチップモジュール
US6191493B1 (en) 1993-02-18 2001-02-20 Mitsubishi Denki Kabushiki Kaisha Resin seal semiconductor package and manufacturing method of the same
US5362986A (en) * 1993-08-19 1994-11-08 International Business Machines Corporation Vertical chip mount memory package with packaging substrate and memory chip pairs
KR100587024B1 (ko) * 1998-12-24 2007-12-12 주식회사 하이닉스반도체 3차원 적층형 마이크로 비지에이 패키지
WO2019054190A1 (ja) * 2017-09-12 2019-03-21 Ｎｅｃプラットフォームズ株式会社 電子機器、モジュール基板
JP2019050339A (ja) * 2017-09-12 2019-03-28 Ｎｅｃプラットフォームズ株式会社 電子機器、モジュール基板

Also Published As

Publication number Publication date
JPH0567070B2 (enrdf_load_stackoverflow) 1993-09-24

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