JPH0533829B2 - - Google Patents

Info

Publication number
JPH0533829B2
JPH0533829B2 JP61250111A JP25011186A JPH0533829B2 JP H0533829 B2 JPH0533829 B2 JP H0533829B2 JP 61250111 A JP61250111 A JP 61250111A JP 25011186 A JP25011186 A JP 25011186A JP H0533829 B2 JPH0533829 B2 JP H0533829B2
Authority
JP
Japan
Prior art keywords
wiring board
wiring
semiconductor
board
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61250111A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63104361A (ja
Inventor
Myoshi Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61250111A priority Critical patent/JPS63104361A/ja
Publication of JPS63104361A publication Critical patent/JPS63104361A/ja
Publication of JPH0533829B2 publication Critical patent/JPH0533829B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
JP61250111A 1986-10-20 1986-10-20 半導体装置 Granted JPS63104361A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61250111A JPS63104361A (ja) 1986-10-20 1986-10-20 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61250111A JPS63104361A (ja) 1986-10-20 1986-10-20 半導体装置

Publications (2)

Publication Number Publication Date
JPS63104361A JPS63104361A (ja) 1988-05-09
JPH0533829B2 true JPH0533829B2 (enrdf_load_stackoverflow) 1993-05-20

Family

ID=17202988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61250111A Granted JPS63104361A (ja) 1986-10-20 1986-10-20 半導体装置

Country Status (1)

Country Link
JP (1) JPS63104361A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362986A (en) * 1993-08-19 1994-11-08 International Business Machines Corporation Vertical chip mount memory package with packaging substrate and memory chip pairs
JP3461204B2 (ja) * 1993-09-14 2003-10-27 株式会社東芝 マルチチップモジュール

Also Published As

Publication number Publication date
JPS63104361A (ja) 1988-05-09

Similar Documents

Publication Publication Date Title
US6376914B2 (en) Dual-die integrated circuit package
US7095104B2 (en) Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same
KR101009121B1 (ko) 삽입 기판에 접속하기 위한 중간 접촉자를 갖는마이크로일렉트로닉 장치, 및 중간 접촉자를 갖는마이크로일렉트로닉 장치를 패키징하는 방법
US6620648B2 (en) Multi-chip module with extension
JPS6355213B2 (enrdf_load_stackoverflow)
US5227995A (en) High density semiconductor memory module using split finger lead frame
JPS61101067A (ja) メモリモジユ−ル
CN101322246A (zh) 层叠式微电子封装
US9219050B2 (en) Microelectronic unit and package with positional reversal
EP0560487B1 (en) Semiconductor device having a lead frame
JPS62109333A (ja) 半導体パツケ−ジ
JPH0567070B2 (enrdf_load_stackoverflow)
JPH0533829B2 (enrdf_load_stackoverflow)
US20040238924A1 (en) Semiconductor package
JPS6159860A (ja) 半導体集積回路装置の製造方法
JPH038110B2 (enrdf_load_stackoverflow)
JPH09107067A (ja) 半導体装置
JPH0531826B2 (enrdf_load_stackoverflow)
JPH0531827B2 (enrdf_load_stackoverflow)
JP2000260931A (ja) 半導体装置およびその製造方法
JP2507855B2 (ja) 半導体装置
JPS6281721A (ja) 半導体装置
JPH02244753A (ja) 集積回路装置
JPS63126259A (ja) 半導体装置の製造方法
JPH11204564A (ja) 半導体装置の製造方法および半導体装置