JPH0558511B2 - - Google Patents
Info
- Publication number
- JPH0558511B2 JPH0558511B2 JP61112264A JP11226486A JPH0558511B2 JP H0558511 B2 JPH0558511 B2 JP H0558511B2 JP 61112264 A JP61112264 A JP 61112264A JP 11226486 A JP11226486 A JP 11226486A JP H0558511 B2 JPH0558511 B2 JP H0558511B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- adder
- signal
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61112264A JPS62267675A (ja) | 1986-05-16 | 1986-05-16 | 集積回路評価回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61112264A JPS62267675A (ja) | 1986-05-16 | 1986-05-16 | 集積回路評価回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62267675A JPS62267675A (ja) | 1987-11-20 |
| JPH0558511B2 true JPH0558511B2 (enrdf_load_stackoverflow) | 1993-08-26 |
Family
ID=14582349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61112264A Granted JPS62267675A (ja) | 1986-05-16 | 1986-05-16 | 集積回路評価回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62267675A (enrdf_load_stackoverflow) |
-
1986
- 1986-05-16 JP JP61112264A patent/JPS62267675A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62267675A (ja) | 1987-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5811983A (en) | Test ring oscillator | |
| JPH02105074A (ja) | 半導体集積回路 | |
| US6223314B1 (en) | Method of dynamic on-chip digital integrated circuit testing | |
| IT1100622B (it) | Dispositivo per la prova di circuiti integrati | |
| JPH05281304A (ja) | テスト回路を内蔵したアナログ・ディジタル混在マスタ | |
| US6529033B1 (en) | Area efficient clock inverting circuit for design for testability | |
| JPS63139266A (ja) | 大規模集積回路のテストデ−タ作成方法 | |
| Khakbaz et al. | Concurrent error detection and testing for large PLA's | |
| JPH0989980A (ja) | 半導体集積回路およびその評価方法 | |
| JPH0558511B2 (enrdf_load_stackoverflow) | ||
| JPS5883282A (ja) | 電子的アセンブリのテスト方法および装置 | |
| US6092226A (en) | Fabrication of test logic for level sensitive scan on a circuit | |
| JPH01111365A (ja) | 半導体集積回路 | |
| JPH04160377A (ja) | 半導体集積回路 | |
| JPH01129432A (ja) | 集積回路 | |
| JP3395773B2 (ja) | 半導体装置 | |
| JPS63271966A (ja) | 半導体集積回路 | |
| WO1992013281A1 (en) | Method to reduce test vectors/test time in devices using equivalent blocks | |
| JPH04296112A (ja) | レジスタ回路 | |
| JPH0750149B2 (ja) | シフトレジスタのテスト方法 | |
| JPH0526981A (ja) | 半導体集積回路のテスト用回路 | |
| JP2972515B2 (ja) | 入出力バッファテスト回路 | |
| KR100271259B1 (ko) | 반도체 집적회로 및 그의 평가방법 | |
| JPS60174963A (ja) | 電子パツケ−ジ試験回路 | |
| JP3086226B2 (ja) | 半導体装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |